SU1481902A1 - Unit for determination of erasing locator polynomial in decoding non-binary block codes - Google Patents

Abstract

The invention relates to a technique for transmitting discrete information and can be applied in decoding devices of data transmission equipment. The purpose of the invention is to increase speed and simplify ya. The device contains registers 1 ₁ ÷ 1 _D-1 , blocks 2 ₁ ÷ 2 _D-3 elements OR, first and second adders 3, 4, multiplication unit 5, additional register 6, switch 7 and control unit 8 containing a distributor 9 pulses and blocks 10.1 ÷ 10. (D-2) elements I. 1 Il.

Description

4 00

SO O HCHE

The invention relates to a technique for transmitting discrete information and can be applied in decoding devices of data transmission equipment.

The purpose of the invention is to increase the speed and simplify the device.

The drawing shows a structural electrical circuit of the device.

A device for determining a multi-member of erase locators when decoding non-binary block codes contains registers 1, -lj., Blocks 2..., OR elements, first 3 and second 4 adders, multiplication unit 5, additional register 6, switch 7 and unit. 8 controls, containing a distributor of 9 pulses and blocks g) of elements I.

The device works as follows.

The device calculates the coefficients of the erase locator polynomial.

I

And Q (Z) P (1 + X - Z).

) J Machined Erase Locators

/ C sequentially fed to the input device. Calculations are based on recursive formulas. If for (k-1) steps the erase locator polynomial is defined

,,

+ a

-g

Z g + .., + a, Z + l,

the coefficient of the erase polynomial on the K step

- one

a0

 but

 +

a., ak, + X; K

aV X, K. “k,.

To calculate, it is required to perform k operations of addition and (k-1) multiplication operations in the Galois field. The number of correctable erasures for a code does not exceed (d-1), where d is the code distance. The number of binary strokes in processing each erase locator is determined by the number of multiply operations. The first erase locator is processed in one clock, the second also in one clock, the third in two binary steps, the fourth in three, and so on. In the first cycle of processing each locator erase switch

0

five

0

five

0

five

0

five

0

five

7 connect the outputs of the last register I to the multiplier 5 in the Ralua field (and for the rest of the time the outputs of the additional register: 6). This mode of operation of the switch 7 is determined by the control signal from the first output of the distributor 9 of the control unit 8. Also by this signal from the first output of the distributor

9, filed on the first clock input of the last register ,,, is the recording of information from the output of the second adder 4 to the register

When processing the second erase locator, a single signal from the second output of the distributor 9 is fed to the first combined inputs of the last i block 10 (j 2) elements I. During processing (d-2) of the locator, a single signal from (d-2) the output of the distributor 9 is fed to the first the combined inputs of the second block 10z elements I. When processing (dl) -ro locator, a single signal from (dl) -ro output of the distributor 9 is fed to the inputs of the first block

10, elements I. In the initial state, all registers 1 are zero. The value of the first erase locator through the input and output of the second adder 4 is written to the register ij,, to the other registers 1,,. f. 1 (j-a, zeros are recorded, since the first inputs of the blocks 10 i, ... 1 O (j g) of the AND elements from the outputs of the distributor 9 are given zero signals.

In the first processing cycle of the second locator, its value is added in the second adder 4 to the value of the first locator from the register 1j output, and the resulting sum is written to the register Ij-f. At the same time, the value of the second locator is multiplied in block 5 multiplying in the Galois field by the value of the first locator fed from the output of the switch 7, the resulting product is added in the adder 3 with zero from the register output and through the block 10.2 of the elements I is written to the register is over. The remaining erasers are processed in the same way. At the same time, when processing the remaining erasers on the second and following work orders to the second input of block 5

five

multiplying the n field, the information is fed from the output of the additional register b through the switch /. The output of the first adder 5 according to the signals of the distributor 9 alternately through the blocks 1 0 (,.),. . ., 10, AND elements and blocks 2 3, ... 2, OR elements are connected to inputs of registers Ij. 2, ..., 1. After processing all erasure locators from the outputs of the registers l, .., lj-i get the desired result.

The calculation of the first and second coefficients of the erase locator polynomial is performed simultaneously. Such a construction of the device for determining the erase locator polynomial makes it possible to process (d-1) and (d-l) (d-2) erasure cata stan + 1

binary ticks instead of d (d-l) / 2 in the known device, i.e. on () tact faster.

Claims (1)

Invention Formula A device for determining the erase locator polynomial when decoding nonbinary block codes containing (d-) registers, a-3 blocks of OR elements, an additional register whose outputs are connected to the first inputs of the switch, a multiplication unit whose first inputs are the inputs of the device, the first adder The outputs of which are connected to the corresponding inputs of the control unit, the first output of which is 819026 The second and the second clock of the switch, the second outputs of the b :: ok control are connected to the first inputs of the corresponding blocks of OR elements, the outputs of which are connected to the inputs of the corresponding blocks of OR elements, the outputs of which are connected to the inputs of the corresponding registers, except the first and (, -ro, the outputs of the registers, except for (d-2) -ro and (d-1) -th, are connected to the second inputs of the corresponding OR blocks and are the first outputs of the device, the third outputs of the block The 15 controls are connected to the corresponding inputs of the first register, the second adder, which is different from the fact that, in order to improve speed and simplify the device, 20, the first input (dl) -ro of the register is connected to the first output of the control unit, the outputs () -ro of the register are connected to the inputs of the additional register, the first inputs of the first adder and are the second outputs of the device, the outputs (dl) -ro of the register are connected by the first inputs the second adder, the third inputs of the switch and are the third outputs of the device, the second inputs of the second adder are connected to the first inputs of the multiplication unit, the outputs of the second adder are connected to the second inputs (dl) -ro of the register, output The switch 35 is connected to the second inputs of the multiplication unit, the outputs of which are connected to the second inputs of the first adder. 25