JPH0764810A - Galois field computing element - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of a multiplier and a syndrome computing element. CONSTITUTION:Outputs of partial product registers 71 to 78 are given to a coefficient device 81 and adders 82 to 88. Switches 92, 93, 94, and 96 give the outputs of coefficient devices 81 to 108 to adders 82 to 88 at the time of multiplying operation. Then, the multiplication result is obtained from the adder 88. Switches 92, 93, 94, and 96 give the outputs of registers 112, 113, 115, and 118 at the time of syndrome operation. Contents of partial product registers 71, 74, 76, and 77 are set to zero. Thus, syndromes so to S4 are held in registers 112, 113, 115, and 118. Since multi-plication and syndrome operation are realized with common circuits, the circuit scale is considerably reduced.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Galois field arithmetic unit suitable as an error correction circuit for digital audio equipment and the like.

[0002]

2. Description of the Related Art In recent years, error correcting codes have been applied to improve the reliability of various digital systems. Various types of error correction codes are adopted depending on the system. Especially, Reed sol on Galois field
The omon code (hereinafter referred to as RS code) has low redundancy,
It is an important code widely used in the fields of CD (compact disc), DAT (digital audio tape) and satellite communication.

By the way, in a digitized information sequence, it is generally convenient to use a polynomial expression. For example, the Galois field multiplication A × B = C can be expressed by the polynomial expression shown in the following expression (1).

C = ((((((B · A7) · α + B · A6) · α + B · A5) · α + B · A 4) · α + B · A3) · α + B · A2) · α + B · A1) · α + B ・A0 ... (1) A polynomial calculation circuit basically uses an exclusive OR circuit and a gate circuit as an adder circuit, and performs calculation by matching the time of each coefficient of A and B by a register. FIG. 3 is a block diagram for explaining the operation of the multiplier that realizes the calculation shown in the above equation (1).

The input registers 21 to 28 are supplied with the coefficients A7 to A0 of the polynomial A, respectively. The product of the coefficient A7 from the input register 21 and the polynomial B is given to the coefficient unit 1 and multiplied by α, and then added by the adder 12 with the result of the product of the coefficient A6 from the input register 22 and the polynomial B. This addition result is multiplied by α and given to the adder 13 to be added to the product of the coefficient A5 and the polynomial B. After that, similarly, the product of the polynomials A and B is multiplied by α times the output of the adder at the preceding stage. The addition result from the adder 18 is stored in the register 8 as the multiplication result of the Galois field by the polynomial expression.
To store. Thus, the above formula (1) is realized.

By the way, the position and value of the error are obtained by obtaining the remainder obtained by dividing the received code polynomial U by the generator polynomial, that is, the syndrome polynomial. In the BCH code, the syndrome can be obtained by substituting the element of the extension field, which is the root of the generator polynomial, into the received code polynomial. For example, assuming that the number of data is 28 and the number of parity is 4, the following equation (2) ) Through (5). Note that Ui represents a data symbol, and α is an element of the extension field.

[0007] FIG. 4 is a block diagram for explaining the operation of the syndrome computing unit that implements the computations represented by the equations (2) to (5).

First, the symbol U0 of the input data is input to the input registers 61 to 67. Input registers 61, 62, 64,
The output of 67 is given as one input to the adders 31, 32, 34 and 37, respectively. Since the contents of the registers 41 to 44 are 0 in the initial state, the other inputs of the adders 31, 32, 34 and 37 are 0, and the symbols U0 are stored in the registers 41 to 44, respectively.

Next, the symbol U1 is transferred to the input registers 61 through 61.
It is input to 67 and given to the adders 31, 32, 34 and 37. The output of the register 42 is given to the adder 32 via the coefficient unit 51, the output of the register 43 is given to the adder 34 via the coefficient units 52 and 53, and the output of the register 44 is added via the coefficient units 54 to 56. Give to vessel 37. Therefore, the other inputs of the adders 31, 32, 34 and 37 are U0, α × U0, α × α × U0 and α × α × α × U0, respectively. The adders 31, 32, 34 and 37 add the two inputs and store them in the registers 41, 42, 43 and 44, respectively. The contents of the registers 41, 42, 43, and 44 at this point are shown in the following equations (6) to (9), respectively.

[0010] Thereafter, similarly, the symbols U2 to U28 are sequentially input to the input registers 61 to 67. The contents of the registers 41 to 44 are sequentially updated, and eventually the syndrome coefficients S0 to S3 of the above equations (2) to (5) are obtained in the registers 41 to 44, respectively.

By the way, an error correction circuit of this kind using the operation on the Galois field is implemented as an LSI. Since the operating frequency was low in the early stages of LSI, pipeline processing in which circuits were operated in parallel was effective in order to enable high-speed calculation. However, at present, the circuit operation is accelerated due to the progress of the LSI manufacturing process, and it is rather important to adopt a fine pattern to realize many functions on a one-chip LSI. When designing a circuit using a technique such as a standard cell, the most effective means for reducing the circuit area is to design one block with as many functions as possible and to optimize the pattern of that block. . However, the configurations of FIGS. 3 and 4 have a large circuit scale, which is disadvantageous in that an error correction circuit having a Galois field multiplier and a syndrome calculator is mounted on an LSI.

[0012]

As described above, in the above-mentioned conventional Galois field arithmetic unit, the circuit scale is large and L is large.
There has been a problem that the board area occupation rate is high in the case of SI, which is disadvantageous for LSI.

According to the present invention, by sharing the circuit block of the Galois field multiplier and the syndrome calculator,
An object is to provide a Galois field arithmetic unit capable of reducing the circuit area on SI.

[Constitution of Invention]

A Galois field arithmetic unit according to the present invention comprises a plurality of α multiplication means for multiplying an element α of an extension field of a Galois field and a number of Galois fields corresponding to the bit width of multiplicand data. Adder means, a plurality of partial product holding means for holding a partial product which is a product of multiplier data and each bit of the multiplicand data, and a portion corresponding to a predetermined bit of the multiplicand data stored in the partial product holding means A multiplication control in which the product is given to the α multiplying means to multiply the element α of the extension field, and the multiplication result is given to the adding means to add with the partial product corresponding to the next bit to perform Galois field multiplication. Means and the contents of a predetermined plurality of partial product holding means among the plurality of partial product holding means are set to 0, whereby the multiplication control means multiplies the nth power of the element α of the Galois field extension field by the power Means and holding said partial product By giving data symbols to a predetermined plurality of partial product holding means of the means and controlling the multiplication control means to give the output of the exponentiation means to the addition means instead of the output of the α multiplication means, And a switching means for obtaining the syndrome from the adding means.

[0015]

In the present invention, the multiplication control means performs the Galois field multiplication using the partial product holding means, the α multiplication means and the addition means. The exponentiation means makes it possible to multiply α to the nth power by setting the contents of the plurality of partial product holding means to 0 and inputting the output of the α multiplication means to the α multiplication means as it is. The switching means provides the output of the exponentiation means to the addition means to obtain the syndrome from the addition means. That is, the exponentiation means and the switching means share the partial product holding means, the α multiplication means, and the addition means to perform multiplication and syndrome calculation, and reduce the scale of the circuit having the multiplication and syndrome calculation functions.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a Galois field arithmetic unit according to the present invention.

The highest to lowest partial product registers 71 to
78 is the polynomial A or the received code polynomial U that is the multiplicand, respectively.
Enter i. That is, when used as a Galois field multiplier, the partial product registers 71 to 78 store the products of the coefficients A1 to A8 of the polynomial A and the polynomial B, which is a multiplier, respectively. When used as a syndrome calculator, the received code polynomial Ui is sequentially input as the multiplier B.
In this case, the multiplicand A is “69” Hex (01
101001), the partial product registers 71, 74, 7
The contents of 6 and 77 are set to 0.

The outputs of the partial product registers 71 to 78 are given to the coefficient unit 81 and the adders 82 to 88, respectively. The adders 82 to 88 are 2
Add input and output. Coefficient unit 81 is a partial product register 71
The output of is multiplied by α and the adder is added through the input terminal a of the switch 92.
Give to 82. The outputs of the adders 82, 83, 85, 88 are given to the registers 112, 113, 115, 118, respectively, and the registers 112, 113 are given.
, 115 and 118 are applied to the input terminals b of the switches 92, 93, 94 and 96, respectively. The outputs of the adders 82, 83 and 85 are given to the input terminals a of the switching devices 93, 94 and 96. Switch 92, 93, 9
4 and 96 are controlled by a switching signal. When performing a multiplication operation, the input end a is selected, when performing the syndrome operation, the input end b is selected, and the signals from the selected input ends are added to the adder. 82 and coefficient units 103, 104 and 106.

The coefficient units 103, 104 and 106 multiply the input signals by α and give them to the adders 83, 84 and 86, respectively. Adder 84,
86 outputs the outputs to the coefficient multipliers 105 and 107, respectively. Coefficient unit 10
5 and 107 multiply the input signal by α and adder 85 and 87 respectively
, And the adder 87 gives the output to the coefficient unit 108. The coefficient unit 108 multiplies the input signal by α and supplies it to the adder 88. The registers 112, 113, 115, 11
8 is to be cleared by a clear signal. Further, at the time of syndrome calculation, the content of the uppermost partial product register 71 is 0 or undefined and is not used.

Next, the operation of the embodiment thus constructed will be described with reference to FIG. FIG. 2 is a block diagram showing an equivalent circuit during the syndrome calculation operation.

First, it is assumed that the multiplier operates as a Galois field multiplier. In this case, the switches 92, 93, 94 and 96 select the input end a. The multiplicand coefficients A7 to A0 are given to the partial product registers 71 to 78, respectively.
78 is the partial product of A7 ・ B, A6 ・ B, A5 ・
B, A4 ・ B, A3 ・ B, A2 ・ B, A1 ・ B, A0 ・
B is stored. The highest-order partial product A7 · B is given to the coefficient unit 81, multiplied by α, and given to the adder 82 via the switching unit 92.
The adder 82 adds the partial products A6.B from the partial product register 72 and the output of the coefficient unit 81 and outputs the result to the switch 93.

Since the switches 92, 93, 94 and 96 select the input terminal a, the outputs of the adders 82 to 87 are respectively output from the coefficient unit 103.
Through 108 to the adders 83 through 88. The output ((B · A7) · α + B · A6) of the adder 82 is multiplied by α by the coefficient unit 103 and given to the adder 83. Thereafter, similarly, the outputs of the adders 83 to 87 are multiplied by α and are given to the next adders 84 to 88. Eventually, in this case, a circuit equivalent to that of FIG. 3 is constructed, and the multiplication result of the above equation (1) is stored in the register 118.

Next, it is assumed that it operates as a syndrome calculator. In this case, the partial product registers 71 to 78
The received code polynomial Ui is sequentially input as a multiplier B to the.
Further, the multiplicand A is 011 in each of the registers 71 to 78.
01001 (= “69”) is given. Therefore, the partial products held in the partial product registers 71, 74, 76, 77 are 0,
Symbols will be output only from the partial product registers 72, 73, 75, 78. Further, when the syndrome calculation is started, the registers 112, 113, 115 and 118 are cleared by a clear signal.

When the syndrome calculation is instructed, the switchers 92, 93, 94 and 96 select the input end b and register the register 112.
, 113, 115, and 118 outputs the output of adder 82 and coefficient unit 1 respectively.
Give to 03, 104 and 106. The coefficient units 103, 104 and 106 multiply the outputs of the registers 113, 115 and 118 by α and adder 83,
Give to 84, 86. Adders 84, 86, 87 are partial product registers 7
Since the contents of 4, 76 and 77 are 0, the coefficient units 104, 106 and 1
The output of 07 is output as it is to the coefficient units 105, 107 and 108. Further, the coefficient units 105, 107 and 108 are provided with the input signal α
It is multiplied and output to adders 85, 87, 88.

That is, the outputs of the partial product registers 71, 74, 76, 77 are set to 0, and the selectors 92, 93, 94, 96 select the input end b, so that the output of the register 112 remains unchanged. 82, the output of the register 113 is multiplied by α and given to the adder 83, the output of the register 115 is multiplied by α 2 and given to the adder 85, and the output of the register 118 is given by α.
Is multiplied by 3 and is given to the adder 88. Therefore, in this case, the equivalent circuit shown in FIG. 2 is configured.

At the start of calculation, the registers 112, 113, 115
Since the contents of 118 are cleared, the switching device 92,
0 is added from the coefficient units 103, 105, 108 to the adders 82, 83, 85,
Given to 88. The symbol U0 input to the partial product registers 72, 73, 75 and 78 is directly applied to the registers 112, 113, 115 and 118 via the adders 82, 83, 85 and 88, respectively. Next, the symbol U1 is transferred to the partial product register 72,
Input in 73, 75, 78. Registers 112, 113, 115, 11
As shown in FIG. 2, the output of 8 is given to adders 82, 83, 85, 88 after being multiplied by 1 times, α times, α times squared, and α times cubed, respectively. 83, 85, and 88 are the output of the register 112 and the outputs of the coefficient multipliers 103, 105, and 108, and the partial product register 7 respectively.
The symbols Ui from 2, 73, 75 and 78 are added and output.

That is, the output of the partial product register 72 is the adder.
Cumulative addition is performed by giving it to the adder 82 via 82, the register 112 and the switch 92. By sequentially inputting the symbols U0 to U27, the syndrome S0 shown in the above equation (2) can be obtained in the register 112.

The output of the partial product register 72 is an adder.
By giving it to the adder 83 via 83, the register 113, the switch 93 and the coefficient unit 103, the cumulative addition is performed while multiplying by α. Therefore, by sequentially inputting the symbols U0 to U27, the syndrome S1 shown in the above equation (3) is stored in the register 113.

The output of the partial product register 75 is an adder.
85, register 115, switching unit 94, coefficient unit 104, adder 84
And by giving it to the adder 85 via the coefficient unit 105,
Cumulative addition is performed while multiplying α by 2. Therefore, the symbol U
By sequentially inputting 0 to U27, the syndrome S2 shown in the above equation (4) is stored in the register 115.

Similarly, the output of the partial product register 78 is the adder 88, the register 118, the switching unit 96, the coefficient unit 106, and the adder.
By giving it to the adder 88 via the 86, the coefficient unit 107, the adder 87 and the coefficient unit 108, cumulative addition is performed while multiplying α to the third power. Therefore, by sequentially inputting the symbols U0 to U27, the syndrome S3 shown in the above equation (5) is stored in the register 118.

As described above, in the present embodiment, the switches 92, 93, 94, and 96 are switched between the multiplication operation and the syndrome operation, thereby sharing the circuit and performing the Galois field multiplication and the syndrome operation. Is going. Since the circuit is shared, it is possible to reduce the circuit scale as compared with the case where the Galois field multiplier and the syndrome calculator are separately configured, and it is possible to reduce the board occupation area in the case of LSI implementation. it can. As a result, the Galois field multiplier and the syndrome calculator can be configured only by occupying the area required for the configuration of the multiplier.

In this embodiment, during the syndrome calculation, the outputs of the switches 92, 93, 94 and 96 are multiplied by α to the 0th power, α times, α to the second power and α to the third power. However, it is also possible to switch the value of n by an external signal using a coefficient unit that multiplies an arbitrary multiple α to the nth power. Then, there is an advantage that it is possible to easily cope with an increase in the number of parities and an error location calculation.

[0033]

As described above, according to the present invention, it is possible to reduce the circuit area on the LSI by sharing the circuit block of the Galois field multiplier and the syndrome calculator. Have.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a Galois field arithmetic unit according to the present invention.

FIG. 2 is an explanatory diagram for explaining an example.

FIG. 3 is a block diagram for explaining the operation of a Galois field multiplier.

FIG. 4 is a block diagram for explaining a syndrome calculation operation.

[Explanation of symbols]

71 to 78 ... partial product register, 81, 103 to 108 ... coefficient unit, 82
~ 88 ... Adder, 92-96 ... Switch, 112-118 ... Register

Claims (2)

[Claims] 1. A plurality of α multiplication means for multiplying an element α of an extension field of a Galois field, an addition means for a Galois field of a number corresponding to a bit width of multiplicand data, and each bit of multiplier data and multiplicand data A plurality of partial product holding means for holding a partial product that is a product, and a partial product corresponding to a predetermined bit of the multiplicand data stored in the partial product holding means is given to the α multiplying means to generate an element of the extension field. multiplication control means for multiplying α and giving a multiplication result to the addition means to add with a partial product corresponding to the next bit to perform Galois field multiplication; and a predetermined one of the plurality of partial product holding means. By setting the contents of the plurality of partial product holding means of 0 to 0, exponentiation means for multiplying the nth power of the element α of the Galois field extension field by the multiplication control means, and a predetermined plurality of the partial product holding means The partial product holding means And a switching means for obtaining the syndrome from the adding means by giving the output of the exponent means to the adding means instead of the output of the α multiplying means by giving the symbol of the data and controlling the multiplication control means. A Galois field arithmetic unit characterized by the above. 2. The Galois field arithmetic unit according to claim 1, further comprising a power control means for controlling n of the power means by an external signal.