JP2963018B2 - Reed-Solomon error correction code decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to error correction decoding and encoding of Reed-Solomon codes used for correcting random errors. The present invention relates to a high-speed operation circuit used for high-speed decoding of a high-order Reed-Solomon code, which is particularly excellent in error correction capability.

[0002]

2. Description of the Related Art Algebraic processing required for encoding and decoding Reed-Solomon codes will be described.

The theory of the Reed-Solomon code itself is described in Imai's "Code Theory" (IEICE),
Richard E. Blahut's "Theory and practice of error
control codes "(Addison-Wesley), G. Clark and J. Cain
"Error-Correction Coding of Digital Communication
s "(Plenum Press).

The Reed-Solomon code is encoded by the following operation.

[0005]

(Equation 1)

[0006] G (x) is a code generator polynomial and is defined as follows.

[0007]

(Equation 2)

Here, α is one of the primitive roots of the Galois field. That is, it is realized by treating the information sequence as a polynomial, and considering the coefficient of the remainder K-th order polynomial obtained by dividing the information sequence by the generator polynomial as parity, and adding it after the original data sequence. The operation for obtaining the remainder of the polynomial is exactly the same as the ordinary polynomial operation except that the four arithmetic operations on the coefficients are performed as operations on the Galois field.

Generally, decoding of a Reed-Solomon code can be performed in the following procedure.

(I) Calculation of syndrome polynomial S (x) (II) Erasure polynomial Γ (x) / transformed syndrome polynomial T
Calculation of (x) (III) Error value polynomial Ω (x) and error location polynomial Λ
Calculation of (x) (IV) Error value polynomial Ω (x) and error location polynomial Λ
Evaluation of (x) The syndrome polynomial S (x) is defined as follows using α in (3).

[0011]

(Equation 3)

R (x) is a received word information polynomial. If all the coefficients of the syndrome polynomial S (x) are zero, it is determined that there is no error. If the syndrome polynomial S (x) is non-zero, error correction is attempted according to the following procedure.

Calculation of the erasure polynomial Γ (x) and the modified syndrome polynomial T (x) is performed when the error position can be estimated by some means and erasure correction can be performed. Assuming that the erasure has occurred at the location from byte i0 to IE-1, the erasure polynomial Γ (x) and the modified syndrome polynomial T (x) are defined as follows.

[0014]

４ (x) = (α ⁱ⁰ x −1) (α ⁱ¹ x −1)… (α ^iE−1 x −1) (5) T (x) = S (x) Γ (x) mod x ^2t (6) When erasure correction is not performed, Γ (x) = 1 (7) T (x) = S (x) (8)

The calculation of the error value polynomial Ω (x) and the error location polynomial Λ (x) can be performed by the Euclidean algorithm. That is,

[0016]

Ω _i (x) = q _i (x) Ω _i-1 (x) + Ω _i-2 (x) (9) Λ _i (x) = q _i (x) Λ _i-1 (x) + Λ _i-2 (x) (10) Q _i (x) = Ω _i (x) / Ω _i-1 (x) (11)

[0017]

Ω ₋₁ (x) = x ^2t Ω ₀ (x) = T (x) Λ ₋₁ (x) = 0 ₀ (x) = Γ (x) (12) Error value polynomial Ω (x ) Is repeatedly calculated until the order of 2) becomes 2t-E or less. By solving the obtained error value polynomial and error position polynomial as follows, the position and value of the error byte can be known.

From the error value polynomial Ω (x) and the error locator polynomial Λ (x), the error can be calculated as follows.

[0019]

(Equation 7)

That is, if the result of substituting α- ⁱ for Λ (x) is 0, there is an error in the byte at the i-th power and e _i is the value.

In the prior art, the Euclidean mutual division processing of the Reed-Solomon error correction code has often been performed by microprogramming. But when the correction capability of the Reed-Solomon error correction code and t, the processing time increases with t increases to require a product-sum operation in a Galois field (2t) ² times, interfere with the realization of high-speed processing Have been.

In order to solve this problem, parallel processing has been attempted in recent years. For example, Imai et al. (JP-A-63-16)
No. 4629) shows that high-speed processing is possible by using 2t cells. However, in this method, since the state of each cell is different, a control line to each cell is separately required, and the controller needs to have a state of 2t, which increases the amount of hardware.

Also, Cameron et al. In US Pat.
170,399 called Euclid stack 2
By arranging two structures using t cells in parallel,
High-speed processing is realized. This demonstrates that it is possible to perform division between polynomials in one clock cycle by moving up to 2t + 1 multipliers on the Galois field in parallel. Also, the technique described in this US patent specification is different from that described in Japanese Patent Application Laid-Open No. 63-164629, in that all control inputs to each basic cell are common and integrated on an LSI. And the controller is easy to simplify. Also, the process of forming the error value polynomial Ω (x) and the error location polynomial Λ (x),
Metamorphic syndrome polynomial T (x) and vanishing polynomial Γ (x)
Are formed in the same manner, so that when two Euclidean stacks are provided, the control of each stack is the same.

However, US Patent No. 5,170,3
The structure shown in FIG. 2A shown in Japanese Patent No. 99 eventually uses 4t basic cells and requires a large amount of hardware. 2B uses only 2t basic cells. However, since the error value polynomial Ω (X) and the error position polynomial Λ (X) are sequentially calculated, the error value polynomial previously calculated is used. Register memory for storing Ω (X) (FIG. 2
(B) 46) is required. The error locator polynomial Λ
In calculating (X), it is necessary to realize the same sequence as the cycle type for calculating the error value polynomial Ω (X). Therefore, the history of the cycle type for calculating the error value polynomial Ω (X) is stored in the register memory or the control block. Need to accumulate. Also, the control block itself is forced to perform different processing in the cycle of the error value polynomial Ω (X) and the error position polynomial Λ (X),
(X), there is a problem that the control sequences forming the error locator polynomial Λ (x) cannot be fully utilized.

Also, see US Pat. No. 5,170,39.
No. 9 is based on the premise that a syndrome generator and an error value / error locator polynomial evaluation processor are separately provided in addition to the Euclidean stack, and these processes also require a maximum of 2t + 1 parallel multiplications. It does not mention the possibility of a Euclidean stack that can perform this processing even though it is an operation.

[0026]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an arithmetic circuit for performing high-speed error correction decoding of a Reed-Solomon error correction code using a circuit having a simple structure and a small amount of hardware. It is.

[0027]

In order to achieve the above-mentioned object, according to the first aspect of the present invention, an error value polynomial Ω (x),
In a Reed-Solomon error correction code decoding circuit having at least a plurality of basic cells for forming the error locator polynomial Λ (x), one TERM cell and a control circuit, each of the basic cells is 2 The TER includes two sets of registers for operating a set of polynomials, a multiplexer for selecting the registers, a multiplexer for controlling the operations, and at least an operation unit for performing an operation on the Galois field.
The M cell has a divider on the Galois field and at least a register, and the control circuit controls the error value polynomial Ω while maintaining the same control on the basic cell except for the selection of the register.
(X) operation cycle and error location polynomial Λ (x) operation cycle are performed, and the immediately preceding error value polynomial Ω
The division result of the operation cycle of (x) is stored in the register in the TERM cell, and the immediately following error locator polynomial {
It is characterized in that an error value polynomial Ω (x) and an error location polynomial Λ (x) are formed by performing control in such a manner as to be repeated in the operation cycle of (x).

According to a second aspect of the present invention, the basic cell includes a modified syndrome polynomial T (x) and an erasure polynomial Γ
The operation of (x) is also possible, wherein the TERM cell has means for generating data corresponding to a lost portion, and the control circuit performs the conversion while maintaining the same control on the basic cells other than the selection of the register. It is characterized by performing control to repeat two cycles of an operation cycle of a syndrome polynomial T (x) and an operation cycle of an erasure polynomial Γ (x) to form a modified syndrome polynomial T (x) and an erasure polynomial Γ (x). .

According to a third aspect of the present invention, the basic cell and the TERM cell can perform an evaluation operation of an error value polynomial Ω (x) and an error location polynomial Λ (x). Performs two cycles of an evaluation operation cycle of the value polynomial Ω (x) and an error operation polynomial Λ (x) evaluation operation cycle, stores the operation result of the previous cycle in a register in the TERM cell, and calculates an error value in a later cycle , By evaluating the error value polynomial Ω (x) and the error location polynomial Λ (x).

The invention according to a fourth aspect is characterized in that the basic cell and the TERM cell can also perform a syndrome calculation operation.

According to a fifth aspect of the present invention, there is provided a multiplier on a Galois field in which one input is connected to an output of a selector and the other input is connected to a common bus, and at least one of the outputs of the multiplier is connected to a common bus. An adder on a Galois field at the input of the two, two M registers having the output of the adder at the input, and two N registers connected to the input of the multiplier and the output of the adder via a multiplexer; , And the two M registers and two multiplexers connected to respective outputs of the two M registers.

[0032]

The present invention utilizes the fact that the processing of the error value polynomial / error locator polynomial is of substantially the same type in the above-described configuration, thereby effectively sharing hardware by performing the processing alternately. The present invention also takes advantage of the fact that the occurrence of syndromes and the evaluation of error values / error locator polynomials is a parallel operation with a maximum of 2t + 1, and the same hardware is used by time division, thereby sharing and minimizing hardware. Is going.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

(Configuration of Embodiment) FIG. 1 is a block diagram showing the configuration of a basic cell in an embodiment of the present invention. Basic cell 2
FIG. 2 is a block diagram showing the configuration of a TERM cell used in combination with t cells. Also, 2t basic cells and TER
FIG. 3 shows an overall configuration of an arithmetic circuit according to an embodiment of the present invention for decoding a Reed-Solomon error correction code by performing Euclidean mutual division processing by combining M cells.

In FIG. 1, reference numeral 101 denotes a multiplier on a Galois field. 102 is an adder on the Galois field. 10
1, 102 can be replaced by a single multiplier / adder. 1
Reference numerals 03 and 104 denote multiplexers, which switch inputs of a multiplier and an adder, respectively. Multiplexer 103,
The switching control lines 104 are s0 and s1, respectively.
105 and 106 are register groups called M registers.
107 and 108 are register groups called N registers.
The write control lines of the registers 105, 106, 107, and 108 are wm0, wm1, wn0, and wn1, respectively. The output of the registers 105 and 106 is the multiplexer 1
09 is selected. Similarly, registers 107 and 108
Are selected by the multiplexer 110. The multiplexers 109 and 110 are both controlled by the control line s3. Qbus is a common bus, and is an input of the multiplier 101. M _i-1 is an input and is connected to the M _i output of the preceding basic cell as shown in FIG. M _i is an output, and as shown in FIG.
Connected to _i-1 .

In FIG. 2 showing a TERM cell, 201
Is a register and wf is its write control line. 2
02 is an inverse function operation circuit on the Galois field, and 203 is a multiplier on the Galois field. 202 and 203 can be replaced by a single divider. 204, 205, and 206 are multiplexers, and si1, si2, and si3 are control signals thereof. 207 is a zero detection circuit. mzer
o is its output. 208 is a latch, and l _k1 is its control signal.

In FIG. 3, the basic cell 2t shown in FIG.
FIG. 3 shows the interconnection of the TERM cells shown in FIG. 30
2 to 305 are the basic cells BU0, BU1,.
BU2t-1. Reference numeral 301 denotes a multiplexer, and sl denotes its control line. 307 is a control circuit. The signal lines s0-s3 and wd0-we1 are inputs common to all basic cells, and are output from the control circuit. Note that the mzero output in FIG. 2 is an input to the control circuit. Also, the signal lines wf, si in FIG.
Signals to 1, 1 and 2 are output from the control circuit. The Mi output of each basic cell is connected to the next stage Mi _-1 input. The input M _2t-1 to the TERM cell 306 is
It is connected to the output M _i of 2t-1 th basic cell 305.

(Configuration of Another Embodiment) FIG. 4 is a block diagram of a basic cell of another embodiment. In FIG.
Is a multiplier on the Galois field. 402 is an adder on the Galois field. 401 and 402 can be replaced by a single multiplier / adder. Multiplexers 403 and 404 switch the inputs of the multiplier and the adder, respectively. The switching control lines of the multiplexers 403 and 404 are s0 and s1, respectively. Reference numerals 405 and 406 denote register groups called M registers. Reference numerals 407 and 408 denote register groups called N registers. Each register 405, 406, 40
7 and 408 are wm0 and wm, respectively.
1, wn0, wn1. The outputs of the registers 405 and 406 are selected by the multiplexer 409. Similarly, the outputs of the registers 407 and 408 are
Has been selected. The multiplexers 409 and 410 are both controlled by the control line s3. Qbus is a common bus, and is an input of the multiplier 401. M _i-1 is an input and is connected to the M _i output of the preceding basic cell. M
_i is an output, which is connected to the input M _i-1 of the subsequent basic cell.

FIG. 4 shows a configuration in which an input to the multiplexer 103 is added to the basic cell shown in FIG.

FIG. 5 is a block diagram showing the configuration of a TERM cell according to another embodiment.

In FIG. 5, 501 is a register and w
f is the write control line. Reference numeral 502 denotes an inverse function operation circuit on the Galois field, and reference numeral 503 denotes a multiplier on the Galois field. Reference numerals 504, 505, and 506 are multiplexers, and si1, si2, and si3 are control signals thereof. 5
07 is a zero detection circuit. mzero is its output. 508 is a latch, and l _k1 is its control signal. 509 is a Galois field sequencer, and 510 is a 2 t deep FIFO.

The TERM cell shown in FIG. 5 is different from the TERM cell shown in FIG. 2 in that the Galois field sequencer 50 is used.
9 and a 2 t deep FIFO 510.
The connection of each cell is the same as in FIG.

The basic cell of FIG. 4 and the TERM cell of FIG.
An arithmetic circuit for performing the erasure polynomial; modified syndrome generation and the Euclidean mutual division method is formed by the same connection as the connection in FIG.

FIGS. 6 and 7 show a third embodiment.
FIG. 3 is a diagram illustrating a configuration of an example of FIG. FIG. 5 is an extension of the basic cell shown in FIG.

In FIG. 6, reference numeral 601 denotes a multiplier on a Galois field. 602 is an adder on the Galois field. 60
1,602 can be replaced by a single multiply-adder. 6
Numerals 03 and 604 denote multiplexers.
1. The input of the adder 602 is switched. The switching control lines of the multiplexers 603 and 604 are s0,
s1. Reference numerals 605 and 606 denote register groups called M registers. Reference numerals 607 and 608 denote register groups called N registers. Each register 605,606,607,60
8 write control lines are respectively wm0, wm1, wn
0, wn1. The outputs of the registers 605 and 606 are selected by the multiplexer 609. Similarly, the outputs of the registers 607 and 608 are selected by the multiplexer 610. The multiplexers 609 and 610 are both controlled by the control line s3. Qbus is a common bus,
This is an input of the multiplier 601. M _i-1 is an input and is connected to the M _i output of the preceding basic cell. M _i is an output and is connected to the input M _i-1 of the succeeding basic cell.
Reference numerals 611 and 612 represent additional multiplexers. s
2, s4 is the control line. The constant input for calculating the syndrome polynomial, the constant input for evaluating the error locator polynomial, and the constant input for evaluating the error value polynomial as inputs to the multiplexer 603 are compared with the basic cell configuration of FIG. Has been added.

FIG. 7 is an extension of the configuration of the TERM cell of FIG.

In FIG. 7, reference numeral 701 denotes a register w
f is the write control line. 702 is an inverse function operation circuit on the Galois field, and 703 is a multiplier on the Galois field. Reference numerals 704, 705, and 706 are multiplexers, and si1, si2, and si3 are control signals thereof. 7
07 is a zero detection circuit. mzero is its output.
708 is a latch, and lk is its control signal. 7
09 is a Galois field sequencer, 710 is a 2t deep FIF
O.

The above configuration is similar to that of the TERM cell in FIG. Then, as compared with the configuration of FIG. 5, as terminals, Decode data input, Encode data input, Encode
The data output, SUM _odd and SUM _even are added. 713 is a zero detection circuit, and sumzero is its output. 712 is an adder on the Galois field, and SUM
_{The odd} and SUM _even are input and the SUM is output. 71
1 is a latch, and lk2 is its control line. 704
The output of 711 is added to the input of. SUM is added to the input of 705.

FIG. 8 is an overall connection diagram when the basic cell of FIG. 6 and the TERM cell of FIG. 7 are combined. s0-s
Although the control lines 5, wd0-1 and we0-1 are omitted, they are required as common inputs to all basic cells as in FIG. 0th and 1st basic cells 802 and 8
03 is input to the SUM _i-1 input. The SUM _i-1 input of the 2i-th basic cell is the SUM of the 2i-2-th basic cell
Connect to _i output. SUM _{i-1 of} 2i + 1th basic cell
The input is connected to the SUM _i output of the 2i-1 elementary cell. The SUM _odd input of the TERM cell 806 is connected to the SUM _i output of the 2t-1st basic cell 805, and SUM _even
The input is connected to the SUM _i output of the 2t-2 basic cell.

(Operation of Embodiment) Decoding of the Reed-Solomon code according to the above-described embodiment of the present invention will be described by following the operation in the configuration in detail.

In the initial state, the registers of each basic cell and TERM cell in FIG. 3 are initialized as shown in FIG. That is, each coefficient of the initial value polynomial of the error value polynomial Ω ₀ x) is set in each register 105 of the basic cell. Similarly, the error value polynomial Ω ₋₁ (x) is stored in the register 107. Each register 106 of the basic cell has an error locator polynomial Λ
Each coefficient of the initial value polynomial of ₀ (x) is set. Similarly, the error locator polynomial Λ ₋₁ (x) is stored in the register 108. Refer to the above equation (12) for each initial value to be set.

The error locator polynomial Λ (x) is stored in a form shifted from the error value polynomial Ω (x) by one degree for convenience. That is, in the initial state, n +
The first term is stored. The zero-order term is placed in a virtual register immediately before the basic cell 0. This virtual register is always zero except that it has an initial value of 1 (the least significant digit of Λ (x) always moves to the register of BU0 (basic cell 302) in the first division process). In terms of the circuit, 0x is applied to the input of the Mi _-1 terminal of the basic cell 302.
It is realized as a selector for inputting 01 (the multiplexer 301 in FIG. 3 corresponds thereto).

The initialization processing itself becomes unnecessary if the processing for obtaining the syndrome polynomial is performed by the same circuit using the expanded configuration described later, but the generation of the syndrome polynomial is performed by another circuit. To do this, use In as shown in FIG.
It is possible by shifting in from the it input terminal. Alternatively, the shift-in may be performed serially from outside.

One Euclidean algorithm convergence calculation after initialization can be performed by the following procedure. In this embodiment, the error value polynomial Ω (x) and the error location polynomial Λ
The calculation relating to (x) is performed alternately.
The following description focuses on the error value polynomial Ω (x) polynomial, and then describes the operation of the error location polynomial Λ (x).

An operation for obtaining a remainder polynomial by dividing a polynomial can be written as follows. When considering the remainder obtained by dividing the error value polynomial Ω _i-1 (x) by the error value polynomial Ω _i-2 (x), the remainder polynomial W (x) (that is, Ω _i (x)). Ie

[0056]

(Equation 8)

This can be easily understood if it is applied to the procedure of polynomial division. The procedure of the division will be described later in detail.

The expression (18)

[0059]

[Outside 1]

The term corresponds to the quotient obtained by dividing Ω _i-2 (x) by Ω _i-1 (X). That is, assuming that a quotient obtained by dividing Ω _i-2 (x) by Ω _i-1 (X) is Q (x), (18) can be written as follows using the coefficient q _i. .

[0061]

W _{k + 1} (x) = W _k (x) + Ω _i-1 (x) q _ijk x ^ijk (19) FIG. 10 shows the result of the polynomial division calculation. FIG. 11 shows a procedure of a single polynomial division operation using the configuration of the embodiment of the present invention corresponding to FIG.

Now, in FIG.

[0063]

A (x) = a ₃ x ³ + a ₂ x ² + a ₁ x + a ₀ (A) B (x) = b ₂ x ² + bx + b ₀ (B), and equation (A) is represented by equation (B). When divided, the following equation (C) is established using the quotient equation Q (x) and the remainder equation W (x).

[0064]

A (x) = Q (x) B (x) + W (x) (C) where Q (x) = q ₁ x + q ₀ ; W (x) = a ″ ₁
x + a ″ _{0 In} FIG. 10, in operation 1, q ₁ x is obtained, and q ₁ = a ₃ /
a b _2. A ′ (x) derived in operation 1 is

[0065]

A ′ (x) = a ′ ₂ x ² + a ′ ₁ x + a ′ ₀ (D) where a ′ ₂ = a ₂ −q ₁ b ₁ , a ′ ₁ = a ₁ −q ₁
In b ₀ operation 0, Motomari is _{q 0, q 0 = a '} 2 / b 2 , and the remainder W (x) is obtained.

FIG. 11 shows the result of this calculation performed with the configuration shown in FIG. 3 of the embodiment of the present invention.

In the above operation 1, the cycle is from T to T +
When it becomes 1, it is executed by performing the following operation in all the basic cells. Here, M _i, N _i is, i-th basic cell M register shows the contents of the N register.

[0068]

M _{i, T + 1} = Q × M _{i−1, T} + N _{i, T} (E) N _{i, T + 1} = M _{i−1, T} Q = N _{2t, T} / M _{2t−1 , T The} above Q is calculated in the TERM cell and sent to each basic cell via Qbus. Also, the contents of the M register are set to N
Moved to register. Next, the cycle of operation 0 is T + 1
When it becomes T + 2 from all the basic cells, it is executed by performing the following operation.

[0069]

M _{i, T + 2} = Q × N _{i, T + 1} + M _{i-1, T + 1} (F) N _{i, T + 2} = N _{i, T + 1} Q = M _{2t−1 T + 1} / N _{2t, T + 1} As above, Q is obtained in the TERM cell and sent to each basic cell via Qbus. The remainder is found in the M register.

FIGS. 12 and 13 show the switching of the control lines of the basic cell and the TERM cell at the time of the operation 1, and FIGS. 14 and 15 show the control at the time of the operation 0.

FIG. 12 shows the basic cell at the time of operation 1 in the above equation (E).

[0072]

## EQU15 ## The connection for performing the calculation of Mi _{, T} = Q.times.Mi _{-1, T-1} + _{Ni, T- 1Ni, T + 1} = Mi _{-1, T} is shown. FIG. 13 shows the TERM cell at the time of operation 1 in the above equation (E).

[0073]

## _EQU16 ## A connection for performing an operation of Q = N _2t / M _2t-1 is shown.

FIG. 14 shows the basic cell in operation 0 and the above equation (F).

[0075]

[Mathematical formula _- see original document] The connection for performing the operation of Mi _{, T} = Q * _{Ni, T-1} + Mi _{-1, T-1} is shown. FIG. 15 is a graph showing the TERM cell in operation 0 in the above equation (F).

[0076]

## _EQU18 ## The connection for performing the operation of Q = M _2t-1 / N _2t is shown.

Such an operation is used for the division of the polynomials (14) to (19). In operation 1, (14) ~
While obtaining W ₁ (x) in the procedure of (19),
Ω _i-2 (x) in the M register is transferred to the N register storing Ω _i-1 (x). W ₁ (x) is Ω _i-2
(X) is overwritten on the stored M register. After that, W ₂ (x) is obtained by calculation 0.

FIG. 16 illustrates the control procedure of the present invention in pseudo code. In FIG. 16, POWER
R and REDUCE are counters each capable of counting up to t. Operation 2 in FIG. 16 is an operation of shifting up the contents of the M register of each basic cell. In this operation 2, the control of the basic cell is the same as the operation 0, and is realized by performing control to output 0 to Qbus by the selection signal of si3 of the TERM cell. The control procedure of FIG.
In FIG. 3, the control is performed using a control circuit 307.

The calculation of the error value polynomial Ω (x) has been described above. The calculation of the error locator polynomial Λ (x), which is performed in parallel with the calculation of the error value polynomial Ω (x), is represented by the equation (1)
0). This equation (10) and equation (1)
_Focusing on 9), using the q _IJk obtained in the calculation of the error value polynomial Ω (x), the error location polynomial Λ _i−2
Error value polynomial Ω _i-2 for (x), Λ _i-1 (x)
It can be seen that it is sufficient to perform exactly the same operation as that performed for (x) and Ω _i-1 (x).

In the embodiment of the present invention, as shown in the time chart of FIG. 17, the cycle of the operation of the error value polynomial Ω (x) and the latch of the value of the Q bus, the error position polynomial Λ
The operation cycle of (x) is performed alternately. Error value polynomial Ω
The coefficients of _i-1 and Ω _i-2 are determined by the registers 105,
107, the error locator polynomial Λ _i-1 ,
The coefficient of Λ _i−2 is stored in registers 106 and 108 of each basic cell. The operation of the error locator polynomial を (x) is performed by using the value of the Q bus obtained by the operation of the error value polynomial Ω (x) as TER in FIG.
The data is stored in the latch 208 of the M cell, and s0 and s1
In the next cycle, while holding the value of the control line, the selection signals ωmo, ωm1, ωno, ωm1,
This is realized by switching s3 and controlling to select the registers 106 and 108 instead of the registers 105 and 107.

FIG. 18 shows an example of processing for the code of t = 2. FIG.

[0082]

## EQU19 ## On a Galois field defined by G _p (x) = x ⁸ + x ⁵ + x ³ + x ² +1 (20), a Reed-Solomon code of M ₀ = 120 and t = 2 is used as an example. I have. This is an example in which an error having a size of x10 is added to a term of X16 of a codeword having all zero coefficients. T = 0 is the initial state, and the coefficients of the syndrome polynomial are stored in the register 105 of each basic cell. Each of the registers 107, 106, 108
Are Ω ₋₁ (x), Λ ₀ (x), Λ according to equation (12).
Initialized to a coefficient of _-1 (x). Since M2t _-1 is non-zero, stepB is executed according to FIG. 16, and the contents of the register in each basic cell change to the state of T = 2 in FIG.
(T increases by two, but two cycles are required because each cycle of Ω cycle for calculating an error value polynomial and Λ for calculating an error locator polynomial is required.) The process according to the algorithm of FIG. , T = 8, the coefficients of the final error value polynomial Ω (x) and error location polynomial Λ (x) are obtained in the registers 105 and 106 of each basic cell.

The operation 0, the operation 1 and the operation 2 have only to be performed each time the degree of the polynomial is reduced by one. Therefore, the calculation of the error value polynomial Ω (x) of the Reed-Solomon code with the correction capability t requires 2t at most. Times needed. In the present invention, operation 0 and operation 1
・ Since operation 2 is performed in one cycle, the position polynomial Λ
(X) and the error value polynomial Ω (x) are calculated at most 2t ×
Only two cycles are required.

As described above, it has been shown that the Euclidean algorithm of the Reed-Solomon code can be processed at high speed by using the embodiment of the present invention.

(Operation of Another Embodiment) In the following, FIG. 1 and FIG.
4 and 5 in which the error value polynomial Ω (x),
This shows that not only the calculation of the error locator polynomial Λ (x) but also the derivation of the modified syndrome polynomial T (x) and the erasure polynomial Γ (x) are possible.

At the end of data input, the TERM cell FIF
Alpha ₀ corresponding to erasures in _{O510, α 1 ... α iE-} 1 is stored. Initialization of basic cell is error value polynomial Ω
(X), the same as in the case of the error locator polynomial Λ (x).
Equations (5) and (6) can be written as the following recurrence equations.

[0087]

数_{j + 1} (x) = (α _j −1) Γ _j (x) (21) T _{j + 1} (x) = (α _j −1) T _j (x) (22) The cell will eventually have a similar

[0088]

[Mathematical formula-see original document] The operation of γi _{, T + 1} = αi _, Tγi _{-1, T} + γi _{, T} (23) may be realized.

FIG. 19 shows the modified syndrome polynomial T (x)
The connection of the basic cells at the time of calculation is shown. In this connection, the basic cell is

[0090]

[Mathematical formula-see original document] An operation of M _{i, T + 1} = Q × M _{i−1, T} + M _{i, T} is performed. This is similar to the form of the above equation (23).

The TERM cell is connected to the multiplexer 50.
6 to output the value of the FIFO 510. At the time of calculating the erasure polynomial １ ， (x), the same operation is performed by switching wm0, wm1, and s3. FIG. 20 shows a timing chart.
Erasure polynomial when FIFO 510 is empty
(X), the metamorphic syndrome polynomial T (x) calculation ends. At this time, the coefficient of the metamorphic syndrome polynomial T (x) is stored in the register 405 of each basic cell, and the coefficient of the erasure polynomial Γ (x) is stored in the register 406 of each basic cell. Since this matches the initial state for calculating the error value polynomial Ω (x) and the error position polynomial Λ (x) at the time of erasure correction, the controller continues the error value polynomial Ω (x),
It is possible to shift to the calculation of the error locator polynomial Λ (x).
Error value polynomial Ω (x) at the time of erasure correction, error position polynomial Λ
The procedure for calculating (x) uses the procedure shown in FIG. 21 instead of the procedure shown in FIG. FIG.
The control circuit shown in FIG. 3 controls the basic cell and the TERM cell according to the procedure shown in FIG.

(Operation of Third Embodiment) Hereinafter, it will be shown that by extending the present invention, it is possible to perform all the operations necessary for the Reed-Solomon code. Figure 6 below
7 shows that the circuit shown in FIG. 7 can execute a syndrome calculation operation / error value polynomial / error position polynomial evaluation operation required for decoding.

For the calculation for finding the syndrome, rewriting (4),

[0094]

R (α ^{m0 + 1} ) = ((... ((r _N α ^{m0 + i} + r _N-1 ) α ^{mo + i} + r _N-2 ) ... + r ₁ ) α ^{m0 + i} + α ^{m0 + i} ) (24) Therefore, in each basic cell,

[0095]

S _{i, T + 1} = s _{i, T} α ^{m0 + i} + r _T (25) It suffices if the operation can be executed.

FIG. 22 shows the connection of the extended basic cells shown in FIG. 6 in the syndrome calculation operation. Syndrome const in FIG.
ant C _S is α ^{mo + i} . TERM cell is Deco
The received word is output to Qbus from the de Data Input through the si3 multiplexer. Therefore, in FIG.

[0097]

Equation 25] _{M n, T = C S ×} M n, T + r t ( However, r _t is t-th received word) is calculated.

Prior to the syndrome operation, the register 60
5,606 is initialized to zero. This is because, for example, when Qbus is selected for both the multiplexers 604 and 611, the Qb
This is possible by outputting zero to us. Thereafter, a syndrome operation is performed, but processing can be performed for one byte of the received word in one cycle. M of each basic cell after codeword input
The syndrome polynomial remains in the register. This continues with the vanishing polynomial Γ (x) and the modified syndrome polynomial T
It is convenient to derive (x). The operation of initializing the register 607 corresponding to Ω ₋₁ (X) is from 2t−1 stored in the basic cell, and the zero-order term is the multiplexer 61
This is performed by inputting 0 with 1. 2t next term is TER
Although this corresponds to the register 701 in the M cell, the initialization is not performed in the present embodiment. Instead, when Ω _-1 (X) is used for the first time, the multiplexer 705 outputs 0 to deal with it. I have. The error locator polynomial Λ
The initialization of Λ ₋₁ (x) for (x) is performed by register 608
Is possible by inputting 0 by the multiplexer 612.

The derivation of the erasure polynomial Γ (x) and the modified syndrome polynomial T (x) and the calculation of the error value polynomial Ω (x) and the error location polynomial Λ (x) are the same as described above. When the calculation of the error value polynomial / error position polynomial Λ (x) is completed, the error value polynomial Ω (x) is stored in each register 60.
5, the error locator polynomial Λ (x) is in each register 606. The evaluation operation of the error value polynomial / error locator polynomial Λ (x) will be described below.

FIGS. 23 and 24 show the connection of the extended basic cells shown in FIG. 6 for the evaluation operation of the error value polynomial Ω (x) and the error locator polynomial Λ (x). The TERM cell outputs zero to Qbus by si3 and the zero detection circuit 7
13, zero of the error locator polynomial Λ (x) is detected.
The extended basic cell alternately repeats the operation of the evaluation cycle of the error locator polynomial Λ (x) (FIG. 24) and the evaluation cycle of the error value polynomial Ω (x) (FIG. 23). The lamda constant is α ^-i and the omega constant is α ^{-mo-i + 1} .

Therefore, in the extended basic cell connected as shown in FIG.

[0102]

(Equation 26)

In the extended basic cell connected as shown in FIG.

[0104]

The calculation of M _{i, T + 1} = CΛ × M _{i, T} is performed.

That is, in each extended basic cell,

[0106]

Ω _{i, T + 1} = ω _{i, T} α ^{-mo-i + 1} [= ω _{i, 0} α ^{(-m0-i + 1) T} ] λ _{i, T + 1} = λ _{i, T} α ^-i [= λ _{i, 0} α ^-iT ] (26) As a result of calculating the error value polynomial Ω (x) and the error position polynomial Λ (x), the error value polynomial Ω (x),
The most significant coefficient of the error locator polynomial Λ (x) is 2t−1
Cell. Assuming that the order of the error locator polynomial Λ (x) is E, the order of the error value polynomial Ω (x) is E−1. Considering this, it can be seen that (26) realizes the following operation. SUM is the output of the adder 712.

[0107]

(Equation 29)

Therefore, if a zero is detected by the zero detection circuit 713 during the evaluation cycle of the error locator polynomial Λ (x), it indicates that an error has been detected.

Further, in a Galois field, generally 2a = a
Since + a = 0,

[0110]

[Equation 30]

In order to satisfy

[0112]

(Equation 31)

Is as follows. Therefore, (27) is replaced by (30)
(10) is obtained by dividing by. In order to realize this, in the present invention, the zero detection circuit 7 is provided during the cycle (1).
13 if a zero is detected by L
In addition to latching UModd, in the next Ω cycle, connection of the extended TERM cell shown in FIG.
Error value is output to the Option Output.

The above control is performed by the control circuit 807 shown in FIG.
This is done by controlling the cells.

As described above, the encoding and decoding processes of the Reed-Solomon code can be realized with only 2t basic units. When the code length is set to N, the erasure correction is not performed, and N is applied to the syndrome operation.
Cycle, 2t × 2 cycles for Euclidean operation, 2 for evaluation of error value polynomial Ω (x) / error location polynomial Λ (x)
It takes N cycles. Therefore, a cycle rate of 20
Assuming that Mhz, t = 8, and N = 255, processing at a data rate of 6.3 MByte / sec is possible. Further, when performing erasure correction, it takes only a maximum of 2t × 2 cycles to obtain the erasure polynomial / altered syndrome polynomial, so the data rate is 6.1 MByte / sec.
Is possible.

[0116]

As described above, according to the present invention, it is possible to calculate an error value polynomial and an error locator polynomial な at high speed with a simpler control circuit and fewer circuit elements compared to the prior art. Since the structure of each basic cell is the same, LSI
Suitable for stacking on. The present invention does not stop there,
This shows that other hardware operations of the Reed-Solomon code can be efficiently hardware-structured by time-division processing. Since each basic cell is the same except for constant input, L
The advantage of being convenient to integrate on SI is not lost. In addition, a processing speed of 6.3 MByte / sec can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a basic cell of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a TERM cell of the present invention.

FIG. 3 is a block diagram of a Reed-Solomon decoding circuit combining a basic cell and a TERM cell.

FIG. 4 is a block diagram showing a configuration of another embodiment of the basic cell of the present invention.

FIG. 5 is a block diagram showing a configuration of another embodiment of the TERM cell of the present invention.

FIG. 6 is a block diagram showing a configuration of an embodiment of an extended basic cell according to the present invention.

FIG. 7 is a block diagram showing a configuration of an embodiment of an extended TERM cell of the present invention.

8 is a block diagram of a Reed-Solomon decoding circuit obtained by combining the basic cell in FIG. 6 and the TERM cell in FIG. 7;

9 is a diagram illustrating an initial state of the Reed-Solomon decoding circuit in FIG. 3;

FIG. 10 is a diagram illustrating division of a polynomial.

FIG. 11 is a diagram illustrating the operation of the Reed-Solomon decoding circuit of FIG. 3;

FIG. 12 is a diagram for explaining the operation of operation 1 of the basic cell in FIG. 1;

FIG. 13 is a diagram for explaining the operation of Operation 1 of the TERM cell in FIG. 2;

FIG. 14 is a diagram illustrating the operation of operation 0 of the basic cell in FIG. 1;

FIG. 15 is a diagram illustrating the operation of operation 0 of the TERM cell in FIG. 2;

16 is a diagram illustrating an operation procedure of an operation of the Reed-Solomon decoding circuit in FIG. 3;

FIG. 17 is a time chart of the operation of the Reed-Solomon decoding circuit in FIG. 3;

FIG. 18 shows the Reed-Solomon decoding circuit shown in FIG.
FIG. 3 is a diagram for explaining processing at the reference numeral.

19 is a modified syndrome polynomial T of the basic cell of FIG.
It is a figure explaining operation | movement of derivation of (x).

FIG. 20 is a time chart of an operation for deriving an erasure polynomial Γ (x) and a modified syndrome polynomial T (x).

FIG. 21 is a diagram illustrating a procedure for deriving an erasure polynomial Γ (x) and a modified syndrome polynomial T (x).

FIG. 22 is a diagram illustrating an operation of a syndrome operation of the extended basic cell in FIG. 6;

FIG. 23 is a diagram illustrating an operation of an evaluation calculation of an error value of the extended basic cell in FIG. 6;

24 is a diagram illustrating an operation of an evaluation calculation of an error position of the extended basic cell in FIG. 6;

FIG. 25 is a diagram illustrating an operation of calculating an error value of the extended TERM cell of FIG. 7;

[Explanation of symbols]

 101 Multiplier on Galois Field 102 Adder on Galois Field 103, 104 Multiplexer 105, 106 M Register 107, 108 N Register 109 Multiplexer 201 Register 202 Inverse Function Operation Circuit on Galois Field 203 Multiplier on Galois Field 204, 205,206 Multiplexer 207 Zero detection circuit 208 Latch 301 Multiplexer 302-305 Basic cell 306 TERM cell 307 Control circuit 401 Multiplier on Galois field 402 Adder on Galois field 403,404 Multiplexer 405,406 M Register 407,408 N Register 409, 410 Multiplexer 501 Register 502 Inverse function operation circuit on Galois field 503 Multiplier on Galois field 504, 505, 506 Multiplexer 507 Zero Output circuit 508 Latch 509 Galois field sequencer 510 FIFO of 2t depth 601 Multiplier on Galois field 602 Adder on Galois field 603,604 Mux 605,606 M register 607,608 N register 609,610,611,612 Mux 701 Register 702 Inverse function operation circuit on Galois field 703 Multiplier on Galois field 704, 705, 706 Multiplexer 707, 713 Zero detection circuit 708 Latch 709 Galois field sequencer 710 FIFO 712 Adder on Galois field 711 Latch 801 Multiplexer 802 305 Basic cell 806 TERM cell 807 Control circuit

Claims (5)

(57) [Claims] 1. A plurality of basic cells and one TE for forming an error value polynomial Ω (x) and an error locator polynomial Λ (x).
In a Reed-Solomon error correction code decoding circuit having at least an RM cell and a control circuit, each of the basic cells includes two sets of registers for calculating two sets of polynomials, and a multiplexer for selecting the registers. ,
A multiplexer that controls the operation, and at least an arithmetic unit that performs an operation on the Galois field; the TERM cell has at least a divider on the Galois field and at least a register; While the control on the basic cell other than the selection of the register remains the same, two cycles of the operation cycle of the error value polynomial Ω (x) and the error position polynomial Λ (x) are performed, and the immediately preceding error value polynomial Ω (x) Is stored in the register in the TERM cell, and control is performed so as to repeatedly use the error cycle polynomial Λ (x) in the arithmetic cycle to obtain the error value polynomial Ω (x). , The error locator polynomial Λ
A Reed-Solomon error correction code decoding circuit, wherein (x) is formed. 2. The basic cell is capable of calculating a modified syndrome polynomial T (x) and an erasure polynomial Γ (x), and the TERM cell has means for generating data corresponding to an erasure location, The control circuit controls the modified syndrome polynomial T while maintaining the same control on the basic cells except for the selection of the register.
(X) and a cycle of erasure polynomial Γ (x) are repeated. The modified syndrome polynomial T (x) and the erasure polynomial Γ (x)
2. The Reed-Solomon error correction code decoding circuit according to claim 1, wherein 3. The basic cell and the TERM cell can also perform an evaluation operation of an error value polynomial Ω (x) and an error location polynomial Λ (x). Two cycles of an evaluation operation cycle and an error locator polynomial Λ (x) evaluation operation cycle are performed.
Evaluating the error value polynomial Ω (x) and the error locator polynomial Λ (x) by repeating the control of storing the data in the register in the RM cell and using it in the calculation of the error value in a later cycle. The lead according to claim 1 or 2,
Solomon error correction code decoding circuit. 4. The Reed-Solomon error correction code decoding circuit according to claim 1, wherein the basic cell and the TERM cell can also perform a syndrome calculation operation. 5. One of the inputs is connected to the output of the selector,
A multiplier on a Galois field whose other input is connected to a common bus, an adder on a Galois field having at least one output of the multiplier, and two multipliers having an output of the adder as inputs An M register; two N registers connected to an input of the multiplier and an output of the adder via a multiplexer; two M registers; and two multiplexers connected to respective outputs of the two M registers The Reed-Solomon error correction code decoding circuit according to any one of claims 1 to 4, wherein the circuit is configured using the basic cell having: