JPH0834440B2 - Galois field calculation method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Galois field arithmetic unit used in a code error check / correction apparatus used when recording / reproducing data on / from a medium such as an optical disk.

2. Description of the Related Art In recent years, development of a data recording / reproducing device using an optical disc has been actively conducted. The optical disk memory can record a large amount of data as compared with the magnetic disk, but has a drawback that the raw error rate of the recording medium is high. Therefore, a method is generally used in which an error check correction code is added to the data at the time of recording to record both the data and the error check correction code on the optical disc, and the error of the data is checked and corrected at the time of reproduction by using the error check correction code. To be A Reed-Solomon code with a minimum distance of d = 17 is one that has been drawing attention in recent years as a name error check / correction code. Normally, in decoding a Reed-Solomon code, first the syndrome is calculated from the received word, then the number of errors and error position polynomial σ (x) and error amount polynomial ω (x) are obtained from the syndrome, and finally the error position is calculated from each polynomial. The error amount is estimated and the correction is executed. However, since the minimum distance is large, the decoding process is complicated, the decoding takes a long time, and a large circuit is required to realize the hardware. Of these, parallel calculation hardware is often used because the calculation of the syndrome greatly affects the decoding speed. However, if high speed is required, other correction processing is not pure hardware and is a microprogramming method. Depending on the case, processing may be performed at a speed close to that of hardware. At this time, a fast solution algorithm such as Euclidean mutual division method is known for the derivation calculation of the error locator polynomial and the error amount polynomial, and the Chien algorithm is used to obtain the error position from the error locator polynomial. The error amount is obtained by calculating the error position polynomial and the polynomial of the error position polynomial on the Galois field. Of these, Chie
The algorithm of n and the calculation of the polynomial obtained by differentiating the error locator polynomial and the calculation of the error amount polynomial are mostly the calculation of substituting a variable that is a polynomial to obtain the value of the polynomial. Horn generalized as a method for finding the value of a polynomial at a somewhat high speed
A method called er's method, which results in repeated product-sum calculation, has been used. (For example, Technical Report of IEICE
IT84-43, Rerd-So based on systolic algorithm
A method for constructing a lomon code decoder, Kimura et al., page 5) A conventional Galois field arithmetic method will be described below with reference to the drawings. 3 and 4 show a part of a Galois field arithmetic circuit used in the conventional correction processing. In FIG. 3, 11 is a 0 element determination circuit, 12, 13, 34 are input pipeline registers, 28 is a memory, 29 is a Galois field multiplication circuit, 30 is a Galois field addition circuit (exclusive OR operation circuit), 31, 32 is a switch logic gate circuit, 33 is a primitive element α
Is a power generation circuit (position number generation circuit). This operation
Performed on GF (2 ₈ ).

The operation of polynomial calculation by the conventional Galois field arithmetic unit will be described below. First, the received word read from the optical disc is input to the syndrome calculation circuit after deinterleaving. The obtained syndromes are all 0
If not, it is determined that there is an error, this syndrome is sent to the Galois field arithmetic unit, and the number of errors is calculated and the error position and the error amount are estimated. (D-1) syndromes are sent from the syndrome arithmetic circuit to the memory of 28, where d is the minimum distance of the code, and the multiplier of 29 and the adder of 30 or micro program though not shown in the figure. The number of errors t and the coefficient (including 0th order) of each degree of the (t + 1) error locator polynomial are calculated and stored by the control logic circuit, the inverse memory, and the like. Now, the operation of obtaining the root α ^N of the error locator polynomial and the value obtained by substituting α ^N for the polynomial obtained by differentiating the error locator polynomial using the same Galois field arithmetic circuit will be described. If there are three errors for simplification, the error locator polynomial is k ₃ X ³ + k ₂ X ² + k ₁ X + k ₀ , and the polynomial obtained by differentiating the error locator polynomial is k ₃ X ² + k ₁ . Therefore, the switch logic gate circuit of 31 is connected to the Galois field adder circuit side of α of 33,
Switch logic gate circuit of 28 to memory side
Substitute the coefficients k ₃ , 0, k _{1 for} Rc and α ^N for Ra of 12. It is assumed that the contents of Rb of 13 are cleared to 0 before the calculation is executed. The output of the 30 adders at this time is α ^N * 0 + k ₃ , α ^N * k ₃ +0, α ^N * (α ^N *
k ₃ ) + k ₁ is obtained, and the value obtained by substituting the error position into the polynomial obtained by differentiating the error position polynomial in the third step is calculated.
Note that the above expressions are all operations on the Galois field, and the operator + indicates addition and * indicates multiplication. Generally, the number of steps required for calculation is the same as the degree of the polynomial except for the initial setting. Further, the 0 element determination circuit 11 and the power generation circuit 33 of α are used to substitute the number of error positions into the error position polynomial in the calculation of the error position and determine whether or not it is a root. This calculation is
Since the same procedure as the above-described polynomial calculation method can be used, the description thereof will be omitted. FIG. 4 shows the inside of the 29 multiplication circuits. In FIG. 4, 1, 2, 3, 4, 5, 6, 7, and 8 are Galois field fixed coefficient multipliers, and 9 is a fixed coefficient multiplier corresponding to when each bit of 12 pipeline registers is 0. It is a logical product circuit for multiplying the output by 0 element in series, and is provided for each bit for each output of each fixed coefficient multiplier. Further, 10 is a paridi generator circuit, which outputs an exclusive OR of each bit for all symbols of the multiplication result.

Problems to be Solved by the Invention However, in the above method, as the number of errors increases, the error locator polynomial and the degree of the error locator polynomial increase, and the amount of sum-of-products calculation for obtaining the polynomial value increases. There is a problem that the decoding time becomes long.
For example, when the error position α ⁱ has been obtained, the error amount e ⁱ corresponding to the error position is σ
(X), assuming that the error amount polynomial is ω (x), it can be calculated by e _i = −α ⁱ · ω (α ⁱ ) · σ ′ (α ⁱ ) ⁻¹ , but as a polynomial calculation, ω (α ⁱ ). And σ ′ (α
ⁱ ) must be calculated, and the larger the number of errors that occur, the greater the amount of product-sum calculation.
Usually, when the Reed-Solomon code is used for recording / reproduction of an optical disk or the like, the decoding time is limited due to the need to transfer data in real time. It is necessary to reduce the amount of calculation required for decoding. In view of the above problems, the present invention provides a Galois field arithmetic unit that achieves both high speed and a small amount of hardware.

Means for Solving the Problems In view of the above problems, the present invention has a codeword Galois field GF.
Intermediate value of (t + 1) symbols or more in each degree calculated by substituting the position number into the coefficient value of the error locator polynomial of degree t of the Reed-Solomon code composed of (2 ^r ) elements and the error locator polynomial A storage element group for storing the result; a means for storing coefficient values in the storage element;
Common to the symbol input, the primitive element α of the Galois field GF (2 ^r ) is a power of 0 to (r−1), that is, α ⁰ to α _r−1.
Up to r fixed coefficients, or α for a storage element group of (t + 1) symbols within r
^A group of r multipliers that multiply a fixed coefficient from ⁰ to α ^t ;
A fixed coefficient generation circuit that generates a symbol in which the even-numbered bit is 0 and the odd-numbered bit is 1 starting from the lower-order 0th bit of GF (2 ^r ), and a second arbitrary 1-symbol input different from the above Corresponding to the lower-order 0th bit to the (r-1) th bit of the binary representation of 0, the r fixed coefficients from α ⁰ to α _r-1 are fixed coefficients of 0 element on the Galois field GF (2 ^r ). Means for switching the second one-symbol input to a fixed coefficient output from the fixed coefficient generating circuit,
Means for supplying to the input of the multiplier group a selected result that has been switched using the first arbitrary symbol and the value of the output of the storage element group as input, and r number of results obtained by the multiplier group R odd and even decision unit groups that obtain the result of 1 symbol by taking the exclusive OR of each component of the binary vector of the symbol, and means for detecting whether the output symbol of the odd and even decision unit group is 0 element, (T obtained by the multiplier group)
+1) In a Galois field arithmetic unit provided with means for feeding back and storing an output of a symbol in the storage element group, when performing Galois field multiplication, α ^{0 is} input to the first arbitrary 1 symbol input.
To α _r-1 by r fixed coefficients and from the 0th bit of the binary representation of the second arbitrary 1-symbol input to r-1
If each bit is 0 corresponding to the th bit, the r fixed coefficients from α ⁰ to α _r-1 are switched to fixed coefficients of 0 element on the Galois field GF (2 ^r ) and the multiplication result is To obtain the number of error positions and the derivative of the error position polynomial by obtaining the output symbol of the oddity judgment device group, α of the fixed coefficient multiplier
After storing the t-th coefficient of the error locator polynomial in the storage element group corresponding to ^t , at least 1 from the lower order to the t-th bit is given as the second 1-symbol input and each input of the multiplier As a result, each of the corresponding storage elements is selected, and the multiplication result of the (t + 1) symbol by the multiplier is fed back to each of the storage elements to feed back when the output of the oddness judgment unit group becomes 0 element. After temporarily stopping and measuring the number of times of feedback to obtain the number of error positions, the output of the fixed coefficient generating circuit is given as the second one-symbol input, and the differential operation of the error position polynomial is given to the output of the oddity judgment unit group. After obtaining the result, the feedback is continued again, and the above operation is repeated until the number of times of the feedback reaches the code length −1 times. Further, in the Galois field arithmetic method of the present invention, when the number of error positions of the rth order or more is obtained, the coefficient value of each residue of the error locator polynomial and the intermediate result in each order calculated by substituting the error position number into the error locator polynomial are stored. the fixed coefficient of storage elements and the order r more of said alpha ^r or more fixed coefficient multiplier group and the alpha ^r or more fixed coefficients multipliers the output of storage elements corresponding to the number of error locations to 0 yuan The sum of the multiplication result obtained by the switching means, the fixed multiplier group of α ⁰ to α _r−1, and the multiplication result obtained by the fixed coefficient multiplier group of α ^r or more is r + 1 or more (t + 1) pieces. When the Galois field multiplication is performed and r odd-even decision units that obtain the result of 1 symbol are provided by taking the exclusive OR of each component of the binary vector of r number of fixed from α ⁰ to α _r-1 in Fixed from the lower 0-th bit of the binary representation of multiplying the number and second arbitrary one symbol input of the r from the alpha ⁰ of each bit of r-1 th bit corresponding If 0 to alpha _r-1 The fixed coefficient of the coefficient multiplier group is switched to a fixed coefficient of 0 element on the Galois field GF (2 ^r ), and the output of the fixed coefficient multiplier group of α ^r or more is set to 0 element at the input of the odd / even decision unit group. In order to obtain the multiplication result at the output of the odd / even decision unit group and obtain the number of error positions equal to or greater than r, 1 is given to each bit as the second 1-symbol input. The output of the fixed coefficient multiplier group equal to or ^larger than α ^r is input to the input of the odd / even decision unit group, and when the differential of the error locator polynomial is obtained, the fixed coefficient generation is performed as the second arbitrary 1-symbol input. above the alpha ^r with providing the output of the circuit In the case where the highest order of the error locator polynomial is equal to or higher than the r-th order such that the output of the even-numbered fixed coefficient multiplier starting from the r-th constant coefficient multiplier group outputs 0-element and is supplied to the input of the odd-even coefficient determiner group Also in, the same operation as described above is repeated.

In the operation of Galois field GF (2 ^r ), the common multiplier of 1 symbol is multiplied by a fixed coefficient of α ⁰ to α ^r−1 to obtain r results, and r of the binary vector of the multiplicand symbol is obtained. If the next component is 0, the fixed multiplier multiplication result corresponding to the r-th component is set to 0, and the exclusive logic of the obtained r symbols can be taken. In addition, using the same fixed multiplier circuit, the memory output that stores the coefficient value calculation result from the 0th to the tth of the error locator polynomial is used as the input of the fixed multiplier circuit, and the fixed coefficient from α ⁰ to α ^t is input to the memory output. The result t obtained by the fixed coefficient multiplier group is returned to the memory for each multiplication and multiplication result for each order.
It is possible to obtain the calculation result by taking the exclusive OR of the symbols and obtaining the result of one symbol and substituting the error position into the error position polynomial.

At this time, the multiplicand may be set in the register so that all of its binary vectors are 1. When the number of errors t is larger than (r-1), the output symbol of the storage element group that stores the intermediate result in each degree calculated by substituting the position into the error locator polynomial is further multiplied by the fixed coefficient of the rth order or more. A group of vessels may be provided. When the calculation result obtained by substituting the error position into the error position polynomial is 0, the error position is the solution of the error position polynomial. Here, the value of the polynomial obtained by substituting the error position into the polynomial obtained by differentiating the error locator polynomial can be found by using the fact that each order component of the error locator polynomial is found before entering the next error locator calculation. . In the differential of the polynomial in the Galois field, the even-order terms before the differentiation are 0 after the differentiation, and the coefficients of the odd-order terms before the differentiation are the coefficients of the first-order and lower-order terms after the differentiation. That is, σ (X) = k ₈ X ⁸ ＋ k ₇ X ⁷ ＋ k ₆ X ⁶ ＋ k ₅ X ⁵ ＋ k ₄ X ⁴ ＋ k ₃ X ³ ＋ k ₂ X ²
The derivative of + k ₁ X + k ₀ has a relationship of σ ′ (X) = k ₇ X ⁶ + k ₅ X ⁴ + k ₃ X ² + k ₁ , but at this time, X · σ (X) = k ₇ X ⁷ + k ₅ X By utilizing the fact that ⁵ + k ₃ X ³ + k ₁ X ¹ , X · σ (X) can be easily determined using the same hardware.

That is, the results obtained by multiplying the memory outputs storing the 0th to tth order calculation results of the error locator polynomial by the fixed coefficients α ⁰ to α ^t , respectively, are the multiplicands whose binary vectors are even-numbered from the bottom. If you use a symbol whose bit is 0 and odd-numbered bit from the bottom is 1,
The bit component corresponding to the even power of α in the output of the fixed coefficient multiplier group becomes 0, and the exclusive OR of the fixed multiplier multiplication results of only the odd powers of α is taken. The result of substituting the error position for X · σ (X)
Can be easily obtained without special calculation. Since the value of the differentiated polynomial obtained in this way is not calculated by lowering the degree of the polynomial variable by one degree at the time of differentiation, an error position is added by one extra degree as compared with the value of the actually differentiated polynomial. Although the value is obtained, this can be solved by, for example, multiplying the error amount by the error position once in the process of obtaining the error amount.

Embodiment A Galois field arithmetic method according to an embodiment of the present invention will be described below with reference to the drawings. 1a-1 and 1a-2 show a flow chart of the first embodiment of the present invention, and FIG. 1b shows a block diagram of an apparatus applied to the first embodiment of the present invention. It is shown. In FIG. 1b, 1,
2, 3, 4, 5, 6, 7, and 8 are Galois field fixed coefficient multipliers, 9 is an AND circuit, 10 is a parity generator circuit,
Pipeline registers 12 and 13 are the same as those in FIG. 4 above. Reference numeral 11 is a 0-element determination circuit, 14, 15, and 36 are switch logic gate circuits, and 16, 17, and 18 are registers for storing an intermediate value obtained by multiplying the coefficient input value of the error locator polynomial and the position number of the error locator polynomial of each degree. Is. Reference numeral 35 is an 8-bit fixed symbol generation circuit for generating a constant of binary 00000010. 37 is a pipeline register. These operations are performed on GF (2 ⁸ ), and the first embodiment deals with the case where the number of errors t is 2 or less. The flow of the arithmetic method applied to the Galois field arithmetic device configured as described above will be described below with reference to FIG. When the coefficient value of each number of errors and each error locator polynomial is obtained by the multiplication / division / addition process on the Galois field of the syndrome, the multiplication is common to a certain 1-symbol multiplier input and the primitive element α of GF (2 ^r ) Power of 0 to (r−1), that is, r fixed coefficients from α ⁰ to α ^r−1 are multiplied, and the fixed coefficient of 0 element is further serially connected corresponding to each r-th component of the binary vector of the multiplicand symbol. The multiplication result of one symbol is obtained by taking the exclusive OR of the symbols of the r multiplication results obtained by multiplication, and by switching the switch logic gate circuit of 15 in FIG. 1 to the input pipeline register side of 13 The Galois field arithmetic unit of the embodiment functions similarly to the multiplication circuit of FIG. The division and addition are executed by including the function of another block not described in this embodiment. For example, the division can be configured by the inverse element ROM and the multiplier of this embodiment. After that, the value of the coefficient of each degree of the error locator polynomial is set in the switch logic gate circuit 14 on the input side other than the feedback side and stored in the registers 16, 17, and 18. The switch logic gate circuit 15 multiplies the output of 13 pipeline registers storing the multiplied symbols at the time of the function of the multiplication circuit and the fixed coefficient from α ⁰ to α ² , respectively, and multiplies the position number of the error locator polynomial of each degree of the error locator polynomial. The register output of 16, 17, and 18 for storing the feedback value of the intermediate value in which is substituted is switched, and the feedback is repeated by the number of steps corresponding to the code length n with the switch logic gate circuit 14 as the feedback side. This time
The 0 element is input to the 13 input pipeline registers, and 1 is set to all the bits of the 12 input pipeline registers so that the terms of α ³ order or higher do not affect. Since this processing is parallel processing, it is performed very quickly, and the root determination is performed by confirming with the 0-element determination circuit 11 whether the output symbol of the parity generator circuit 37 is 0-element. It can be obtained by the number of times. In this embodiment, the 0-element determination circuit
Since 11 is after the fixed coefficient multiplier, if the root of the error locator polynomial is α ⁰ , the 0-element judging circuit 11 cannot judge the root, but at this time, the coefficient of each degree of the error locator polynomial is Taking advantage of the fact that the exclusive OR of 0 is the same as the root being α ⁰ ,
When storing coefficient values in 7 and 18, it can be confirmed that they take an exclusive OR in parallel and have a root of α0. Here, when the root of the error locator polynomial is obtained by the 0-element determination circuit 11 during the feedback step, the switch logic gate 36 is switched to the fixed pattern generator 35 side before proceeding to the next feedback step. The feedback value registers 16, 17, and 18 store the coefficient values of the equation in which the error position is substituted into the error position polynomial. Since the fixed pattern generator 36 generates binary 00000010 symbols, parity is generated. Α ^{1 for the} generator circuit 10
Only the following term is output, and the pipeline register 37
The value of the expression when the error position is substituted into the polynomial obtained by differentiating the error position polynomial is stored. By using the value of this equation for the subsequent calculation of the error amount, the calculation amount of the polynomial can be reduced when calculating the error position. In this example, the number of errors is 2 or less for simplification of explanation.
In particular, when the number of error occurrences is large and the order of the error locator polynomial is high, that is, when the conventional method requires a long calculation time, the effect of reducing the calculation amount is large. As described above, in the present embodiment, the multiplication circuit of FIG. 4 is provided with a register for feeding back partial products of r fixed coefficient multipliers α ⁰ to α ^r−1 to store the intermediate result for each switch, Furthermore, a logic circuit that detects that the output symbol obtained by parity in the bit direction is 0 element, a logic circuit that generates 10 fixed symbols instead of the multiplicand, general multiplication, calculation of the root of the error locator polynomial, and error location By adding a logic circuit that switches the function of calculating the value of the polynomial that differentiates the polynomial, the effective utilization and speeding up of hardware assets are realized at the same time.

In the first embodiment of the present invention, it is not necessary to provide a dedicated register which is a storage element of 16, 17, 18 and may be a memory used in the process of calculating the coefficient of the error locator polynomial. It does not always have to be returned to the same area in the process of finding the root of the position polynomial. The same processing may be performed by using an OR gate circuit instead of using the 14 switch logic gate circuit. Next, a second embodiment of the present invention will be described with reference to the drawings. 2a-1 and 2a
2 is a flow chart of the second embodiment of the present invention, and FIG. 2B is a block diagram of a Galois field arithmetic unit applied to the second embodiment of the present invention. In FIG. 2b, 1, 2, 3, 4, 5, 6, 7, and 8 are Galois field fixed coefficient multipliers, 9 is an AND circuit, 10 is a parity generator circuit, and 12 and 13 are pipeline registers. The above is the same as in FIG. 11 is a 0 element determination circuit, 14, 15, 36
Is a switch logic gate circuit, and 16, 17, and 18 are registers for storing the coefficient input value of the error locator polynomial and the intermediate value obtained by multiplying the position number of the error locator polynomial of each degree, which are the same as those in FIG. Further, 19, 20, 21, 22, 23, and 24 are registers for storing the coefficient input value of the error locator polynomial and the intermediate value obtained by multiplying the position number of the error locator polynomial of each degree, and 25 is a fixed coefficient multiplier of α ^8. 26 is a logical switch circuit of one system, and 27 is a logical product circuit. Reference numeral 35 is an 8-bit fixed symbol generation circuit for generating a constant of binary 10101010. 37 is a pipeline register. These operations are performed on GF (2 ₈ ), and in the second embodiment, since the case where the number of errors t is 8 or less is handled, the number of storage elements is increased and the number of errors t is increased.
Since r exceeds r, a fixed coefficient multiplier is added only for calculating the order of r or more of the error locator polynomial. The operation of the Galois field arithmetic unit configured as described above will be described below with reference to FIG. 2B. When determining the values of the coefficients of each order of the error number and the error position polynomial, Figure 1 a-1 multiplication in the Galois field, is carried out as in Figure 1 a-2 or FIG. 4, alpha ⁸ The logic switch circuit 26 is set to the L level in order to remove the influence of the multiplier term of. At this time, the outputs of the AND circuit 27 are all at the L level, and the output of the multiplier 25 of α ⁸ does not affect the multiplication result. The calculation of the error locator polynomial is performed in the same manner as in FIGS. 1a-1 and 1a-2, but each degree of the error locator polynomial is initialized to a term of maximum 8th order according to the number of errors. If the number of errors is 7 or less, the root of the error locator polynomial and the value of the error locator polynomial are calculated. Can be calculated. In this way, after the error position is determined by the method of Chien, the multiplication circuit can be used again to obtain the value of the equation that differentiates the error position. When working as a normal Galois field multiplier, instead of 26 logic switches
You may substitute 0 element in 24 registers.

As described above, according to the method of the present invention, many parts of the multiplier, which is a part of the Galois field arithmetic unit of the code error check / correction device, are used to calculate the value of the differential expression of the error locator polynomial. It can be used and this calculation can be done quickly and easily. In particular, when the number of error occurrences is large and the next equation of the error locator polynomial becomes high, that is, when the conventional method requires a long calculation time, the effect of reducing the calculation amount is large. In this way, by sharing high-speed decoding and small hardware at the same time by sharing hardware assets, it is possible to practically decode a recording medium having a high raw error rate in an optical disk device or the like that requires high speed and high functionality. The effect is great because it can be done.

[Brief description of drawings]

FIG. 1a is a flow chart of the first embodiment of the present invention, FIG. 1b is a block diagram of a Galois field arithmetic unit applied to the first embodiment of the present invention, and FIG. 2a is of the present invention. 2 is a flow chart of the second embodiment, FIG. 2b is a block diagram of a Galois field arithmetic unit applied to the second embodiment of the present invention, and FIG. 3 is a block diagram of a Galois field arithmetic unit in a conventional example. FIG. 4 is a block diagram of a Galois field multiplication circuit in the conventional example. 1 ... α ⁰ Galois field fixed coefficient multiplier, 2 ... α ¹ Galois field fixed coefficient multiplier, 3 ... α ² Galois field fixed coefficient multiplier, 4 ... α ³ Galois field fixed coefficient multiplier, 5 ... ... α ⁴ Galois field fixed coefficient multiplier, 6 ... α ⁵ Galois field fixed coefficient multiplier, 7 ... α ⁶ Galois field fixed coefficient multiplier, 8 ... α ⁷
Galois field fixed coefficient multiplier, 9 ... AND circuit, 10 ... Parity generator circuit, 11 ... 0 element determination circuit, 12 ...
Pipeline register circuit, 13 …… Pipeline register circuit, 14 …… Switch logic gate circuit, 15 …… Switch logic gate circuit, 16 …… Register circuit, 17 …… Register circuit, 18 …… Register circuit, 35 …… Fixed pattern generator circuit, 37 ... Pipeline register circuit.

Claims (2)

[Claims] 1. A calculation is performed by substituting the position number into a coefficient value of each degree of an error locator polynomial of degree t of a Reed-Solomon code whose codeword is composed of elements of a Galois field GF (2 ^r ) and the error locator polynomial. A storage element group for storing intermediate calculation results of (t + 1) symbols or more in each order, a means for storing coefficient values in the storage element, and the Galois field GF (common to the first arbitrary 1-symbol input 2 ^r ) from 0 of the primitive element α (r−
1) Exponentiation, that is, it is multiplied by r fixed coefficients from α ⁰ to α _r−1, or within the r number (t + 1)
A group of r multipliers for multiplying a symbol storage element group by a fixed coefficient from α ⁰ to α ^t, and an even-numbered bit 0 and an odd-numbered bit starting from the 0th least significant bit of GF (2 ^r ). A fixed coefficient generating circuit for generating a symbol having a value of 1, and α ⁰ to α _r-1 corresponding to the lower 0th bit to the (r-1) th bit of the binary representation of the second arbitrary 1-symbol input. Means for switching the ^r fixed coefficients of 0 to fixed coefficients of 0 element on the Galois field GF (2 ^r ), and means for switching the second 1-symbol input to fixed coefficients output by the fixed coefficient generating circuit, Means for supplying a selected result to the input of the multiplier group by using the first arbitrary symbol and the value of the output of the storage element group as input, and r means of the results obtained by the multiplier group. Exclusive theory for each component of binary vector of symbol R odd / even decision unit groups that take the sum and obtain a result of 1 symbol, means for detecting whether the output symbol of the odd / even decision unit group is 0 element, and (t + 1) symbols obtained by the multiplier group In a Galois field arithmetic unit equipped with means for feeding back and storing the output of the above in the storage element group, in the case of performing the Galois field multiplication, the first arbitrary 1 symbol input from α ⁰ to α _r-1 Multiplying by r fixed coefficients and corresponding to the 0th bit to the (r-1) th bit of the binary representation of the second arbitrary 1-symbol input, if each bit is 0, the above α ⁰ to α _r-1 The r fixed coefficients are switched to fixed coefficients of 0 element on the Galois field GF (2 ^r ) and the multiplication result is obtained as the output symbol of the oddity judgment unit group, and the error position number and the differential of the error position polynomial are obtained. the SL corresponding to alpha ^t of the fixed coefficient multiplier in the case After storing each tth coefficient of the error locator polynomial in the element group, at least 1 from the lower order to the tth bit is given as the second 1-symbol input and the corresponding storage element is input as each input of the multiplier. Each of them is selected, and the multiplication result of the (t + 1) symbol by the multiplier is fed back to each of the storage elements, and when the output of the oddness judgment device group becomes 0 element, the feedback is temporarily stopped and the number of times of feedback is returned. After obtaining the number of error positions, the output of the fixed coefficient generating circuit is given as the second one-symbol input, and the result of the differential operation of the error position polynomial is obtained at the output of the oddity judgment unit group. A Galois field arithmetic method, characterized in that the above-mentioned operation is repeated until the number of times of returning reaches the code length −1 times. 2. A storage element group for storing coefficient values of each degree of an error locator polynomial of degree r or higher and intermediate results at each degree calculated by substituting the number of error locators into the error locator polynomial, and the r
The output of the memory element group corresponding to the next higher number of error positions alpha ^r
The fixed coefficient multiplier group described above and means for switching the fixed coefficient of the fixed coefficient multiplier group of α ^r or more to 0 element are provided.
2 of (t + 1) symbols that are a total of r + 1 or more of the multiplication result obtained by the fixed multiplier group of ⁰ to α _r−1 and the multiplication result obtained by the fixed multiplier multiplier group of α ^r or more. Exclusive OR for each component of the original vector 1
When a group of r odd-even decision units for obtaining a symbol result is provided and the Galois field multiplication is performed, the first arbitrary 1-symbol input is multiplied by r fixed coefficients from α ⁰ to α _r−1. And if each bit of the lower 0th bit to the (r-1) th bit of the binary representation of the second arbitrary 1-symbol input is 0, then the corresponding _r fixed coefficient multiplications from α ⁰ to α _r-1 The fixed coefficient of the unit group is switched to a fixed coefficient of 0 element on the Galois field GF (2 ^r ) and the α
^When the output of the fixed coefficient multiplier group of ^r or more is provided with a means for supplying 0 element and the multiplication result is obtained at the output of the odd / even decision unit group and the number of error positions of the rth order or more is obtained, When 1 is given to each bit as the second 1-symbol input of, and the output of the fixed coefficient multiplier group of αr or more is input to the input of the odd-and-even decision unit group, the differential of the error locator polynomial is calculated. Is an output of the fixed coefficient generation circuit as a second arbitrary 1-symbol input and
Starting from the r-th fixed coefficient multiplier group of ^r or more, the even-numbered fixed coefficient multiplier outputs 0 element and supplies it to the input of the odd / even decision unit group, and the same procedure is performed. The Galois field arithmetic method according to claim 1.