JPS63146619A - Arithmetic unit for galois field - Google Patents

Abstract

PURPOSE:To attain effective utilization of the hardware resource and the high speed processing by providing a register feeding back a partial product by a fixed coefficient multiplier and storing the intermediate result of each step, and adding a logic detecting whether or not an output symbol is '0' element and a logic switching two kinds of functions of a general multiplication and a calculation of an error location polynomial. CONSTITUTION:A coefficient of each order number of an error location polynomial is stored in registers 16-18 by setting a switch logic gate circuit 14 to an input side not being the feedback position. A switch logic gate circuit 15 switches an output of a pipeline register 13 and outputs of the registers 16-18 storing the feedback value of an intermediate value being the result of multiplication of fixed coefficients from a<o> to a<t> and substitution of position number of the error location polynomial. Then, the switch logic gate circuit 14 is thrown to the feedback position and the feed back is repeated by a step number corresponding to the code length (n) and a '0' element detection circuit 11 obtains roots of the error location polynomial. Thus, many parts of multipliers being a part of the Galois field arithmetic unit are used to obtain roots of the error location polynomial and the arithmetic operation is processed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a Galois field arithmetic device used in a code error check and correction device used when recording and reproducing data on a medium such as an optical disk.

BACKGROUND OF THE INVENTION In recent years, data recording and reproducing devices using optical disks have been actively developed. Although optical disk memory can record a larger amount of data than magnetic disks, it has the disadvantage of a high raw error rate of the recording medium.

A common method is to add an error check and correction code to the data during recording, record both the data and the error check and correction code on the optical disc, and use the error check and correction code to detect and correct data errors during playback. used for. A Reed-Solomon code with a minimum distance d of approximately 17 is a type of error checking and correcting code that has attracted attention in recent years. However, decoding such a code with a large minimum distance is very complicated and requires a long time or a large circuit, and it is common practice to perform decoding using software such as a microcomputer at the expense of time. Decoding in a Reed-Solomon code sequentially calculates the syndrome, estimates the number of errors, calculates the coefficients of the error locator polynomial, calculates the error position, and calculates the error value. Evaluating the maximum amount of these calculations using the number of additions or multiplications in Galois field calculations, we can calculate the syndrome, calculate the error location, estimate the number of errors, and calculate the coefficients of the error location polynomial.
It is often the order of the calculation of the error value. Syndrome calculations have a significant impact on decoding speed, so parallel processing hardware is used even when executed using software, but when high speed is required, microprogramming techniques are used instead of pure hardware. Other processes may also be performed at a speed close to that of hardware. At this time, it is possible to estimate the number of errors and solve the error value o total x at a certain speed using algorithms such as Berlekamp-Massey or Euclid's algorithm, but it is difficult to calculate the error position at high speed. Calculation of error location involves solving a t-order error location polynomial for t errors, but it has been proven that higher-order equations of order 6 or higher cannot be solved algebraically, so if there are 5 or more errors, If it is determined that there is, Chien's method of substituting all possible error positions into the error position polynomial and finding the roots must be used. The operation of the conventional example will be described below with reference to the drawings.

FIGS. 3 and 4 show a part of the Galois rest arithmetic circuit used in conventional correction processing.

In FIG. 3, 11 is a zero element determination circuit, 12.13 is an input vibe line register, 28 is a memory, 29 is a Galois field multiplication circuit, 3o is a Galois field addition circuit (exclusive OR operation circuit), and 31.32 is a Galois field multiplication circuit. Switch logic gate circuit, 33
is a power generation circuit (position number generation circuit) of the primitive element α.

This calculation is performed on the GF (28). First, the received word read from the optical disk and demodulated is dinterleaved and then input to a code error detection circuit, that is, a syndrome calculation circuit. If all of the obtained syndromes are not 0, it is determined that there is an error, and this syndrome is sent to the Galois field arithmetic circuit that estimates the number of errors and calculates the coefficients of the error position polynomial. It calculates the position. The syndromes of the minimum distance (d-1) are sent from the syndrome calculation circuit to the memory 28, and the multiplier 29 and the adder 30, or control logic based on a microprogram (not shown in the figure), backlight memory, etc. The number of errors t and t
+1 error locator polynomial coefficients of each order including the 00th order are calculated and stored. Thereafter, the root of the error locator polynomial is found using the same Galois rest arithmetic circuit using Chien's method.

For simplification, let's assume that there are two errors.If we want to find the root of 1x+ko=o in the erroneous position polynomial k The switch logic gate circuit is moved to the position number generation circuit side of 33, and Re of 31 is set to 2. 1. ko,
2. 1. The coefficients are sequentially substituted into Ra of 12, O, a, a, O, a, a, and so on. At this time, the output of 30 adders is 2+＠※0゜k 1+ (k 2 ) after pipeline
Mα, k o + (k 1 + k 2 *a)
*α.

k +@+o, k + (k)ryal, 0+
(2+*a)*a for k1+, and the root of the error locator polynomial is determined every third time. Note that the above equations are all operations on the Galois field, the operator + indicates addition, * indicates multiplication, and @ indicates an indefinite value. FIG. 4 shows the inside of the 290 multiplication circuit. In the figure: 1.2, 3, 4, 5, 6° 7.8
9 is a Galois field fixed coefficient multiplier, and 9 is an AND circuit that multiplies the output of each fixed coefficient multiplier by a zero element in series when each bit of the 12 pipeline registers is 0. Each bit is provided for the output. Further, 1° is a parity generator circuit which performs an odd-even judgment for each order of the binary vector representation of all the symbols of the multiplication result.

Problems to be Solved by the Invention However, with the above configuration, it is extremely difficult to increase the speed, and the worst-case decoding time is dominated by Chien's error location search. The conventional example cited here is called the generalized Horner's method, and although it is a method that can speed up to some extent, it is possible to reduce the number of errors and the Galois field of about n*(t+1) for code length n. Multiplication and addition are each required, n=13
0. When t=8, it takes 1170 microsteps. It is also possible to install dedicated hardware to increase speed, but the amount of circuitry increases too much.
This had the problem of decreasing practicality.

In view of the above problems, the present invention provides a Galois field arithmetic device that achieves both high speed and small amount of hardware.

Means for Solving the Problems In order to solve the above problems, the Galois field arithmetic device of the present invention uses a t-th order error locator polynomial of a Reed-Solomon code whose codeword is composed of elements of the Galois field GF(2''). a storage element group for storing intermediate calculation results of (1+1) symbols or more for each degree calculated by substituting the coefficient value of each degree and the number of positions into the error locator polynomial; and means for storing the coefficient value;
GF (2r
) from 0 to the (r-1) power of the primitive element α, that is, α0
a group of r multipliers for multiplying a storage element group of up to r (t + 1) symbols by fixed coefficients from α to αt; The r fixed coefficients of the multiplier are G
F(2r); means for switching with a zero-element fixed coefficient on F(2r); and means for switching the first arbitrary symbol and the value of the output of the storage element group as inputs and supplying the selected result to the input of the multiplier group; A two-dimensional vector of r symbols as a result obtained by the multiplier group. r adder groups that add each r-order component to obtain a one-symbol result, and an output symbol of the adder group is 0 elements. means for detecting whether there is a coefficient value, means for feeding back and storing the output of the (1+1) symbol obtained by the multiplier group in the storage element group, and means for switching the input of the storage element group into the coefficient value and the multiplier output. We are prepared.

Further, the Galois field arithmetic device of the present invention provides output symbols of a storage element group that stores coefficient values of each degree of an error locator polynomial of degree r or higher and intermediate results at each degree calculated by substituting the number of positions into the error locator polynomial. A total of one or more multiplication results obtained by a fixed coefficient multiplier group of αr or more, a fixed coefficient multiplier group of α0 to αr−1, and a multiplication result obtained by a fixed coefficient multiplier group of r or more. A group of r adders that add each r-dimensional component of a two-dimensional vector of (1+1) symbols to obtain the result of one symbol, and a group of r adders that add each r-order component of (1+1) symbols, and a group of r adders that obtain a result of one symbol. When multiplied by r fixed coefficients, means is provided for inputting a 0 element to the output of the fixed coefficient multiplier group whose inputs to the adder group are αr or more.

Function When decoding Reed-Don-Romon codes, after calculating the syndrome, estimating the number of errors in the event of an error, calculating the coefficients of the error locator polynomial, calculating the error value, etc. Galois field multiplication is performed for one symbol input. Commonly, α0 to αr of the multiplier from O to (-1) power of the primitive element α of GF(2r)
If it is false, G
Switching to the zero element fixed coefficient on F(2r), the obtained r
It is possible to carry out the procedure by performing the exclusive OR of each r-order component of a two-dimensional vector of symbols resulting from multiplication to obtain the result of one symbol.

After this, using the same hardware assets, the memory output that stores the coefficient value calculation results from the 0th order to the tth order of the erroneous position polynomial is multiplied by the fixed coefficients α0 to αr, and the multiplication results are applied for each order. Exclusively OR each of the r-dimensional two-dimensional vector components of the r symbols obtained by the fixed coefficient multiplier group while returning to the memory, obtain the result of one symbol, and assign the position to the error locator polynomial. Obtain the calculated result after substitution. If the number of errors t is larger than (r-1), among the output symbols of the storage element group that stores the intermediate results of each order calculated by substituting the number of positions into the error locator polynomial, the output symbols of the first order or higher are additionally αr or more. A fixed coefficient multiplier group of αr or more and a fixed coefficient multiplier group of α0 to α
A two-dimensional vector of one or more (1+1) symbols in total of the multiplication results obtained by the fixed coefficient multiplier group up to r-1. Exclusive OR of each r-dimensional component is performed and the result of one symbol is obtained in the same way. obtain.

Embodiment Hereinafter, a Galois field arithmetic device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of the invention.

In FIG. 1, 1.2, 3, 4, 5, 6, 7.8 is a Galois field fixed coefficient multiplier, and 9 is an AND circuit for multiplying 0 elements. Further, 1o is a parity generator circuit, and 12.13 is a pipeline register, which is the same as the configuration shown in FIG. 4. 11 is a zero element determination circuit;
4.16 is a switch logic gate circuit, 16, 17.18
is a register that stores an intermediate value obtained by multiplying the coefficient input value of the error locator polynomial and the number of positions of the error locator polynomial of each degree. These operations are performed on GF(2''), and the first embodiment deals only with cases where the number of errors is 2 or less.

The operation of the Galois field arithmetic device configured as described above will be explained below with reference to FIG.

When calculating the number of errors and the value of the coefficient of each degree of the error locator polynomial by multiplication, division, and addition processing on the Galois field of syndromes obtained by Berlekamp-Massey, Euclid's algorithm, etc., multiplication is a one-symbol multiplicand. The input is commonly multiplied by r fixed coefficients from 0 to (r-1) powers a to α of the primitive element α of GF(2r), and each r-dimensional component of the two-dimensional vector of the 1-symbol input multiplier is Correspondingly, GF (
2r) r obtained by further multiplying the 0-element fixed coefficient above in series
Since each r-dimensional vector of two-dimensional vectors of the symbols of the multiplication results is subjected to exclusive OR, the result of one symbol is obtained.
By switching the 16 switch logic gate circuits in FIG. 1 to the 13 input vibe line register side, the Galois field arithmetic device of this embodiment functions similarly to the multiplication circuit in FIG. 4. Division and addition are executed by including the functions of another block not described in this embodiment. For example, division can be implemented by the backlight ROM and the multiplier of this embodiment. After this, the value of the coefficient of each degree of the erroneous position polynomial is set to 1
The switch logic gate circuit No. 4 is set to the input side other than the feedback side and stored in the registers No. 18, 17, and 18. The switch logic gate circuit 15 multiplies the outputs of 13 pipeline registers that store input symbols when the multiplication circuit functions by fixed coefficients α to a, respectively, and substitutes the number of positions of the error locator polynomial of each order of the error locator polynomial. 16, 17, and 18 register outputs that store intermediate feedback values, and 14 switch logic gate circuits are set to the feedback side, and feedback is repeated by the number of steps corresponding to the code length n. The root of the error locator polynomial is determined by the detection circuit. At this time, enter 0 into the input vibe line register 18, leave the corresponding bit set to 1 in the input vibe line register 12, and execute multiplication by a power of α. do it like this. Since this processing is parallel processing, it is performed at a very high speed, and by checking whether the output symbol of the parity generator is a zero element, the root is determined, and the position of the error can be obtained by the number of feedbacks. As described above, in this embodiment, a register is provided to feed back the partial products of the r fixed coefficient multipliers from α0 to αr-1 in the multiplier circuit of FIG. 4, and to store the intermediate results for each step. We have added logic to detect whether the output symbol with direction parity is 0 elements, and logic to switch between two types of functions: general multiplication and error locator polynomial calculation, making effective use of hardware assets and high speed. simultaneously.

In addition, in the first embodiment of the present invention, 16°, 17°1
It is not necessary to provide a memory element dedicated to the register, which is the storage element of No. 8, but it may be a memory used in the process of calculating the coefficients of the error locator polynomial, and it must always be returned to the same area in the process of calculating the roots of the error locator polynomial. It's not something that should be done. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of a Galois field arithmetic device showing a second embodiment of the present invention. In the same figure, 1.2, 3, 4, 6, 6° 7.8
is a Galois field fixed coefficient multiplier, and 9 is an AND circuit that multiplies 0 elements. Further, 1σ is a parity generator circuit, and 12.13 is a pipeline register, which are basically the same as the configuration shown in FIG. 4. 11 is a zero element determination circuit, 14°16 is a switch logic gate circuit, 15
, 17, and 18 are registers for storing coefficient input values of the error locator polynomial and intermediate values multiplied by the number of positions of the error locator polynomial of each degree, and these registers have the same structure as in FIG. Further, 19, 20, 21, 22, and 23.24 are registers that store the coefficient input values of the error locator polynomial and intermediate values multiplied by the number of positions of the error locator polynomial of each order, and 26 is an α8 fixed coefficient multiplier. .

In addition, 26 is a logic switch circuit of one system, and 2A is 0
It is an AND circuit that multiplies elements. These operations are GF(
2"), and in the second embodiment, since the number of errors t is 8 or less, the number of storage elements is increased and a fixed coefficient multiplier is installed to compensate for the number of errors t exceeding r. It is added exclusively for calculation of orders of 1 or more of the error locator polynomial.

The operation of the Galois field arithmetic device configured as described above will be described below with reference to FIG. When calculating the number of errors and the value of the coefficient of each degree of the error locator polynomial, multiplication is the first
This is carried out in the same manner as in the case shown in the figure or in FIG. 4, but in order to eliminate the influence of the multiplier term of α, 26 logic switch circuits are set to the L level. For this reason 10
The L level is input to the parity generator ', and does not affect the multiplication result. Further, if the number of errors is 7 or less, the calculation can be performed without any problem by initializing the register corresponding to the unused order to 0 element. Note that when operating as a normal Galois field multiplier, 0 elements may be assigned to 24 registers instead of 26 logic switches. Calculation of the error locator polynomial is performed in the same manner as in FIG. 1, but each order of the error locator polynomial is initially set up to a maximum of 8th order depending on the number of errors. After the error position is determined by Chien's method in this manner, the amount of error can be determined using the multiplication circuit function again, and the data is rewritten to complete the error correction process.

Effects of the Invention As described above, according to the present invention, many parts of the multiplier, which is a part of the Galois field arithmetic unit of the code error check and correction device, can be used for rooting the error locator polynomial.
Moreover, these operations can be performed extremely fast. In this way, by sharing hardware assets, high-speed decoding and small hardware can be achieved at the same time, making it practical to decode recording media with high raw error rates in Akira disk devices that require high speed and high functionality. The effect is great because it can be carried out.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, FIG. 3 is a block diagram of a conventional Galois rest arithmetic circuit, and FIG. 4 is a block diagram of a conventional Galois rest arithmetic circuit. It is a block diagram of the Galois field multiplication circuit in the same conventional example. 1...α0 Galois field fixed coefficient multiplier, 2...
...αr Galois field fixed coefficient multiplier, 3...α
Galois field fixed coefficient multiplier, 4......α3 Galois field fixed coefficient multiplier, 6......a Galois field fixed coefficient multiplier, 6......α5 Galois field fixed coefficient multiplication device, 7...α6 Galois field fixed coefficient multiplier, 8...
...α7 Galois field fixed coefficient multiplier, 9...
AND circuit, 1o... Parity generator circuit, 11... Zero element judgment circuit, 12...
Pipeline register circuit, 13... Pipeline register circuit, 14... Switch logic gate circuit, 16... Switch logic gate circuit, 1
6...Register circuit, 17...Register circuit, 18...Register circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3

Claims (2)

[Claims] (1) Coefficient values of each order of the t-th order error locator polynomial of a Reed-Solomon code whose codeword is composed of elements of the Galois field GF(2^r) and each coefficient value calculated by substituting the number of positions into the error locator polynomial. a storage element group for storing intermediate calculation results of (t+1) symbols or more in order; means for storing coefficient values in the storage elements; The primitive element α of ^r) is multiplied by r fixed coefficients from 0 to (r-1) powers, that is, from α^0 to α^r^-^1, or (t+1) symbols that are within the above r numbers. α^0 for the memory element group of
a group of r multipliers that multiply by fixed coefficients from to α^t;
The r fixed coefficients are switched to zero-element fixed coefficients on the Galois field GF(2^r) corresponding to each r-dimensional component of a second arbitrary one-symbol input two-dimensional vector different from the above. means for switching the first arbitrary symbol and the value of the output of the storage element group as inputs and supplying the selected result to the input of the multiplier group; A group of r odd-even determiners that performs exclusive OR of each r-order component of a two-dimensional vector of r symbols to obtain a result of one symbol, and an output symbol of the group of odd-even determiners is 0.
means for detecting whether the output of the (t+1) symbol obtained by the multiplier group is fed back to the storage element group, and inputting the input of the storage element group to the coefficient value and the multiplier A Galois field arithmetic device comprising: an output; and means for switching. (2) The output symbol of the storage element group that stores the coefficient value of each degree of the error locator polynomial of degree r or higher and the intermediate result of each degree calculated by substituting the number of positions into the error locator polynomial is α
A fixed coefficient multiplier group of ^r or more, and the above α^0 to α^r
Binary of (t+1) symbols with a total of r or more of the multiplication results obtained by the fixed coefficient multiplier group up to ^-^1 and the multiplication result obtained by the fixed coefficient multiplier group of α^r or more Take the exclusive OR of each r-dimensional component of the vector and calculate 1
A group of r odd-even judges that obtain the result of a symbol, and an arbitrary
α^0 to α^r^-^1 in common for symbol input
Claim 1, further comprising means for causing the output of the fixed coefficient multiplier group of α^r or more to output an element 0 to the input of the odd-even determiner group when r fixed coefficients are multiplied by up to r fixed coefficients. Galois field arithmetic device as described in .