RU2115231C1 - Data coding-decoding device - Google Patents

Abstract

FIELD: communication engineering. SUBSTANCE: device has input-output unit 1, common bus 2, storage unit 3, first, second and third buffer registers 4,5 and 6, first and second delay assemblies 7 and 8, multiplier 9, switch 10, unit of modulo 2 adders 11, first, second and third units of switches 12,13 and 14, first, second and third OR gates 15,16 and 17, sequential data input-output 18, clock input 19, starting input 20, parallel data inputs-outputs 21, and control inputs-outputs 22. EFFECT: enhanced noise immunity of data transmission. 19 dwg

Description

 The invention relates to communication technology and can be used in data transmission equipment for the implementation of error-correcting coding and decoding of information by a cascade code.

 Known devices for encoding [1] and decoding [2, 3, 4] information using non-binary codes, such as Reed-Solomon codes.

 These devices are implemented in hardware and therefore are complex and unreliable in operation. In addition, they have a fixed structure and therefore cannot be reconfigured to use other codes, which is necessary when changing the transmission conditions.

 The indicated drawbacks are deprived of devices using a software implementation of the encoding and decoding procedures. Currently designed data transmission equipment (ADF), as a rule, contains a microprocessor, which, along with solving problems of managing information flows and their processing, can be used to carry out encoding and decoding of information, especially considering the possibility of time diversity of these procedures .

 Closest to the proposed technical solution and therefore selected for the prototype is a device for encoding-decoding information [5]. The device comprises an input-output unit, the outputs of which through the first memory unit are connected to the first inputs of the input-output unit. The outputs of the first memory block through series-connected the first block of adders, the second block of read-only memory and the second block of adders are connected to the second inputs of the input-output block. The input-output block contains a microcomputer connected via one inter-module interface to the serial-parallel interface, the input-output of which is the serial input-output of the input-output block, and through the other inter-module interface to the parallel interface, the parallel inputs and outputs of which are parallel inputs outputs of the input-output block.

 The known device operates as follows. In the encoding mode, information in the parallel code is fed to the parallel inputs and outputs of the input-output unit; according to the program recorded in the microcomputer, it is stored in its memory and fed into the address inputs of the first memory unit as an address. At these addresses, verification characters are read and written to the memory of the microcomputer. The last program organizes the serial output of the code combination, consisting of information and test characters, through a serial-parallel interface to the communication channel.

 In decoding mode, information from the communication channel in the form of code combinations of a systematic code (which has information and verification symbols separated) is fed to the serial input-output of the input-output unit and is stored in the program in the memory of the microcomputer. After that, information symbols of the code combination are sent to the address inputs of the first memory block. At these addresses, verification characters are read, which enter the first inputs of the first adder block, the second inputs of which receive verification characters received from the communication channel. Matching test characters means receiving a code combination without errors. Otherwise, a syndrome is formed at the output of the first adder block, which arrives at the address inputs of the second memory block. A combination of errors corresponding to this type of syndrome is read at these addresses. This combination arrives at the first inputs of the second adder block, the second inputs of which receive information symbols from the output of the input-output block. In this case, erroneous characters are inverted, and received without errors pass through the adder block without change. Corrected information enters and from the input-output unit through parallel inputs / outputs to the consumer.

Thus, the encoding and decoding of information in a known device is carried out in a tabular manner. The number of combinations that must be stored in the first memory block is 2 ^k , where k is the number of information bits in the code combination, and in the second memory block is 2 ^r , where r is the number of check characters. The known device can not work with large length codes, because with increasing k and (or) r memory amount _zu N = 2 ^k +2 ^r words that significantly complicates and makes the device unreliable.

 In practice, the values of k and r are limited by the capacity of microprocessors. Most microprocessors currently in operation have a capacity of 16-32. For noise-tolerant transmission of information over poor-quality communication channels, especially with grouping of errors, such a bit depth of code combinations is clearly not enough.

Improving the noise immunity of information transmission can be achieved by using long codes having acceptable implementation complexity, for example, BCH codes in the GF field (2 ^m ), in which the length of code combinations in terms of binary characters can be several thousand or even tens of thousands. Examples of the implementation of encoding-decoding devices in non-binary fields in hardware are given in [1, 2, 3, 4]. Their disadvantage lies in the complexity of implementation and the fixation of the structure.

 The known prototype device using the software implementation principle cannot use long codes and, therefore, at a fixed relative speed of information transfer has a low noise immunity of transmission.

 The objective of the invention is to increase the noise immunity of information transmission.

 The technical result achieved in solving the problem is to provide encoding and decoding of information using long non-binary codes, for example, cascading codes, in which the non-binary code of the PC is used as an external code.

 To solve this problem, an information encoding / decoding device containing an input / output unit and a memory unit connected by a common bus, as well as an adder unit modulo two, introduces three buffer registers, a multiplier, two delay nodes, a switch, and three key blocks and three elements OR. In this case, the information inputs of the first buffer register, the outputs of the first, second, and third key blocks and the first inputs of the switch are connected to a common bus. The outputs of the first buffer register through the multiplier are connected to the inputs of the first block of keys and to the first inputs of the block of adders modulo two. The outputs of the switch through the second buffer register are connected to the second inputs of the multiplier and to the inputs of the second block of keys, and through the third buffer register to the inputs of the third block of keys and the second inputs of the block of adders modulo two, the outputs of which are connected to the second inputs of the switch. The first, second and third control outputs of the I / O block are connected respectively to the control inputs of the first, second and third key blocks, the fourth to the write input of the first buffer register, the fifth through the first OR element to the write input of the second buffer register, through the third OR element to the control input of the switch, and through the second delay node and the second element OR connected in series to the recording input of the third buffer register. The sixth control output of the input-output unit is connected to the second inputs of the second and third OR elements and through the first delay node to the second input of the first OR element. The seventh control output of the input-output unit is connected to the second inputs of the first and second delay nodes. In this case, the serial information input-output, parallel information inputs and outputs, control inputs and outputs, clock and start inputs of the input-output unit are the corresponding inputs and outputs of the device.

 The proposed device provides coding of information with a cascade code [6, p. 228], consisting of two codes, internal (n, k) and external (N, K), where n and N are the total number, and k and K are the number of information symbols in the combination of internal and external codes, respectively.

Binary short codes are used as the internal code, non-binary codes are used as the external code, for example, Reed-Solomon (PC) codes over the field GF (2 ^m ), where m is the extension of the binary field.

As an example, the proposed device uses an internal (24, 16) code with a generating polynomial
g (X) = x ⁸ + x ⁷ + x ⁴ + 1, (1)
correcting single errors, detecting all double errors of a higher multiplicity.

As an external code, the PC code (241, 225) is used over the field GF (2 ⁸ ) with the generatrix of the field
F (X) = x ⁸ + x ⁴ + x ³ + x ² + 1 (2)
with a primitive field element α = 00000010.

На фиг. 1 представлена функциональная схема предлагаемого устройства; на фиг. 2 - функциональная схема блока ввода-вывода 1; на фиг. 3 - функциональная схема дешифратора 25 (пример); на фиг. 4 - функциональная схема параллельного порта ввода-вывода 24 (пример); на фиг. 5 - функциональная схема последовательного порта ввода-вывода 26 (пример); на фиг. 6 - функциональная схема микропроцессорного блока 23 (пример); на фиг. 7 показано распределение области кодирования ОЗУ (пример); на фиг. 8 изображена блок-схема алгоритма кодирования информации внешним кодом (пример); на фиг. 9 - блок-схема алгоритма кодирования информации внутренним кодом (пример); на фиг. 10 дано схематичное представление распределения ячеек ОЗУ для записи информации, принимаемой из канала связи (пример); на фиг. 11 представлена блок-схема алгоритма декодирования информации, закодированной внутренним кодом (пример); на фиг. 12 - блок-схема обобщенного алгоритма декодирования внешнего кода; на фиг. 13 - блок-схема алгоритма вычисления коэффициентов синдромного многочлена (пример); на фиг. 14 показаны временные диаграммы управляющих сигналов; на фиг. 15 изображена блок-схема алгоритма определения коэффициентов многочлена локаторов стираний (пример); на фиг. 16 - диаграмма состояний; на фиг. 17 - структура массива коэффициентов многочлена локаторов стираний; на фиг. 18 - блок-схема алгоритма определения коэффициентов модифицированного синдромного многочлена (пример); на фиг. 19 - блок-схема алгоритма определения коэффициентов многочлена локаторов ошибок (пример).The generating polynomial of the PC code has the form

In FIG. 1 presents a functional diagram of the proposed device; in FIG. 2 is a functional diagram of an input-output block 1; in FIG. 3 is a functional diagram of a decoder 25 (example); in FIG. 4 is a functional diagram of a parallel input / output port 24 (example); in FIG. 5 is a functional diagram of a serial input / output port 26 (example); in FIG. 6 is a functional diagram of a microprocessor unit 23 (example); in FIG. 7 shows the distribution of the RAM coding region (example); in FIG. 8 shows a block diagram of an algorithm for encoding information with an external code (example); in FIG. 9 is a block diagram of an information encoding algorithm with an internal code (example); in FIG. 10 is a schematic representation of the distribution of RAM cells for recording information received from a communication channel (example); in FIG. 11 shows a block diagram of an algorithm for decoding information encoded by an internal code (example); in FIG. 12 is a block diagram of a generalized external code decoding algorithm; in FIG. 13 is a block diagram of an algorithm for calculating the coefficients of a syndromic polynomial (example); in FIG. 14 shows timing diagrams of control signals; in FIG. 15 shows a block diagram of an algorithm for determining the coefficients of the polynomial of erasure locators (example); in FIG. 16 is a state diagram; in FIG. 17 is a structure of an array of coefficients of a polynomial of erasure locators; in FIG. 18 is a block diagram of an algorithm for determining the coefficients of a modified syndromic polynomial (example); in FIG. 19 is a block diagram of an algorithm for determining the coefficients of a polynomial of error locators (example).

 The operations of encoding and decoding information by the internal (binary) code are carried out programmatically: by the tabular method. Some difference lies in the operation of comparing the verification symbols received from the communication channel with the ones formed at the receiving location, which is performed in the proposed device in software and in the prototype in hardware.

The main difference of the proposed device from the prototype is the provision of encoding and decoding information in the GF field (2 ^m ), for which purpose the units that carry out operations in this field under the control of the microprocessor are introduced into the device.

 In this case, the encoding and decoding of information by a non-binary code is reduced mainly to three computational procedures: computations according to the Horner scheme, addition of products, multiplication by a common factor, carried out by the same device nodes. A change in the calculation procedure is provided by the processor by just changing the order in which the operands are written to the buffer registers without changing the operating mode of the device, which eliminates the use of extra commands.

где

, R - число проверочных символов кода PC;

- символы принятой кодовой комбинации;
α - примитивный элемент поля GF(2^m);
N - длина кодовой комбинации кода PC,
элемент α записывается в первый буферный регистр, символ C₁ - во второй буферный регистр, а последующие символы

- в третий буферный регистр, при этом результат вычисления получается сразу же при вводе символа C_j во втором буферном регистре. Благодаря такой организации вычисления наиболее сложная операция определения коэффициентов S_m осуществляется достаточно быстро.So, for example, when calculating the coefficients S _{m of the} syndromic polynomial according to Horner's formula [7, p. 175]

Where

, R is the number of check characters for the PC code;

- characters of the received code combination;
α is a primitive element of the field GF (2 ^m );
N is the length of the code combination of the PC code,
the element α is written in the first buffer register, the character C ₁ in the second buffer register, and subsequent characters

- in the third buffer register, while the result of the calculation is obtained immediately when you enter the character C _j in the second buffer register. Thanks to such organization of the calculation, the most complicated operation of determining the coefficients S _{m is} carried out rather quickly.

 Thus, for one “transfer” command, the following operations are performed: multiplication in the field, addition in the field, recording the result in the place of one of the factors with the possibility of continuing such calculations.

 Such a combination of hardware and software methods for the implementation of operations made it possible to optimally distribute computer time resources and ultimately ensure coding of information with long codes with acceptable implementation complexity and thereby increase the noise immunity of information transmission.

Compared with other technical solutions that implement the encoding and decoding of information in the field GF (2 ^m ), the proposed device is simpler. In fact, the hardware of the proposed device used for operations in the GF (2 ^m ) field contains three buffer registers, a multiplier, a switch, an adder unit modulo two, two delay circuits, three keys, and three OR elements.

 In the encoding device [1], in addition to other nodes, N-K shapers of check symbols are contained, each of which is comparable in volume with the hardware of the proposed device.

In the device for decoding the Reed-Solomon code [2], only for the operation of computing syndromes by the block of checks, NK sections are required, each of which contains three multipliers, four blocks of adders performing operations in the field GF (2 ^m ), the generator of elements of the field GF (2 ^m ), register, i.e. in volume larger than the hardware of the proposed device used for these purposes. It should be noted that in [2] the blocks for computing the polynomial of erasure locators and the block for solving the key equation are comparable with the block for computing the polynomial of generalized checks.

The set of computational operations in the Galois field GF (2 ^m ), implemented in [4], has low functionality and requires multi-cycle control circuits. The device performs the sum of only two works, and using it it is difficult to perform calculations according to the formula (1).

An analysis of these and other technical solutions [3] shows that, as a rule, the decoding procedure of a PC code is performed by a set of nodes, each of which performs any one operation with a total of about 10 (see further the generalized decoding algorithm, Fig. 12 ) The proposed device with a small set of hardware nodes and a microprocessor performs all these operations, which allows to achieve a technical result: providing encoding and decoding of information by long codes in the GF field (2 ^m ).

 In FIG. 1 presents a functional diagram of the proposed device. The device contains an input-output block 1, a common bus 2, a memory block 3, the first 4, the second 5 and the third 6 buffer registers, the first 7 and the second 8 delay nodes, a multiplier 9, a switch 10, an adder block modulo two 11, the first 12 , second 13 and third 14 key blocks, first 15, second 16 and third 17 OR elements, serial information input-output 18, clock input 19, start input 20, parallel information inputs-outputs 21, control inputs-outputs 22.

 The device has the following connections. The inputs and outputs of the input-output block 1, the memory block 3, the information inputs of the first buffer register 4, the first inputs of the switch 10 and the outputs of the first 12, second 13 and third 14 key blocks are connected to the common bus 2. The outputs of the first buffer register 4 through the multiplier 9 connected to the inputs of the first block of keys 12 and to the first inputs of the block of adders modulo two 11. The outputs of the switch 10 through the second buffer register 5 are connected to the second inputs of the multiplier 9 and to the inputs of the second block 13 of the keys, and through the third buffer register 6 to the inputs of the third block lyuchey and second inputs of the adders modulo two unit 11, which outputs are connected to second inputs of the switch. The first Q1, second Q2 and third Q3 control outputs of the I / O unit 1 are connected respectively to the control inputs of the first 12, second 13 and third 14 key blocks, the fourth Q4 - to the recording input of the first buffer register 4, the fifth Q5 - through the first element OR 15 to the recording input of the second buffer register 5, through the third OR element 17 to the control input of the switch 10, and through the second delay node 8 connected in series and the second OR element 16 to the recording input of the third buffer register 6. The sixth control output Q6 of the I / O unit 1 is connected ene to second inputs of the second 16 and third 17 and OR elements through the first delay unit 7 to the second input of the first OR gate 15. The seventh control output Q7 input-output unit 1 is connected to the second inputs of the first 7 and second 8 delay units.

 Serial information input-output 18, clock input 19, start-up input 20, parallel information inputs-outputs 21 and control inputs-outputs 22 of the input-output unit 1 are the corresponding inputs and outputs of the device.

 Buffer registers 4, 5 and 6 can be performed on the IMS K588IR1, key blocks 12, 13 and 14 - on the IMS 564KT3, the adder block 11 modulo two - on the IMS 564LP2 [9].

 The switch 10 can be performed on 16 pairs of keys implemented on the IC 564KT3. The control inputs of the even keys are combined and connected to the control input of the switch directly, and the odd keys through the inverter. Thus, the information inputs of the even keys are the first (A) inputs, and the odd keys are the second (B) inputs of the switch 10.

 The memory unit 3 contains a ROM implemented on the IC 573RF4, and RAM on the IC 537RU9.

 The central node of the device is a microprocessor unit 23, which is part of the input-output unit 1. During operation of the device in any of the modes, the microprocessor polls for signs of 2 nodes connected to the common bus, exposing each address in sequence, in order to identify a node ready for information exchange, and with a positive result, carries out this exchange. In the following examples of the implementation of the nodes of the device, the name of the control signals supplied to these nodes is given with reference to the processor K1801VM2 [7].

 The proposed device operates in the following modes: input-output information and encoding-decoding information.

 Information input-output mode.

 In FIG. 2 is a functional diagram of an input / output unit 1. An input / output unit 1 comprises a microprocessor unit 23, a parallel input / output port 24, a decoder 25, and a serial input / output port 26. The inputs and outputs of a microprocessor unit 23, a parallel input / output port 24 , serial I / O port 25 and the inputs of the decoder 25 are connected to a common bus 2.

 Decoder 25 has three groups of outputs. The first group of outputs gives seven control signals Q1 - Q7, which are necessary for the device to operate in the encoding-decoding mode of information. The second group of outputs gives the signals necessary to ensure the input / output of information by the parallel input / output port 24. The third group of outputs gives the signals necessary to provide the input / output of information by the serial input / output port 26.

 The parallel input-output port 24 is designed for the exchange of parallel information and control signals between the data terminal equipment (OOD) and the proposed device, which is carried out respectively through parallel information inputs and outputs 21 and control inputs and outputs 22.

 The serial input / output port 26 is intended for the exchange of serial information between the communication channel and the proposed device, carried out by the serial information input-output 18. In this case, the information received from the communication channel is accompanied by a clock frequency arriving at the clock input 19 and a sign of the beginning of the information arriving at launch input 20.

 In FIG. 3, as an example of implementation, a functional diagram of a decoder 25 is presented, which comprises a buffer register 27 connected in series, a binary decimal decoder 28, and a block of AND elements 30, the number of which is equal to the number of decrypted signals.

 The decoder works as follows. Bus 2 receives the address code of the node being interrogated at the information inputs of the buffer register 27, and the “Exchange” signal (SYNC as applied to the K1801BM2 processor), which fixes this address in the buffer register 27, to the control input of the record with some delay. After fixing the address from the control The output of the buffer register 27 is the signal "Confirmation", received via the address-data 2 bus to the microprocessor unit 23. From the output of the buffer register 27, the address combination is input to the binary decimal decoder 28, which converts the code Dres a position signal supplied to the block elements 29 and 30.

The microprocessor in the process of interaction with the nodes of the device performs two operations: reading and writing information. Therefore, each positional signal from the output of the binary decimal decoder 28 is fed to the first inputs of the two And elements, the second inputs of which receive the “Read” (DIN) or “Write” (DOIT) control signals from the microprocessor unit 23, while the And outputs signals are read or written information for the respective nodes of the device, arriving at the outputs of the decoder 24:
seven control signals Q1 - Q7, which are supplied to the outputs of the I / O unit 1, four control signals: "Read 1"("RE1"),"Read2"("RE2"),"Write1"("RF 1 ")," Reset "- to the parallel I / O port 24 and five control signals:" Read 3 "(" RE 3 ")," Read 4 "(" RE 4 ")," Read 5 "(" RE 5 " ), "Record 2"("RFP2") and "Record 3"("RFP3") - to the serial input-output port 26.

 If the node interrogated by the microprocessor operates only in one mode of reading or writing information, then the positional signal from the output of the decoder enters only one element I.

 The buffer register 27 can be implemented on the chip K588IR1, binary decimal decoder 28 - K564ID1, elements I - 564LA7 [8].

 Consider the operation of the device in the input-output mode of information through the parallel input-output port 24, an implementation example of which is shown in FIG. 4.

 I / O port 24 contains a buffer register for inputting 31 information, a buffer register for outputting 32 information, a trigger for input features 33, a trigger for features for output 34, two keys 35 and 36.

 Information from the OOD comes in parallel code to the inputs 21 of the input-output block 1 and then to the information inputs of the input buffer register 31, and the signal "Input" from the OOD to the input 22 of the input-output block 1 (Fig. 1) and further at the recording input of the buffer register 31, is recorded in the latter. At the same time, the “Input” signal is input to the input trigger trigger 33, setting it to state “1”, which is fed to the information input of the first key 35. The signal from the inverse output of the trigger 33 goes to the port output and then to the control input-output 22 of the input unit - output 1 in the OOD, signaling the prohibition of entering the next word of information (signal "Prohibition").

 The microprocessor, being in the cycle of polling the nodes of the device, periodically polls and analyzes the status of the key 35, giving the signal "Read 1" through the decoder 25, which is received at the control input of the key 35.

 If there is information in the input buffer register 31 at the output of the key 35, a signal will appear that goes to the output of the port and then to bus 2 as a sign of "Availability of information from the OOD". The microprocessor, having detected this symptom, reads information from the buffer register 31, for which it sets the “Read 2” signal through the decoder 25 to the reading input of the buffer register 31, while the information in the parallel code goes to the port output and then to bus 2.

 After recording information in RAM, the microprocessor through the decoder with the "Reset" signal resets the trigger 33, as a result of which the "Disable" signal is removed from the output of the trigger, allowing the input of the next word of information from the OOD.

 In the mode of outputting information, the latter via bus 2 enters the information inputs of the buffer register of output 32 and is fixed in it by the signal “Record 1”, which is fed to the recording input of the buffer register 32 from the microprocessor through the decoder 25.

 By the same signal, the trigger of the signs of the output 34 is set to the state "1", which through the control input-output 22 of the input-output unit is received in the OOD as a signal "Information availability". The signal from the inverted output of the trigger 34 is fed to the information input of the second key 36. The microprocessor, interrogating the key 36 with the “Read 1” signal, coming to the control input of the key 36 through the decoder 25, detects a busy sign of the buffer register 32 and therefore does not output the next word of information from RAM . OOD, upon detecting the signal “Availability of information”, issues a signal “Output”, which is received via the control input-output 22 of the input-output unit 1 to the read input of the buffer register 32, reading information from it, which is input-output 21 of the input-output unit 1 enters the OOD. Simultaneously with the “Output” signal, the trigger of the output flag is reset, as a result of which the flag “Availability of information” is reset and in the next cycle the word is allowed to be output from RAM to port 24.

 Buffer registers 31 and 32 can be implemented each of two IMS K588IR1, triggers 33 and 34 - on IMS 564TM2, keys 35 and 36 - on IMS 564KT3 [9].

 In FIG. 5, as an example of implementation, a functional diagram of the serial input / output port of information 26 is provided, which contains serial-parallel registers for inputting 37 and outputting 38 information, parallel buffer registers for inputting 39 and outputting information 40, binary-decimal counter 41, AND element 42, triggers 43 and 44, keys 45 and 46, OR elements 47 and 48.

Entering information is as follows. The information in the serial code from input-output 18, the clock frequency F _t from input 19 and the “Start” signal from input 20 of the input-output unit 1 of the device are supplied respectively to the information and recording inputs of the serial-parallel input register 37 and the installation input of the counter 41 ( through the element OR 48). In addition, the clock frequency F _t is also supplied to the counting input of the counter 41. The information is recorded in the register 37, and the counter 41 is set to zero and through the number of ticks equal to the word capacity, for example 16, through the AND element 42, which plays the role of a 16 clock decoder , gives a signal to the recording input of the parallel buffer register 39, fixing the information received at its inputs from the output of the serial-parallel input register 37. At the same time, the signal from the output of the And 42 element through the OR element 47 sets the trigger 44 in state "1", which is fed to the information input of key 45, signaling to the microprocessor that there is information from the communication channel. The microprocessor, being in a polling cycle, detects this signal by supplying a Read 3 signal to the control input of key 45 via bus 2 through decoder 25, after which it generates a Read 4 signal, which is transmitted via bus 2 through decoder 25 to the read input buffer register 39, reading from it the information that goes to the output of the port and then to bus 2. After that, the microprocessor generates a signal "Record 2", received via bus 2 through the decoder 25 to reset the trigger 44, setting it to state "0", as a result, reception becomes possible the next word of information.

 In the information output mode, the last one on bus 2 is input to the information inputs of the buffer register 40 and the “Record 2” signal, coming from the microprocessor via bus 2 through the decoder 25, is recorded in this register. At the same time, the trigger 44 is set to the zero state, which will be present at the information input of the key 45 and, when interrogated by the microprocessor, will indicate that the next information word cannot be entered into the buffer register 40.

 After writing the first word of information to the buffer register 40, the microprocessor on the bus 2 through the decoder 25 generates a signal "Read 5", coming through the OR element 48 to the installation input of the binary decimal counter 41, setting it to zero, to the first input of the trigger 43, setting it is in a single state, through an OR element 47 - to the recording input of a parallel-serial register for outputting 38 information, recording information in it from the outputs of the buffer register of output 40, and to the first input of trigger 44, setting it in a single state and thereby removing the ban on entering another word of information.

The signal from the output of the trigger 43 opens the key 46 and information under the action of the clock frequency F _t supplied to the clock input of the register 38, is issued to the input-output 18 of the input-output unit 1.

 The subsequent words of information are output to the buffer register 40 by the signals periodically issued after 16 cycles by the counter 41 through the And 42 element. 16 cycles after the last word has been written to the buffer register 40, the microprocessor sends a "Record 5" signal via bus 2 through the decoder 25, which resets trigger 43 to the zero state and thereby disconnecting the output of the register 38 from the communication channel. At the same time, in the polling cycle, the analysis of key 45 for the possibility of entering information is terminated.

 Serial-parallel registers 37 and 38 can be implemented on four ICs 564IR9, buffer registers 39 and 40 each on two ICs 588IR1, counter 41 - IC 564IE10, element I 42 - on IC 564LA7, triggers 43 and 44 - on IC 564TM2, keys 45 and 46 - on the IC 564KT3, the elements OR - on the IC 564LE5 [9].

 In FIG. 6 shows an example of the implementation of the functional diagram of the microprocessor unit 23 based on the processor K1801VM2. The microprocessor unit contains the actual processor 49, the shift register 50 and the OR element 51. The shift register and the OR element form the response signal generation circuit. The processor contains inputs and outputs AD0-AD15, through which the processor gives the addresses of the nodes being surveyed and receives or provides information, the "Confirmation" (AR) input, by which the processor receives a signal confirming that the decoder has received the address, the "Exchange" (SYNC) outputs, " Reading "(DIN)," Write "(DOIT), by which the processor generates signals entering the decoder when organizing its interaction with the device nodes, as well as the" Byte "output (WIBT), by which the processor generates a signal in RAM. This signal, together with the least significant bit of the address (zero), determines which of the RAM bytes is being written. For example, the value “0” of a signal means writing one of two bytes to RAM; the address “0” indicates which byte will be written specifically (low, high). The above processor outputs form a common bus 2.

 The shift register 50 is designed to delay the signals "Read" or "Write" and the formation of the signal "Response" for the processor at the input of RPLY. The “Response” signal indicates that in the mode of reading information by the processor from the interrogated node, this information is set on bus 2, and in the recording mode, the information is written to the node. The amount of delay provided by the shift register 50 is selected based on the reliable operation of the nodes interacting with the processor.

 The shift register 50 can be implemented on the IC 564IR2, the element OR on the IC 564LE5.

 The encoding-decoding mode of information.

 As mentioned earlier, in cascading code, information is double-encoded, first with an external non-binary code, such as a PC code, and then with an internal binary code. In the proposed device to increase its speed and reduce complexity, two-way coding of information by external code is used. To do this, the information is divided into blocks of 16 characters, with even bytes of all blocks form one strip, and odd bytes form another strip, each of which is encoded with an external PC code.

It is known [6, p.119] that the code polynomial C (x) can be represented as
C (x) = x ^NK • I (x) + t (x), (5)
Where
I (x) - information polynomial;
t (x) is the remainder of the division of the polynomial x ^NK • I (x) by the generator of the polynomial G (x).

 The operation of dividing one polynomial into another by “Column” consists in multiplying the canceled coefficient of the dividend by the divisor coefficients (coefficients of the forming polynomial), followed by the addition of the obtained products with the dividend coefficients. Thus, the encoding of information can be carried out using the operations of multiplication and addition. Moreover, in the proposed device, the multiplication operation, which requires a large expenditure of computer time, is carried out by the hardware, and the addition operation, which requires a small expenditure of computer time, is software.

 In FIG. 7 schematically shows the distribution of the RAM region used in encoding. This area contains six zones. In 1 and 2 zones, each 241 bytes in volume, information arrays of 1 and 2 bands are recorded, respectively. 5 and 6 zones duplicate 1 and 2 zones. In zones 3 and 4, the verification characters of the PC code will be recorded. The volume of 3 and 4 zones of each is 16 eight-bit words.

 The initial recording of information from the input-output unit is carried out simultaneously on the first strip in 1 and 5 zones, on the second strip in 2 and 6 zones.

Allocation of K memory cells for recording information symbols and N - K memory cells with the initial “zero” value and the subsequent recording of test characters of the PC code in them means the automatic multiplication of the information polynomial I (x) by x ^NK in accordance with expression (5).

Subsequently, in the process of encoding with the PC code, the contents of zones 1 and 2 are constantly updated to store intermediate results of dividing the polynomial x ^NK • I (x) by the generating polynomial G (x) (the coefficients of the generating polynomial are stored in ROM), while the contents of 5 and 6 zones remain unchanged. As a result of the division, the verification characters of the PC code (the remainder of the division) will be recorded in zones 3 and 4.

 The coding of information is carried out according to the program stored in the ROM of the memory unit 3, in accordance with the algorithm presented in Fig. 8. Algorithm operators have the following purpose.

 The first operator writes to the general purpose register (RON) 1 of the microprocessor the number K of information symbols of the PC code (K = 225).

The second operator reads the highest coefficients (bytes) of the polynomial x ^NK • I (x) from zones 1 and 2 of the RAM of memory block 3 and sends them to the first buffer register 4, setting the address of this register on bus 2. The decoder 25 decrypts this address and the control signal Q4 supplied to the recording input of this register, fixes this coefficient in it (figure 1).

 The third operator checks the end of the encoding with an external code, for which the contents of RON 1 are reduced by one and compared with zero. If the result differs from zero, the transition to the fourth operator is performed, otherwise, the transition to the program for encoding information with internal code.

 The fourth operator writes to RON 2 of the microprocessor a number equal to (N-K - 1), in our example (N-K-1) = 15.

The fifth operator writes from the ROM the next (at the first stage of dividing the polynomials x ^NK • I (x) and G (x) - senior) coefficient of the polynomial G (x) through switch 10 into the second buffer register 5, setting the address 2 for this this register. The decoder 25 decodes this address and the control signal Q5 through the first element OR 15 captures this coefficient in the second buffer register 5. At the same time, at the output of the multiplier 9, the result of multiplying the contents of both registers is obtained.

 The sixth operator sends the result of the multiplication to RON 3 of the microprocessor, for which the microprocessor through the decoder 25 generates a control signal Q1, as a result of which the first block of keys is opened and the result of the product is sent via bus 2 to RON 3.

The seventh operator in the arithmetic logic unit (ALU) of the microprocessor contains the contents of RON 3 with the current coefficients of the polynomial stored in zones 1 and 2, following the order of magnitude of the reduced coefficient. At the first stage, when the leading coefficient of the polynomial x ^NK • I (x) is reduced, such current coefficients are the coefficients following the leading one. In this case, the result of addition is recorded at the address of the current coefficient, and the combination of these coefficients forms an intermediate (modified) polynomial, with the coefficients of which at the subsequent stages of division, the operations of multiplication and addition will be performed.

 The eighth operator checks at the end of the procedure of multiplying the contents of the first and buffer registers with the coefficients of the generatrix of the polynomial G (x), for which the contents of RON 2 are reduced by one and compared with zero. If the subtraction result differs from zero, the transition to the fifth operator is performed; otherwise, the transition to the second operator is performed, starting the procedure for reducing the next highest coefficient of the modified polynomial.

 In the proposed device, the encoding and decoding of information is carried out immediately in two bands. Therefore, the buffer registers 4, 5 and 6 contain two eight-bit registers, and the multiplier 9 contains two eight-bit multipliers.

In relation to the K1902BM2 processor, the set of elements indicated in the implementation examples requires ≃ 6 μs for each operator 1, 3, 4, and 8, and ≃ 15 μs for each operator 2, 5, and 7. Coding of one block (225 • 16) dv. characters with a PC code will require a number of commands equal to N _k = (4 • 15 + 4) 225 + 1 = 401 teams, and will take T _externally in time _. ≃ 0.16 s. On average, 2.5 commands are required to encode one bit of information.

 A further increase in the performance of the proposed device can be achieved by using a decoding procedure with erasure in place of check symbols when encoding. Since the proposed device is more adapted to the decoding procedure, the speed increases to 1.37 instructions per bit.

 In addition, the use of high-speed processors, for example, Intel 80386 also improves the performance of the device.

A purely software implementation of the operation of multiplying two numbers in the field GF (2 ^m ) will require 18 commands [10].

 The gain of the proposed device in the number of commands for the operation of multiplication is approximately 4.5 times. The gain of the device in the entire encoding operation with the PC code will be approximately the same, since the multiplication operation is the most frequent.

 After completing the encoding of information with an external code, the microprocessor encodes each 16-bit word with an internal (24, 16) code, adding 8 test characters to 16 information symbols. Coding is carried out in a tabular manner.

However, the direct tabular coding used in the prototype, when 16 information characters are the address of the cell in which 8 test characters are stored, requires a large amount of memory. Therefore, the proposed device uses tabular coding in parts with the length of each part l = 8 [11], which allows to reduce the amount of memory from 2 ¹⁶ to 2 ⁸ cells.

 In FIG. 9 shows a block diagram of an algorithm for encoding information with an internal code (example). Algorithm operators have the following purpose.

Operator 1 sets the source data, which include
the starting address of the array M 1 characters of the PC code (information combinations of the internal code),
the starting address of the array M 2 residues,
the starting address of the array M 3 verification characters of the internal code,
the initial value of the step counter characters in the code block of the PC code, for example N = 241.

 Each access to the arrays of characters of the PC code and verification characters of the internal code uses an auto-incremental addressing method.

 Operator 2 generates the cell address of array M 2, where the remainder of dividing the first byte of the current block of the internal code (at the beginning of the algorithm of the first) by the generating polynomial g (x) is stored.

 Operator 3 at the address generated in operator 2 extracts the remainder and sends it to the microprocessor RON.

 Operator 4 extracts the second byte of the current block from the array M 1.

 Operator 5 adds the second byte of the current word with the contents of RON.

 Operator 6 allocates the least significant byte as a result of addition (the operation of resetting the most significant byte, characteristic of the instruction system of machines of the type "Electronics-60").

 Operator 7, at an address equal to the contents of the least significant byte of this result, reads a check character from an array of M 2 residues and writes it to an array of check characters M 3.

 Operator 8 decreases the value of the counter of the number of characters by one.

 Operator 9 checks the condition of equality of 0 counter readings. If the condition of equality 0 is not fulfilled, the transition to operator 2 is carried out, when executed, the end of the algorithm.

 The loading of the microprocessor by the internal encoding program according to the algorithm described above amounted to about 1690 instructions, or 0.29 instructions per bit of information.

The resulting load of the microprocessor for encoding with internal and external codes will be approximately T _res = T _ext. + T _int = 1.37 + 0.29 = 1.66 k / bit.

 Information decoding mode.

 In the mode of inputting information from the communication channel, as mentioned earlier in the description of the operation of the I / O unit 1, information is recorded in the RAM of the memory unit 3. The microprocessor and RAM used in the device are 16-bit. In FIG. 10 schematically shows the distribution of RAM cells for recording information received from a communication channel.

 In FIG. 11 is a flowchart of a decoding algorithm of information encoded by an internal code. The algorithm uses a tabular method of decoding in parts [11]. The purpose of the algorithm operators is as follows.

Operator 1 sets the source data, which include
the number of blocks of the internal code in the PC code block, for example, equal to 241,
the starting address of the RAM zone in which information received from the communication channel is stored,
the starting address of the RAM zone in which the signs of the internal code blocks are stored, for example, “0” is the code block with no error or with an undetected error, “1” is the code block with the detected error.

 Operator 2 determines the intermediate result of dividing a byte containing the highest coefficients of the decoded code block. It happens as follows.

 The byte with the highest coefficients is counted at the current (starting at the beginning of coding) cell address of the RAM information zone and written to the microprocessor RON, since this multiplies the byte, the operation of "zeroing" (entering a constant) of the high byte of this RON is necessary. This operation of entering constants is repeated each time information is read from RAM. In this case, the high byte of RON is used to indicate a specific zone in RAM, and the low byte is used to indicate the byte address in this zone.

 At the address of the contents in the low byte of the RON, taking into account the constant in the high byte of the RON, the remainder zone is accessed and the intermediate residue is read from it by dividing the highest coefficients of the decoded block by the generating polynomial g (x) and written to the same RON. Then the contents of the RON are added modulo two with the next byte of the decoded block and recorded in the same RON.

 Operator 3 determines the syndrome of the decoded block, for which, at the address of the RON content, an access to the corresponding cell of the residual zone and reading the result of dividing the contents of the RON by the generating polynomial g (x), which is written in the same RON, are read. After that, the contents of the RON are added modulo two with the check byte of the decoded block, the result of the addition, which is the syndrome, is recorded in the same RON.

 Operator 4 performs an analysis of the syndrome. If the syndrome is equal to zero, then operator 5 records the sign “0” in the cell of the zone of signs corresponding to the block being decoded; if the syndrome is different from zero, then operator 6 records the sign “1” in this cell.

 Operators 7 and 8 check for completion of the decoding procedure. For this, operator 7 reduces by one the contents of the memory cell (RON), where the current number of the decoded block is stored, and operator 8 compares the value of this number with zero. If N = 0, then the decoding procedure ends, if N ≠ 0, then the transition to operator 2 occurs and the decoding procedure continues.

 As a result of decoding, an information array with the number of 16-bit code blocks equal to N will be recorded in one part of the RAM, and an array of signs (deletions) of the same volume will be recorded in the other part of the RAM.

 The algorithm is somewhat more complicated when using the code in the mode of fixing single errors. A detailed study of this algorithm showed that the cost of computer time is 0.86 instructions per bit for the most difficult decoding option (241 characters have 16 erasures and 225 single error corrections).

 The decoding algorithm of the external PC code, which is a special case of the BCH code, is essentially described in [7, p. 167 - 175]. The initial data for decoding the external code are the decoded code combinations obtained by decoding the internal code, numbers (locators) of the erased code combinations of the internal code.

 A generalized decoding algorithm for an external BCH (RS) code is shown in FIG. 12.

[6, с. 188] , где D - кодовое расстояние кода; m₀ - целое положительное число, не превышающее -2.In the first operation of the algorithm, the syndrome polynomial S (x) is calculated. The syndrome polynomial has the form
S (x) = S ₀ x ^R-1 + S ₁ x ^R-2 + ... + S _R-1 ; R = n - K. (6)
Coefficients of a polynomial are defined as the values of the code polynomial C (x) of length N when substituting values in it

[6, p. 188], where D is the code distance of the code; m ₀ is a positive integer not exceeding -2.

For example, for m ₀ = 0 and a PC code with a generating polynomial (3) (D = 17), it is necessary to substitute the values α ^o , α; α ² , α ³ ... α ¹⁵ into the code polynomial.

 It is convenient to calculate the coefficients of the syndromic polynomial in the form of a recurrence relation by the formula (4).

In the absence of distortion, the coefficients S _m are equal to zero, in the presence of distortion, they are nonzero and, together with the locators (numbers) of the erased characters determined when decoding the internal code, are used further to decode the PC code.

 In FIG. 13 shows a block diagram of an algorithm for calculating the coefficients of a syndromic polynomial according to Horner's scheme, using both the software and hardware of the encoding-decoding device (Fig. 1).

In FIG. 14 shows timing diagrams of control signals generated by the microprocessor in calculating the coefficients S _m .

 Algorithm operators have the following purpose.

Operator 1 sets the source data, which include
the initial value of the address B ₀ + 1 of the array of field elements in the ROM, where B ₀ is a constant,
the initial value of the coefficient counter of the syndrome polynomial R__ → <A> (the value R is entered in the cell at address A, as an example, R = 16),
the initial value of the address A ₀ + 1 of the array of coefficients S _{m of the} syndrome polynomial, where A ₀ is a constant.

 Operator 2 sets the initial value C + 1 of the information array in RAM, where C is a constant. The initial value of the addresses of the arrays is recorded in RONs, and an auto-incrementing addressing method is used.

(в начале алгоритма α^o из ячейки с адресом B₀ + 1).The operator 3 on the signal Q4 (Fig. 14 g) writes from the ROM of the memory unit 3 via bus 2 to the first buffer register 4 (Fig. 1) of the next field element

(at the beginning of the algorithm α ^o from the cell with the address B ₀ + 1).

Operator 4, on signal Q5 (Fig. 14 b), writes from RAM of memory block 3 via bus 2 through switch 10 to the second buffer register 5 of the next character C _j (at the beginning of algorithm C ₁ from the cell with address C + 1). At the same time, at the output of the multiplier 9, the result of the multiplication C _i α ^{m is} obtained, which is supplied to the first inputs of the block of adders 11 modulo two.

по сигналу Q6 (фиг. 14 г) осуществляют запись из ОЗУ блока памяти 3 по шине 2 через коммутатор 10 в третий буферный регистр 6 символов C₂ - C_N, при этом с вводом каждого символа на выходе блока сумматора по модулю два 11 образуется сумма предыдущего результата с вводимым символом, которая через коммутатора 10 (при снятии сигнала Q6 коммутатор устанавливается в противоположное состояние) поступает на информационные входы второго буферного регистра 5, где фиксируется сигналом Q6, задержанным в первом узла 7 задержки (фиг. 14 д), величина задержки определяется управляющим сигналом Q7 (тактируемая задержка).Operators

the signal Q6 (Fig. 14 g) is used to write from the RAM of the memory unit 3 via bus 2 through the switch 10 to the third buffer register 6 characters C ₂ - C _N , and with the input of each character at the output of the adder block modulo two 11 the sum is formed of the previous result with an input symbol, which, through the switch 10 (when the Q6 signal is removed, the switch is set to the opposite state), enters the information inputs of the second buffer register 5, where it is fixed by the Q6 signal delayed in the first delay node 7 (Fig. 14 d), the delay value determine Xia control signal Q7 (clocked delay).

On the multiplier 9, this sum is multiplied by the value α ^m and the multiplication result is sent to the block 11 adders modulo two, and from its output through the switch 10 to the second buffer register, where it is fixed by the next signal Q6.

The operator N + 4 after entering the last character C _N generates a signal Q2 to the second block of keys, and the value of the coefficient S _{m is} written to RAM at the corresponding address in the array of coefficients of the syndrome polynomial.

The operators N + 5 and N + 6, before calculating the next coefficient of the syndromic polynomial, check for the end of the algorithm, i.e. whether the next coefficient S _{m is the} last. To do this, the N + 5 operator reduces the contents of cell A by one and writes the result to the same cell, and the N + 6 operator compares the result with zero. A positive comparison result means that all R coefficients of the polynomial are calculated and written to the corresponding RAM array. If the comparison result is negative, the transition to operator 2 and the repetition of the algorithm with the next α ^{m are} performed.
The load of the microprocessor by the program for calculating the coefficients of the syndromic polynomial according to the algorithm described above is about 4000 instructions.

As a result of the implementation of the described algorithm, an array of M ₀ syndromic polynomial coefficients recorded at the addresses (A ₀ + 1) - (A ₀ + R) will be formed.

 In the second operation of the generalized external code decoding algorithm (Fig. 12), the polynomial of erasure locators λ (x) is calculated.

где
Y_j - локаторы (номера) стираний, полученные при декодировании внутреннего кода;
λ_i - значения коэффициентов;
s - число стираний (см. [7], с. 169 формула Б 6, в которой
σ_de=λ_i,aZ^s-e=X^s-i) ).The polynomial of erasure locators has the form

Where
Y _j - erasure locators (numbers) obtained by decoding the internal code;
λ _i are the values of the coefficients;
s is the number of erasures (see [7], p. 169 formula B 6, in which
σ _de = λ _i , aZ ^se = X ^si )).

Equating the coefficients for unknowns with equal degrees in the left and right sides of equation (7), we can find the values of the coefficients λ _i .

.With a software implementation, it is more convenient to determine the values of the coefficients in the form
λ $\genfrac{}{}{0ex}{}{\text{(j)}}{\text{i}}$ = λ $\genfrac{}{}{0ex}{}{\text{(j-1)}}{\text{i}}$ + Y _j λ $\genfrac{}{}{0ex}{}{\text{(j-1)}}{\text{i-1}}$ (eight)
(see similarly to [7], p. 173, formula B 22),
Where
λ $\genfrac{}{}{0ex}{}{\text{(j-1)}}{\text{i}}$ - i-th coefficient after processing the (j - 1) -th erasure locator,

.

 It is advisable to determine the values of the coefficients in s stages using a recursive procedure using the results of determining the values of the coefficients obtained in the previous step.

На третьем этапе определяются коэффициенты

На s-м этапе определяются коэффициенты

В качестве примера на фиг. 15 приведена блок-схема алгоритма определения коэффициентов многочлена локаторов стираний λ(x) , на фиг. 16 - состояние РОНов, первого и второго буферных регистров в зависимости от номера этапа и номера оператора.At the first stage (j = 1), the coefficient
λ ₁ = λ $\genfrac{}{}{0ex}{}{\text{1}}{\text{1}}$ = Y _1. (9)
In the second stage, the coefficients are determined

In the third stage, the coefficients are determined

At the s-th stage, the coefficients are determined

As an example in FIG. 15 shows a block diagram of an algorithm for determining the coefficients of the polynomial of erasure locators λ (x), in FIG. 16 - state of RONs, first and second buffer registers depending on the stage number and operator number.

 The operators of the algorithm have the following meaning.

Operator 1 sets the source data, which include
the starting address A ₁ + 1 of the array M 1 of erasure locators recorded in RON 0, where A ₁ is a constant,
the starting address A ₂ + 1 of the array M 2 of coefficients of the erasure locator polynomial written in RON 2 and RON 4, where A ₂ is a constant,
the initial value of the stage number j = 1, recorded in the counter of the number of stages,
the address of the cell L in which the last erasure locator is recorded, for example, A ₁ + 3, if the number of erasures is s = 3.

Operator 2 writes from the array M 1 to the array M 2 of the first erasure locator Y ₁ , thereby forming a coefficient λ ₁ in accordance with expression (9). To do this, the contents of the cell whose address is specified in RON 0 is recorded in the cell whose address is specified in RON 4. In this case, after each access to the arrays M 1 and M 2, the addresses stored in RON 0 and RON 4 are increased by one.

Operator 3 checks the condition whether the next locator Y _{j is the} last, for which it compares the address of this locator stored in PON 0 with the address of the cell L in which the last erase locator is written. If the comparison result is positive, the algorithm ends; if the comparison is negative, the transition to operator 4 is performed.

 The operator 4 records the number of the completed step j recorded in the step counter in RON 5.

 Operator 5 proceeds to the next step, increasing the contents of the counter of the number of steps by one: j = j + 1.

The operator 6 reads from the array M 1 into PON 1 and into the first buffer register 4 (Fig. 1) of the current erasure locator Y _j (after the first stage Y _j = Y ₂ , after the second Y _j = Y _3, and so on).

Operator 7 reads from the array M 2 in RON 3 the contents of the cell whose address is recorded in RON 2, followed by an increase in the address by one (after the first stage, the coefficient λ ₁ = λ is calculated at this address $\genfrac{}{}{0ex}{}{\text{(1)}}{\text{1}}$ )

Operator 8 determines the coefficient λ $\genfrac{}{}{0ex}{}{\text{(j)}}{\text{1}}$ by summing the contents of RON 3 and RON 1, followed by recording the result in RON 1 (after the first stage in accordance with expression (10), after the second, with expression (12) and so on).

 Operator 9 reads the previous result from RON 1 to array M 2 at the address that is recorded in RON 4, with a subsequent increase of this address by one.

 The operator 10 reads the contents of RON 3 into the second buffer register 5 (Fig. 1), while the next polynomial coefficient λ (x) is calculated.

 The operator 11 records the result of the multiplication in RON 1.

 Operators 12 and 13 carry out a check at the end of the stage by subtracting one from the contents of RON 5 and comparing the result of the subtraction with zero. If the comparison result is positive, the transition to the operator 14. If the comparison is negative, the transition to the operator 7 and determination of the next stage coefficient.

 Operator 14 reads the contents of RON 1 and writes it to the array M 2 at the address that is recorded in RON 4, with a subsequent increase of this address by one, and goes to operator 3.

и промежуточных коэффициентов

полученных в соответствии с выражениями (9 - 15) и записанных по адресам (A₂ + 1) - (A₂ + 136) (при числе стираний меньшем, 16 часть массива остается свободной).As a result of the implementation of the described algorithm, an array of M 2 coefficients of the erasure locator polynomial coefficients will be formed

and intermediate coefficients

received in accordance with expressions (9 - 15) and recorded at the addresses (A ₂ + 1) - (A ₂ + 136) (with the number of erasures less, 16 part of the array remains free).

 In FIG. 17 shows the structure of the array M 2 for this case.

 In the third operation of the generalized algorithm, a modified syndromic polynomial is calculated, which serves to determine the algorithms (numbers) of erroneous symbols of the PC code. To find it in the syndrome polynomial S (x), it is necessary to eliminate the components characterizing the erasure, which is achieved by multiplying the syndrome polynomial S (x) and the erasure locator polynomial λ (x).

где
e_j - значение ошибки;
d_k - значение стертого символа;
x_j - локатор ошибки;
Y_k - локатор стирания (см. [7], с. 169, формула Б 5),
а также с учетом того, что

получим
T(x) = T₀x^R-1-S + T₁x^R-2-S + ... + T_R-2-Sx + T_R-1-S, (18)
где

где
величины

определены первой и второй операциями обобщенного алгоритма.By multiplying these polynomials with the subsequent substitution of values

Where
e _j is the error value;
d _k is the value of the erased character;
x _j is the error locator;
Y _k - erasure locator (see [7], p. 169, formula B 5),
as well as the fact that

we get
T (x) = T ₀ x ^R-1-S + T ₁ x ^R-2-S + ... + T _R-2-S x + T _R-1-S , (18)
Where

Where
values

defined by the first and second operations of the generalized algorithm.

 As an example in FIG. 18 is a flowchart of an algorithm for determining the coefficient of a modified syndromic polynomial T (x).

 Algorithm operators have the following purpose.

, где ]•[ означает целую часть.Operator 1 sets the source data, which include
conditional starting address (A ₀ + 0) of the array M 0 of the coefficients of the syndrome polynomial preceding the address A ₀ + 1 of the cell in which the coefficient S ₀ is stored, the address is written in RON 0,
the starting address of the array M 3 (A ₃ + 1) of the coefficients of the modified syndromic polynomial recorded in RON 2,
the initial value of the counter of the number of coefficients of the modified syndrome polynomial N _mod = K = 2t, where t is the speed of errors sent by the PC code,

, where] • [means the integer part.

 As an example, consider the case when the number of erasures is S = 3 and, therefore, K = 12.

Оператор 2 записывает в счетчик числа стираний число стираний, в нашем примере N_ст = 3.The system of equations for finding the coefficients T ₀ , T ₁ ..., T ₁₁ has the form

Operator 2 writes to the erasure counter the number of erasures, in our example N _article = 3.

Operator 3 writes to RON 4 the address A ₂ + 1 of the cell of array M 2, in which the first coefficient λ _{1 of} the erasure locator polynomial is stored.

Operator 4 sets the variable L _{1 to a} value of 0.

 Operator 5 increases the contents of RON 0 by S + 1.

Operator 6 reads from the array M 0 the contents of the cell with the address <РОН О>, that is, in our example, with the address <A ₀ +4>, at which the coefficient S _S = S ₃ is stored, and writes it to the third buffer register (Fig. 1) by signal Q6.

Operator 7 reads from the array M 0 the contents of the cell with the address <RON O-1>, at which the coefficient S _N-1 is stored (in our example, λ ₁ ), and writes it to the first buffer register 4 according to signal Q4.

Operator 8 increases the contents of RON 4 by L ₁ .

(в нашем примере λ₁ ), и записывает его во второй буферный регистр 5 по сигналу Q5. При этом адрес, записанный в РОН 4, увеличивается на единицу. На выходе умножителя 9 сформируется результат S₂•λ₁ , который поступит на первые входы сумматора 11 по модулю два, на вторые входы которого поступает сигнал с выхода третьего буферного регистра 6, в котором был записан коэффициент S₃.The operator 9 reads from the array M 2 the contents of the cell with the address RON 4, which stores the coefficient

(in our example, λ ₁ ), and writes it to the second buffer register 5 by the signal Q5. In this case, the address recorded in RON 4 increases by one. At the output of the multiplier 9, a result S ₂ • λ _{1 is} generated, which will be supplied to the first inputs of the adder 11 modulo two, to the second inputs of which a signal is output from the output of the third buffer register 6, in which the coefficient S ₃ was recorded.

The signal Q5, delayed in the second delay element 8, the output signal of the adder 11 equal to (S ₂ λ ₁ + S ₃ ), coming through the switch 10 to the inputs of the third buffer register 6, is recorded in this register.

The operator 10 increases the value of the variable L ₁ by one.

 Operator 11 decreases the value recorded in the erase counter by one.

 The operator 12 checks the condition that the value of the counter of the number of erasures be equal to zero. If the comparison result is negative, the transition to operator 7 occurs; if the comparison is positive, the transition to operator 13. In our example, N - 1 = 2, therefore, operators 7 - 12 are repeated twice.

At the first repetition, operator 7 calculates the coefficient S ₁ , and at the second repetition, S ₀ .

Operator 8 at the first repetition will count the contents of the cell at the address PON 4 = A ₂ + 3, that is, the coefficient λ ₂ , and at the second it will at the address PON 4 = A ₂ + 6, that is, the coefficient λ ₁ .

As a result of the first repetition in the third buffer register 6, the sum S ₁ λ ₂ + S ₂ λ ₁ + S _{3 is formed} , and as a result of the second, the coefficient T _{0 is formed} , while the condition N = 0 will be satisfied and the transition to operator 13 will be carried out.

The operator 13, on signal Q3, through the third key block 14, writes the first coefficient T ₀ to the array M 3, the coefficients of the modified syndrome at the address of the contents of RON 2 = A ₃ + 1, that is, in the first cell of the array M 3, while the address in RON 2 will increase per unit and becomes equal to RON 2 = A ₃ + 2.

 The operator 14 decreases the value of K by one (in our example, K will become equal to 11).

Operator 15 checks that the value K is zero. If K = 0, then the algorithm is completed and 12 coefficients of the polynomial T (x) are sequentially written in the array M 3, starting from T ₀ and ending with T ₁₁ . If K is not equal to 0, then the transition to operator 2 is carried out and the next coefficient is calculated. As a result of the implementation of the described algorithm, in the array M 3 R = S coefficients of the modified syndromic polynomial T (x) are written at the addresses (A ₃ + 1) - (A ₃ + R - S).

Коэффициенты этого многочлена определяются с использованием произведения T(x)•σ(x) аналогично тому, как это было сделано при вычислении коэффициентов модифицированного синдромного многочлена.The fourth procedure defines a polynomial of error locators, which has the form

The coefficients of this polynomial are determined using the product T (x) • σ (x) in the same way as when calculating the coefficients of the modified syndromic polynomial.

,
(аналогично [7], с. 171, формула Б 14).The system of equations for determining the coefficients σ _t has the form

,
(similar to [7], p. 171, formula B 14).

 This system of equations can be solved, for example, by the Gauss method [13] by reducing the matrix of coefficients to a triangular shape.

 Usually, based on the results of modeling noise immunity of cascade codes, the number of correctable errors is limited. This greatly simplifies the procedure for solving the reduced control system and finding error locators in the future.

 In FIG. 19, an example is given of an algorithm for determining the coefficients of the polynomial σ (x) for the case of correction of two errors, i.e., t = 2.

.The matrix of coefficients will have the form

.

 In view of the fact that the purpose of most operators is obvious from their outline, we give only the definition of some coefficients.

В операторе A4

В операторе A6

В операторе A8

В операторе A9 определяются σ₁ и σ₂ .In statement A2

In operator A4

In statement A6

In statement A8

The operator A9 defines σ ₁ and σ ₂ .

 In B2, row permutation is performed.

В операторе B6

Анализ выражений (24 - 30( показывает, что в них участвуют только три операции: деления, сложения по модулю два и умножения.In statement B33

In statement B6

Analysis of expressions (24 - 30 (shows that only three operations are involved in them: division, addition modulo two, and multiplication.

 In the proposed device, the division operation is replaced by the operation of multiplication by the inverse element. For this, a table of inverse field elements is written in the ROM of the memory block. In order to count the element inverse to the divisor, you must set the address equal to the divisor itself.

 Thus, all operations to find the coefficients of equation (21) are reduced to the operation of multiplication and addition modulo two. Due to the fact that the implementation of these operations using the proposed device of FIG. 1 is described in previous procedures, a detailed description of the coefficient determination algorithm is not carried out.

In the fifth procedure, error locators x _{j are found} by solving equation (21). In the general case, this equation can be solved by sequentially substituting all the code locators into this equation and choosing as a solution those locators for which the equation vanishes (Chen's procedure, see [7], p. 176).

которое решается табличным путем: путем считывания из ПЗУ по адресу, соответствующему свободному члену уравнения корней Z₁ и Z₂, причем Z₃=Z₁+Z₂, и последующего определения локаторов ошибок из выражения

.For t≤4, you can use the solution algorithm described in [12, p. 58 - 65]. For example, for t = 3, equation (21) is reduced to

which is solved in a tabular way: by reading from the ROM at the address corresponding to the free term of the root equation Z ₁ and Z ₂ , with Z ₃ = Z ₁ + Z ₂ , and then determining the error locators from the expression

.

The proposed device implements the operation of raising to a power: finding the value of σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ in (31) by multiplying the element by itself, the division operation in (30) by multiplying by the inverse element, as in the previous procedure. The operation of extracting the square root in the proposed device is implemented in a tabular manner, for which purpose a table of square roots of the elements of the field GF (2 ⁸ ) is written in the ROM of the memory unit. Value (σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ + σ ₂ ) ^0.5 in (31) is found by reading from this table at (σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ + σ ₂ ).

 The remaining operations in (31) and (30) are modulo two addition operations. Due to the fame of performing operations from the description of the operation of the device, a detailed description of the calculation algorithm by expression (31) is not given.

 After determining the locators (position numbers) of errors, erasing errors are combined into one concept: distortion.

Алгоритм определения коэффициентов многочлена искажений совпадает с алгоритмом определения коэффициентов многочлена стираний и является его продолжением.In the sixth procedure, the polynomial of distortion locators is calculated, which has the form

The algorithm for determining the coefficients of the distortion polynomial coincides with the algorithm for determining the coefficients of the erasure polynomial and is a continuation of it.

Let, for example, S = 3 and t = 2. Then, in the array M 2 (Fig. 17), six coefficients will be written, three of which are the coefficients λ ₁ , λ ₂ , λ _{3 of} equation (7) and three λ $\genfrac{}{}{0ex}{}{\text{(2)}}{\text{1}}$ , λ $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{1}}$ , λ $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{2}}$ - intermediate coefficients.

Выражения для промежуточных коэффициентов будут иметь вид

В результате выполнения алгоритма эти коэффициенты будут записаны в массив M 2 по адресам (A₂+7) - (A₂+15).The expressions for finding the following coefficients λ ₄ and λ _{5 of} equation (32) will have the form

The expressions for the intermediate coefficients will have the form

As a result of the algorithm, these coefficients will be written to the array M 2 at the addresses (A ₂ +7) - (A ₂ +15).

 The seventh procedure is the final in a generalized decoding algorithm for external PC code. In this procedure, using the coefficients of the syndrome polynomials and distortion locators, distortion vectors are determined and the symbols of the code combination are corrected.

где
λ_s+t-1- λ₁ - коэффициенты многочлена искажений λ(x) (формула 7), определенные в шестой процедуре;
S_o - S_s+t-1 - первые (S+t) коэффициенты синдромного многочлена S(x) (формула 6), определенные в первой процедуре обобщенного алгоритма;
λ′(x_s+t) - значение производной многочлена λ(x), полученное при подстановке в λ′(x) значения x = x_s+t.To determine the (S + t) -th distortion, we use the formula corresponding to Forney's algorithm (see [6], p. 219, Fig. 77, the formula for determining Y _l , it should be noted that the use of inverse elements X $\genfrac{}{}{0ex}{}{\text{-1}}{\text{l}}$ equivalent to the use of direct elements), which in the notation adopted in the application materials has the form

Where
λ _{s + t-1} - λ ₁ - coefficients of the distortion polynomial λ (x) (formula 7) defined in the sixth procedure;
S _o - S _{s + t-1} - the first (S + t) coefficients of the syndrome polynomial S (x) (formula 6) defined in the first procedure of the generalized algorithm;
λ ′ (x _{s + t} ) is the value of the derivative of the polynomial λ (x) obtained by substituting the value x = x _{s + t} in λ ′ (x).

The derivative of the polynomial λ (x) is calculated by the formulas
for even s
λ ′ (x) = [(λ ₁ • x ² + λ ₃ ) x ² + λ ₄ ] x ² + ... + λ _{s + t-1} ; (36)
for odd s
λ ′ (x) = [(x ² + λ ₂ ) x ² + λ ₄ ] x ² + ... + λ _{s + t-1} . (37)
It is advisable to calculate the derivative at the stage of calculating the coefficients of the polynomial of erasure locators.

 Due to the fact that the calculation of λ ′ (x) follows the Horner formula [4], a detailed description of the algorithm is not given.

получим значение последнего искажения E_S+t , соответствующего локатору x_s+t.Substituting into the formula (35) the known values of the coefficients

we get the value of the last distortion E _{S + t} corresponding to the locator x _{s + t} .

 Correction of a distorted symbol is carried out by summing it with the error vector.

.The code polynomial corrected in this way corresponds to a new syndromic polynomial, the coefficient of which is determined as follows:

.

Занчения векторов ошибок записываются в один из РОНов микропроцессора. Затем по адресу искаженного символа, определяемому его локатором, осуществляются исправление искаженного символа путем суммирования его с вектором ошибки и запись результата сложения на место искаженного символа.For i = 1, the syndromic polynomial corresponding to the corrected last distortion is determined, after which the penultimate distortion vector is found from expression (35). Repeating the steps of computing the vectors E _{s + t- (i-1)} and their corresponding syndromic polynomials, in the last steps we obtain

The completion of the error vectors is recorded in one of the RONs of the microprocessor. Then, at the address of the distorted symbol determined by its locator, the distorted symbol is corrected by summing it with the error vector and writing the result of addition to the place of the distorted symbol.

 The number of instructions required to decode a cascade code block is a variable and depends on the number of errors and erasures in the block. For the most difficult case, when 16 erasures are corrected, 1.37 instructions per bit are required to decode the external (241, 225) code, and 0.86 instructions per bit are required to decode the internal (24, 16) code. Complete decoding of the cascade code block is carried out for ≃ 13000 instructions, which is 2.23 instructions per bit.

 Thus, the proposed technical solution allows the operation of encoding and decoding information as conventional binary and non-binary codes. Particularly effective is the use of cascade coding, which, with the same information transmission speed, allows to obtain a gain in noise immunity equal to 2 dB (cascade code: PC and short block code), compared to a binary block code (hard decision) [14, p. 320, table 8.1], and even greater gains when using M-ary modulation [14, p. 322, table 8.2].

 It is also significant that in the proposed technical solution, some parameters of the codes used can be quickly changed by replacing the original data in encoding and decoding programs, which significantly expands the functionality of the device.

 The optimal combination of hardware and software in the device made it possible to ensure a high information processing speed, which is about 1.66 in the encoding mode and 2.23 commands per bit in decoding mode (in the amount of 3.89 commands per bit), which indicates a significant gain of the proposed encoding and decoding procedures compared with the results achieved in [15], where the encoding-decoding speed of the PC code alone is 800 commands / bit.

 The use of higher-speed processors, such as Intel 80386, will reduce the encoding and decoding time by at least 50 times.

 Sources of information.

 1. Auth. St. N 1275782, cl. H 03 M 13/02, 1986.

 2. Auth. St. N 1309317, cl. H 03 M 13/02, 1987.

 3. Auth. St. N 1481902, class H 03 M 13/00, 1988.

 4. Auth. St. N 1635193, CL H 06 M 15/31.

 5. Auth. St. N 1418913, class H 03 M 13/00, 1988 (prototype).

 6. Bleikhut R. Theory and practice of error control codes. M .: Mir, 1986.

 7. Forney D. Cascading codes. M .: Mir, 1970.

 8. Horsetail S.T., Varlinsky N.N., Popov E.A. Microprocessors and microcomputers in automatic control systems. Directory. L .: Engineering, 1987.

 9. Digital and analog integrated circuits. Directory. M .: Radio and communications, 1990.

 10. Istomin G.S., Parisian I.S. On the use of microcomputers for the implementation of arithmetic operations in Galois fields. Communication Technology, TPS Series, vol. 2, 1978.

 11. V.O. Shvartsman, G.A. Emelyanov. Theory of discrete information transmission. M .: Communication, 1979, p. 318.

 12. E. M. Gabidulin, V. B. Afanasyev. Coding in electronics. M: Radio and communications, 1986.

 13. Sigorsky V.P. Mathematical apparatus of an engineer. Kiev: Technique, 1977, p. 230.

 14. J. Clark, Jr., J. Keym. Error correction coding in digital communication systems. M .: Radio and communications, 1986.

 15. Microprocessor encoders and decoders. M .: Radio and communication, 1991, p. 86.

Claims (1)

 An information encoding-decoding device comprising an input-output unit and a memory unit connected to a common bus, as well as an adder unit modulo two, while the serial information input-output and parallel information inputs-outputs of the input-output unit are the corresponding information inputs - device outputs, characterized in that three buffer registers, a multiplier, two delay nodes, a switch, three key blocks and three OR elements are introduced into it, while the information inputs of the first buffer register , the outputs of the first, second and third block of keys and the first inputs of the switch are connected to a common bus, the outputs of the first buffer register through a multiplier are connected to the inputs of the first block of keys and to the first inputs of the block of adders modulo two, the outputs of the switch through the second buffer register are connected to the second inputs multiplier and with the inputs of the second block of keys, and through the third buffer register with the inputs of the third block of keys and the second inputs of the block of adders modulo two, the outputs of which are connected to the second inputs of the switch, the first the second, third and third control outputs of the input-output block are connected respectively to the control inputs of the first, second and third key blocks, the fourth to the recording input of the first buffer register, the fifth to the first input OR to the recording input of the second buffer register, through the third OR element - to the control input of the switch, and through the second delay node and the second OR element connected in series - to the recording input of the third buffer register, the sixth - to the second inputs of the second and third OR elements and through the first node ki - to the second input of the first OR element, and the seventh output of the input-output block is connected to the second inputs of the first and second delay nodes, while the control inputs and outputs, clock and start inputs of the input-output block are respectively control inputs and outputs, clock and trigger inputs of the device.

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