RU2037271C1 - Error-correcting device - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has five registers, buffer register, buffer exchange unit, three buffer units, syndrome generator, two flag registers, erase counter, two locator storage units, locator generator, locator multiplexer, flag controller, locator address controller, buffer flag unit, buffer locator unit, zero-signal detector, analysis register, five multiplexers, main storage unit, adder, arithmetic and logical unit, two comparators, constants storage unit, coder, instruction converter, synchronizing unit, instruction storage unit, instruction register, operating bus, data bus, flag-signal bus, control input, correction address output, control output, check output, synchronization bus, control bus. Device functions to encode or decode accepted words arriving over data bus and in decoding them it can correct as many as two errors within one word or to erase erroneous latters. Device can process contiguous data flow. EFFECT: improved informative capacity and simplified design. 7 dwg, 1 tbl

Description

 The invention relates to computer technology and can be used in noise-encoding and decoding systems, in particular in optical disk storage devices.

A known error-correcting system [1] It contains a syndrome generator, a random access memory block, a locator generator and a computing device including an arithmetic-logical unit, an adder modulo two, exchange registers, multiplexers, ROM of logarithms and antilogarithms, a control circuit. The system calculates and corrects up to two errors in the codeword. Its main distinguishing feature is the locator generator, which performs the function of computing error locators and the reciprocal of the sum of these locators by sequentially substituting their values in the following equations:
f (x) x ² + λ ₁ x + λ ₂ 0 and
S _m α ^φ (α ⁱ + α ^j ) α ^32m , where λ ₁ α ⁱ + α ^j ;
λ ₂ α ⁱ ˙ α ^j ;
S _m modified error syndrome.

 However, the system has the following disadvantages: it does not allow you to correct erasures, i.e., it is unsuitable for the encoding procedure, the complexity of the locator generator and the computing device, and a large number of steps when finding the inverse element.

Known Reed-Solomon decoder circuit [2] It contains a generator of syndromes, a generator of erasure locators, ROM of logarithms, antilogarithms and roots of a quadratic equation, ROM of commands, a RAM block, a control circuit and a computing device including an arithmetic logic unit, exchange registers and multiplexers . The scheme calculates and corrects any combinations of errors and erasures that satisfy the following inequality:
2 ν + 1 ≅ dl, where d is the Hamming code distance;
ν number of errors in the codeword;
l the number of erasures in the codeword.

 However, the following drawbacks are inherent in the circuit: the computing device contains ROM with high redundancy, the operations of addition and multiplication-division are not aligned, which leads to the use of ROM commands with a capacity of more than 1 kbyte, the correction process during decoding is performed in a large number of steps, the decoder requires a complex control circuit.

 A known system for correcting errors [3] is the closest technical solution to the invention according to the principle of action and the achieved result. It is intended for use in jamming digital systems using Reed-Solomon codes. The system contains a syndrome generator, a RAM block, a zero signal detector, ROM of logarithms and antilogarithms of locators, a flag controller, control circuits, a command address generator with a control circuit, ROM of commands, a correction exchange register, a locator generator, an erase counter, and a computing device that includes arithmetic -logic block, operational registers, ROM of logarithms and antilogarithms (or ROM of the inverse element, if a fast multiplier is used as an arithmetic-logical block) and adder by module two.

 The system computes errors and erasure locators, error values and character correction using the calculated error syndromes and the flags accompanying the code words. Moreover, the correcting ability of the system is limited by the expression 2 ν + l ≅ d l. All the above operations in this system are performed in no more than 100 steps and require for this the volume of ROM commands in 384 words (each word contains at least 9 bits).

However, the following disadvantages are inherent in the system: a large number of ROM tables needed for conversions to the Galois field (2 ⁸ ), the complexity of the flag controller and the control circuit of the command address generator, and the irrational use of the volume of ROM commands.

 The aim of the invention is to increase the information capacity of the device and its simplification.

 The goal is achieved in that in a device including a syndrome generator, a first buffer block, a first flag register, an erase counter, a first locator memory block, a locator buffer block, a flag buffer block, a command memory block, a command register, random access memory block and a zero signal detector , arithmetic logic unit, first comparator, information bus, operating bus and flag signal bus, synchronization block, first to fifth registers, buffer register, buffer exchange block, second and third buffer blocks, generator locators, locator multiplexer, locator address controller, flag controller, second flag register, command converter, constant memory block, adder, analysis register, encoder, second comparator and first to fifth multiplexers, while the control inputs of the constant memory block, arithmetic-logical block , the RAM block, the first to fifth multiplexers, the third to fifth registers, the analysis register, the third buffer block, the first and second comparators and the encoder are combined and connected to the control bus, The output of the command converter is connected to the control bus, the address output of the command converter is connected to the address input of the RAM block, the output of which is connected to the information inputs of the first and third multiplexers, the output of the arithmetic-logic block is connected to the second information input of the third multiplexer, the second information input of which is connected with the output of the arithmetic-logical unit, the output of which is connected to the address input of the constant memory block, the output of which is connected to the first information the input of the second multiplexer, the second information input of which is combined with the second information input of the first multiplexer and connected to the output of the fifth multiplexer, the output of the second multiplexer is connected to the blocking input of the adder and to the information inputs of the third and fourth registers, the outputs of which are connected respectively to the first and second inputs of arithmetic -logic block and information inputs of the first and second comparators, the outputs of which are connected to the blocking inputs of the adder, the first input of which the second is connected to the output of the third register, and the output is connected to the information input of the RAM block, the first information input of the fourth multiplexer and the input of the zero signal detector, the output of which is connected to the input of the analysis register, the output of which is connected to the second information input of the fourth multiplexer, the output of which is connected to the input of the third buffer block, the output of which is connected to the operating bus, the output of the first buffer block, the first information input of the fifth multiplexer, the output of the buffer about the locator block, the first input of the locator multiplexer, the first input of the flag controller and the first input-output of the buffer exchange unit are connected to the operating bus, the second input-output of the buffer exchange unit is connected to the input of the buffer register and the output of the first register, the input of which is combined with the outputs of the buffer register and the second buffer block, with the input of the second register and connected to the information bus of the device, the output of the second register is connected to the inputs of the second buffer block and the syndrome generator, the output of which is connected to the first buffer block, the control input of which is combined with the control inputs of the syndrome generator, the locator buffer block, the encoder, the flag controller, the command converter and the output of the command register, the input of which is connected to the output of the command memory block, the control input of which is connected to the first control output of the flag controller , the second control output of which is connected to the control input of the locator address controller, the third control output is the control output of the device, the control output the command generator is connected to the control input of the flag controller, the flag input of which is connected to the output of the second flag register, and the flag output is the control output of the device and connected to the input of the flag flag block, the output of which, as well as the inputs of the first and second flag registers are connected to the flag signal bus devices, the output of the first flag register is connected to the control inputs of the first locator memory block and the erase counter, the output of which is connected to the second information input of the flag controller and the address the first input of the locator memory block, the information input of which is connected to the output of the locator generator, and the output is connected to the second input of the locator multiplexer, the output of which is connected to the information input of the second locator memory, the address and control inputs of which are connected to the corresponding outputs of the locator address controller, and the information output is connected to the information input of the locator buffer block and is the output of the device correction address, the encoder output is connected to the second information the input of the fifth multiplexer, the control input of the synchronization block is the input of the device, the control and address outputs of the synchronization block are connected to the synchronization bus and the address input of the command memory block.

 Comparative analysis with the prototype shows that the claimed device is characterized by altered connections of circuit elements, as well as the presence of new elements, namely, a synchronization block, the first to fifth registers, a buffer register, a buffer exchange unit, a second and third buffer blocks, a locator generator, a locator multiplexer, locator address controller, flag controller, second flag register, command converter, constant memory block, adder, analysis register, encoder, second comparator and first to fifth m ltipleksorov.

The new set of features allows the use of a modified Reed-Solomon decoder algorithm, which is described later. Due to this, in the inventive device, in comparison with the prototype, it was possible to reduce the number of conversion tables in the Galois field (2 ⁸ ) and the volume of ROM commands, as well as simplified the procedure for analyzing the results of intermediate calculations. All of the above can improve the efficiency of the device and simplify its implementation.

 Comparison of the claimed technical solution with the prototype made it possible to establish compliance with the criterion of "novelty." In the study of other well-known technical solutions in this technical field, signs that distinguish the invention from the prototype were not identified, therefore, they provide the claimed technical solution according to the criterion of "significant differences".

 In FIG. 1 is a diagram of a coding procedure; in FIG. 2 diagram of the decoding procedure; in FIG. 3 block diagram of a CIRC decoder; in FIG. 4 algorithm for calculating errors; in FIG. 5 erasure calculation algorithm; in FIG. 6 is a structural diagram of the inventive device, correcting errors; in FIG. 7 command word structure.

 In FIG. 1 and 2 show one embodiment of an encoding and decoding procedure for cross-interleaved Reed-Solomon codes (CIRC).

 In a CIRC encoder, the information processing procedure of which is shown in FIG. 1, double coding is performed by applying Reed-Solomon codes. For this, to the 24 information symbols Wi passed through the interleaver 1, four verification symbols Q0.Q3 are added to the encoder 2. Next, the newly organized codeword passed through the interleaver 3 (D is the multiplicity of the amount of information delay) is re-encoded in the encoder 4, as a result of which four more check characters P0 are added to the information. P3. The output codeword is the word obtained by passing the information encoded in the encoder 4 through the interleaver 5.

 In a CIRC decoder, the information processing procedure of which is shown in FIG. 2, the codeword is alternately interleaved in interleavers 6, 8, and 10. At the same time, the CIRC code is decoded twice in decoders 7 and 9, as a result of which possible errors are corrected. After correction, the corresponding check characters are discarded. At the decoder output, the original Wi information symbols are obtained.

 A block diagram of a codec providing the above encoding and decoding procedures is shown in FIG. 3. The CIRC codec consists of a control controller 14, a memory controller 16, a random access memory block 17, and an inventive error correction device 15. The input 11 of the codec receives the clock signals that support its operation and ensure the coordinated operation of the codec with external devices. In this case, the control controller 14 generates at the outputs 18 and 19 signals for receiving and transmitting information sent through inputs and outputs 12 and 13 between external devices and internal buses (information BD and BFL flag). The control controller also generates the necessary control signals for the device 15 and the memory controller 16. Information processing procedures are performed in the RAM block 17 at specially formed addresses and control signals coming from the memory controller 16. For each of the elements of the processing procedure in the block 17 memory organized by the corresponding memory area. The transfer of information from region to region of memory is supported on the BD and BFL buses by device 15. At the same time, device 15 performs the functions of encoders 2 and 4 (see Fig. 1) and decoders 7 and 9 (see Fig. 2), for which it performs processing information received on the BD and BFL buses. As a result, device 15 calculates error values and their locators. According to the calculated values of the locators arriving at the address input of the flag controller 16, erroneous characters corresponding to the location of these locators are called from the memory block 17. After correcting them in the device 15, the corrected characters are entered in the initial place of the memory block 17. At the same time, the state of the flags accompanying the code word changes by issuing to the BFL bus during overwriting the information in the memory unit 17 the corresponding flag value.

 In the inventive error-correcting device, the encoding mode corresponds to the decoding mode with erasure correction, i.e. errors with previously known locator values. Thus, in the inventive device, the functions of the encoder 4 and decoder 7 are performed by the decoder CI, combined with the decoder CII, performing the functions of the encoder 2 and decoder 9. The difference between the decoders CI and CII lies in the length of the processed code word.

 The operation of the claimed device will be understood from the following description.

All operations in the device are performed on the Galois field GF (2 ⁸ ). The device uses a Reed-Solomon code with a length satisfying the following inequality:
n ≅ (2 ⁸ 1). moreover, the number of information symbols in the code corresponds to the following value:
kn 2t, where 2t is the number of check characters in the codeword.

For the Hamming distance of a given code
d 2t + 1 corrective ability of the claimed device is limited by the following inequality:
2 ν + l ≅ dl, where ν is the number of errors;
l number of erasures.

The generating polynomial has the form
g (x) (x + α ^m o +) (x + α ^m o ^{+ 1} ) (x + α ^m o ^{+ 2} ).

(x + α ^m o ^{+ 2 + 1} ).

Polynomial codeword
V (x) V _o + V ₁ x + V ₂ x ² + + V _n-1 x ^n-1 , divided by g (x), i.e.

 V (x) (mod g (x)) 0.

The received word to be decoded can be represented as
C (x) C _o + C ₁ x + C ₂ x ² + + C _n-1 x ^n-1 , and
C (x) (mod g (x)) [V (x) + E (x)] (mod g (x)) E (x).

e_jx^ij (0≅j≅n-1)
Из полинома ошибок E(x) получают синдромы ошибок S_m в виде
S_m- C(

)= E(

)

e

(0≅ m≅ 2t-1).Moreover, the error polynomial E (x) for errors can be represented as
E (x)

e _j x ^ij (0≅j≅n-1)
From the error polynomial E (x), the error syndromes S _m are obtained in the form
S _m - C (

) = E (

)

e

(0≅ m≅ 2t-1).

S_ixⁱ
Через полученные синдромы в процессе декодирования вычисляют коэффициенты многочлена локаторов (х), имеющего вид
Λ(x)

(1+X_jx)

x^j, где X_j локатор ошибок или стираний.In general, the polynomial syndromes has the form
S (x)

S _i x ⁱ
Through the obtained syndromes in the decoding process, the coefficients of the locator polynomial (x) are calculated, having the form
Λ (x)

(1 + X _j x)

x ^j , where X _{j is the} error or erasure locator.

Odds can be calculated from the expression
S _{m + ν} + λ ₁ S _{m + ν-1} + + λ _ν-1 S _{m + 1} + λ _ν S _m 0, (1) where m 0. (ν -1).

The values of the error locators X are found when solving the equation
λ (x) 0.

e_jX

(1+X_ix) где e значение ошибки, которое можно представить в виде
e_j λ (X_j) * X_j ^-mo⁺¹ /λ (X_j) для каждого конкретного локатора.After calculating the error locators, the values of the errors themselves are found from the solution of the following equation:
Ω (x) S (x) Λ (x) (mod x ²⁺ )

e _j X

(1 + X _i x) where e is the error value, which can be represented as
e _j λ (X _j ) * X _j ^-m o ⁺¹ / λ (X _j ) for each specific locator.

For the case t = 2 and m = 0 have a generating polynomial
g (x) (x + 1) (x + α) (x + α ² ) (x + α ³ ).

Then equation (1) can be represented as
for ν 1
S ₁ + λ ₁ * S ₀ 0;
S ₂ + λ ₁ * S ₁ 0;
S ₃ + λ ₁ * S ₂ 0, whence it follows that
λ ₁ = S ₁ / S ₀ = S ₂ / S ₁ = S ₃ / S ₂ ;
for ν2
S ₂ + λ ₁ * S ₁ + λ ₂ * S ₀ = 0;
S ₃ + λ ₁ * S ₂ + λ ₂ * S ₁ = 0, whence it follows that
λ ₁ = a / c = X ₁ + X ₂ ;
λ ₂ = d / c = X ₁ * X ₂ , (2) where
a = S ₀ * S ₃ + S ₁ * S ₂ ;
f = S ₁ * S ₃ + S $\genfrac{}{}{0ex}{}{\text{2}}{\text{2}}$ ;
c = S $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ + S ₀ * S ₂ .

To solve system (2), a well-known method of solving the quadratic equation through a tabular function with the variable (λ ₂ / (λ ₁ ) ^{2 is used} . The root of this equation (y) is used to find error locators
X ₁ = λ ₁ * y;
X ₂ = X ₁ + λ ₁ .

Based on the assertion that
z * 0 = z / 0 = 0 / z = 0/0 = 0, (3) then the expression for λ ₁ in system (2) can be represented as
λ ₁ = S ₁ / S ₀ + (c * S ₁ / S ₀ + a) / c, then the same decoding algorithm (the so-called modified error decoding algorithm) can be used for two and one errors. This leads to increased efficiency and reduced decoder software.

 A modified error calculation algorithm is shown in FIG. 4.

The erasure calculation algorithm (see Fig. 5) for the known array of erasure locators [X _i ] is given based on the solution of the linear equation system for syndromes, taking into account the previously adopted statement (3).

The process of correcting information consists in the following operation:
V _i = C _i + e _i .

 The structural diagram of the inventive device is shown in FIG. 6. It contains a first register 20, a buffer register 21, a buffer exchange unit 22, a second register 23, a second buffer unit 24, a syndrome generator 25, a first buffer unit 26, a first flag register 27, an erase counter 28, a first locator memory unit 29, locator generator 30, locator multiplexer 31, flag controller 32, locator address controller 33, second locator memory block 34, second flag register 35, flag buffer block 36, locator buffer block 37, zero signal detector 38, analysis register 39, fourth multiplexer 40, third buffer block 41, bl to 42 RAM, adder 43, fifth register 44, third multiplexer 45, arithmetic logic unit 46, third register 47, fourth register 48, first multiplexer 49, first comparator 50, second comparator 51, second multiplexer 52, constant memory unit 53 , fifth multiplexer 54, encoder 55, command converter 56, synchronization unit 57, instruction memory block 58, command register 59, operating bus 60, information bus 12, flag bus 13, control input 61, output 62 of the correction address, control output 63, control output 64, bus 65 synchronization, shea well 66 management.

 A device for correcting errors works as follows.

 The control input 61 performs the initial installation and subsequent start of the synchronization unit 57, which generates installation pulses, exchange signals, command addresses and clock frequency for the internal components of the device.

Processing of the code word is carried out immediately by two decoders CI and CII for two frames (each lasting 588 cycles). In the first frame, the syndromes are calculated in the generator 25, for which the symbols of the corrected code are sequentially entered into the register 23, according to which the syndrome generator 25 performs the following recursion:
S _k C _i S _k * α ^k . where k 0, 1, 2, 3;
i 0. (N-1). moreover, for CI N = 32, and for CII N = 28.

 The processed symbols of the corrected code are output to the bus 12 through the buffer unit 24 for recording in the CI or CII region of the external memory. At the same time, the number of erasures and their locators are calculated. To do this, the erase flags from bus 13 are fixed in register 27. If the flag matches the logical "1" level, the state of the counter 28 and the generator 30 of the locators changes, and the previous information from the generator of locators is recorded in the memory unit 29. Register 27 issues the processed flag to bus 13 for writing to the CI or CII area of the external memory.

 Upon completion of the processing of the first codeword, the calculated values of the syndromes are overwritten in the internal memory of the syndrome generator 25, then they can be output to the operating bus 60 through the buffer unit 26, the values of the locators are overwritten from the memory unit 29 through the second input of the multiplexer 31 to the memory unit 34, regardless of at its address input, and the value of the counter 28 erases into the internal memory of the controller 32 of the flag. After that, the syndrome generator 25, the counter 28 and the memory unit 29 are ready to process the new corrected codeword.

Based on the known values of the syndromes, locators and the number of erasures in the second frame, the true values of the errors Y _i and their locators are calculated, followed by the correction of the code word.

 Algorithms consist of four-stroke calculation operations performed as follows. The first operand A is entered on the first clock in register 47 from the output of the multiplexer 49, the second operand B is entered on the second clock in register 48 on the output of the multiplexer 49.

 After the second clock, the result of adding the first and second operands in the arithmetic-logic unit 46, which is an adder modulo 255, passing through the second input of the multiplexer 52, the constant memory block and the second input of the multiplexer 49, goes to the blocked input of the adder 43. The lock occurs in if an operand corresponding to the value 255 is applied to the input of one of the comparators 50 and 51, which allows condition (3) to be realized. In the adder 43 is the addition of the above result of the addition of the first and second operands with the third operand C, fixed in register 44 in the third clock cycle. The result of the calculation of the operation in the fourth clock can be written to the memory block 42 with a volume of 16 bytes or sent to the operating bus 60 through the second input of the multiplexer 40 and the buffer block 41. To analyze the value of this result by 0, it also goes to the input of the zero signal detector 38, after whereby the analysis result can be recorded in register 39, which is used as a sequential register. Information about the status of the register 39 analysis can be issued through the first input of the multiplexer 40 and the buffer unit 41 to the operating bus 60. Moreover, the buffer unit 41 can be opened only in the fourth step of the operation.

 The multiplexer 52 allows the operands taken from the memory block 42 in the first and second clock cycles of the above calculation operation to be passed through the memory tables. To reduce the calculation time, a constant number 0 is stored in the zero cell of the memory unit 42.

53 The memory unit contains the following conversion tables in GF field (2 ^8): an element in a room space of the field member, seat number field element in the field element accommodation space field element value in the value from the table of the quadratic equation roots repetition (element in the identity element )

The calculation operation is characterized by the following mathematical functions over the operands:
A * B + C;
A / B + C.

 Thanks to the multiplexers 45 and 49, the calculation operation can be performed both on the operands taken from the RAM block 42 and on the operands coming from the operating bus 60 through the first input of the multiplexer 54. The multiplexer 54 together with the encoder 55 performs the encoding function, forming the values of the location numbers locator in the code word.

 The function of the command converter 56 is to convert the command word from the output of the register 59 commands synchronized from the bus 65 into control signals received on the control bus 66, and the addresses of the RAM block 42, supporting the calculation operation. In the codeword format shown in FIG. 7, bit INS7 determines the source of the operand used in the calculation operation, i.e. either a RAM block or bus 60. The BLOCK command disables the lock in the adder 43 and changes the adder module 46. The ALU command enables one of the operating modes of the adder 46, namely, either summation or subtraction. In the presence of command 0, the result of analysis on 0 data obtained as a result of the calculation operation is written to register 39. At the GOT command, information from register 39 enters bus 60 and, simultaneously, in controller 56, the strobe for transmitting the analysis results to the flag controller 32. The VN command allows in the fourth step of the calculation operation to connect external sources to the bus 60. The ROM table commands initialize the inclusion of one of the tables of the constant memory block 53.

 The result of the analysis in the calculation process is entered into the flag controller 32, and additionally calculated error locators are sent both to the memory unit 34 and to the controller 32, where it is analyzed for belonging to its many codeword locators. Locators from the memory unit 34 can be issued both to the bus 60 through the buffer unit 37, and to the output 62 of the correction address.

After the calculation of the error values and their locators is completed at the address set to output 62, a corrected character is called from the external RAM block 17, which, via bus 12, register 20, and buffer exchange block 22, enters the device, where modulo two is summed with the value Y _i . Next, the corrected symbol through the buffer blocks 22 and 21 is issued to the bus 12 and is entered in the original location of the block 17 of RAM.

 In the device, the register 20 and the buffer block 21 in the intervals between corrections are used to maintain the mode of exchange of information on the bus 12.

 On the output 63, the controller 32 may block the correction in the event that the number of errors exceeds the corrective capabilities of the device. For this, the output 63 is connected to the controller 16 of the external memory together with the output 62 of the correction address.

 The controller 32 makes the final decision on the possibility of error correction by the ratio of the results of the analysis and the number of erasures. After the decision is made, the controller 32 outputs to the control output 64 information about the codeword, and also initializes the flags. To broadcast previously set flags, register 35 is used, which receives flags from flag bus 13. Initialized flags arrive through the buffer block 36 on the bus 13 for recording in the external block 17 of RAM.

Processing of analysis results begins with the following reassignment:
b ₀ = a ₀ / a ₃ ;
b ₁ = a ₁ * a ₂ .

Further, taking into account the state of the internal flag register, which stores the information previously calculated in counter 28, on the number of flags F ₀ (NF ₀ ) for the CI decoder, as well as the flags F ₀ (NF ₀ ) and F ₁ (NF ₁ ) for the CII decoder the controller 32 in accordance with the table of the error decoder and the algorithm generates a correction enable command (k), which is output 66, and flags on the channels F ₀ and F ₁ for the decoder CI and F ₀ , F ₁ and F ₂ for the decoder CII, issued on control output 66 and on to bus 13.

 To switch programs (erasure or errors) in the block 58 of the command memory from the controller 32 to its control input receives the corresponding signal.

 The experimental work of the claimed error-correcting device as part of the Reed-Solomon codec for optical storage devices showed that, in comparison with a device of a similar purpose (prototype), the claimed device allows more efficient use of software resources, i.e. the volume of used ROMs is sharply reduced, and its implementation is greatly simplified, which makes it possible to successfully implement the claimed device on semi-ordered CMOS matrix LSIs with a small degree of integration.

Claims (1)

 ERROR CORRECTION DEVICE, comprising a syndrome generator, a first buffer block, a first flag register, an erase counter, a first locator memory block, a locator buffer block, a flag buffer block, a command memory block, a command register, a random access memory block and a zero signal detector, arithmetic a logical unit, a first comparator, an information bus, an operating bus and a flag signal bus, characterized in that, in order to increase the information capacity of the device and simplify it, a synchronization block, the first heel registers, buffer register, buffer exchange block, second and third buffer blocks, locator generator, locator multiplexer, locator address controller, flag controller, second flag register, command converter, constant memory block, adder, analysis register, encoder, second comparator and the first fifth multiplexers, control inputs of the constant memory block, arithmetic logic block, random access memory block, first fifth multiplexers, third fifth registers, analysis register, third buffer block, first and w The comparators and the encoder are combined and connected to the control bus, the control output of the command converter is connected to the control bus, its address output is connected to the address input of the RAM block, the output of which is connected to the information inputs of the first and third multiplexers, the output of the arithmetic-logic block is connected to the second information input of the third multiplexer, the second information input of which is connected to the output of the arithmetic-logical unit, the output of which is connected to the address input of the unit as a constant memory, the output of which is connected to the first information input of the second multiplexer, the second information input of which is combined with the second information input of the first multiplexer and connected to the output of the fifth multiplexer, the output of the second multiplexer is connected to the adder lock input and to the information inputs of the third and fourth registers, outputs which are connected respectively to the first and second inputs of the arithmetic-logical unit and the information inputs of the first and second comparators, the outputs of which x are connected to the blocking inputs of the adder, the first input of which is connected to the output of the third register, and the output is connected to the information input of the RAM block, the first information input of the fourth multiplexer and the input of the zero signal detector, the output of which is connected to the input of the analysis register, the output of which is connected to the second the information input of the fourth multiplexer, the output of which is connected to the input of the third buffer block, the output of which is connected to the operating bus, the output of the first buffer block, the information input of the fifth multiplexer, the output of the locator buffer block, the first input of the locator multiplexer, the first input of the flag controller and the first input-output of the buffer exchange unit are connected to the operating bus, the second input-output of the buffer exchange unit is connected to the input of the buffer register and the output of the first register, the input of which is combined with the outputs of the buffer register and the second buffer block, with the input of the second register and connected to the information bus of the device, the output of the second register is connected to the inputs of the second buffer ith block and syndrome generator, the output of which is connected to the input of the first buffer block, the control input of which is combined with the control inputs of the syndrome generator, buffer block of locators, encoder, flag controller, command converter and the output of the command register, the input of which is connected to the output of the command memory block, the control input of which is connected to the first control output of the flag controller, the second control output of which is connected to the control input of the locator address controller, the third control output d is the control output of the device, the control output of the command converter is connected to the control input of the flag controller, the flag input of which is connected to the output of the second flag register, and the flag output is the control output of the device and connected to the input of the flag buffer block, the output of which, as well as the inputs of the first and the second flag registers are connected to the device’s flag signal bus, the output of the first flag register is connected to the control inputs of the first locator memory block and the erase counter, the output of which is It is connected to the second information input of the flag controller and the address input of the first locator memory block, the information input of which is connected to the output of the locator generator, and the output is connected to the second input of the locator multiplexer, the output of which is connected to the information input of the second locator memory, the address and control inputs of which are connected to the corresponding outputs of the locator controller, and the information output is connected to the information input of the locator buffer block and is the output of the address of the correction oystva, encoder output is connected to the second data input of the fifth multiplexer, a control input sync block is the input device, the control and address outputs connected to the sync block synchronization and the address bus input commands of the storage unit.

Images