JPH0345020A - Cyclic code processing circuit - Google Patents

Abstract

PURPOSE:To attain higher speed processing by providing one or more data generating means outputting a prescribed data with respect to a corresponding check bit to a parallel data of an information bit forming one code word. CONSTITUTION:A memory 60 storing data of cyclic codes to input data i0, i1,..., ik-1, ik as a table receives the data i0, i1,..., ik-1, ik at addresses A0, A1,..., Ak-1, then outputs relevant check bits r0, r1,..., rm-1 from data outputs D0, D1,..., Dm-1. A latch circuit 62 latches the input data i0, i1,..., ik-1, ik and output of the memory 60 corresponding to them, that is, the check bits r0, r1,..., rm-1 as a code word. That is, the relevant check bit or a data based thereon is generated by the parallel processing with respect to the information bit. Thus, the check bit is obtained at high speed independently of the bit rate of the information bit and the data with a high bit rate is processed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cyclic code processing circuit that processes cyclic codes for detecting and correcting data transmission errors at high speed.

[Prior Art] Conventionally, digital signal transmission systems have used an error detection and correction method that detects and corrects transmission errors by adding appropriate redundant bits to information data. One of the encoding methods is CRCC (cy
clic redundancy check cod
There is e). A conventional example of a CRCC encoding/decoding device will be described below. However, all operations below are based on the Galois field.

When cyclically encoding the information polynomial 1(x), 1(x)=
i, +i, x+Lx"+i, x"+-・-+ih-, x
k-' (L), and the generator polynomial G(x) is G(x): go+g+x+g*x"+glx"+-・-
+g, x” (2), the code word A(x) as a systematic code is A(x)=R(x) +I(x)
x” (3). However, R(x)=I(x)x” mod G(x)
(4).

FIG. 3 shows a block diagram of the configuration of an encoding circuit that performs this encoding. 10, 12.14 is a delay circuit of 1 unit time,
16, 18.20 are multipliers that multiply by constants go+g++g, -1, 22, 24.26 are arithmetic circuits that take the exclusive OR of two inputs, 28.30 are switches, 32 are delay circuits 10, 12 .14 and a timing circuit that defines the operation timing of the switches 28 and 30, 34 is an input terminal for information to be encoded, and 36 is an output terminal for a code word.

The operation shown in FIG. 3 will be explained. First, delay circuit 10°12.1
4, connect the switch 28°30 to the A contact side, and input information from the input terminal 34 to 1k-1+1k-1.
+...+ 11 + io is manually applied in this order. Since the switch 28 is connected to the a contact point, the input information of the input terminal 34 is output as is from the output terminal 36, but at the same time, it is outputted from the delay circuit 10, via the arithmetic circuit 26 and the multiplier 16°18.20. 12.14 and 10 is output from the output terminal 36, the delay circuits 10, 12.
14, the remainder R(x) remains. Therefore, switch 28.30 is connected to the b contact side, and the remainder r+m-x, rm
-*+..., rl, and To are taken out from the output terminal 36. In this way, the code word A (x
) can be obtained.

When decoding such a code word A (x), the received word Y (x) is written as Y (x) = yo÷Y1X + ytX" + ... + y
@-IX'-” (5), and the error pattern E
(x), E(x)=e, ÷6+X+e*X'+"'+all-+
If X″-1 (6), then Y(x
) is Y(x)=A(x)+E(x)
It is expressed as (7). Syndrome polynomial 5(x
) is 5(x) two Y(x) mod G(x)
(8), and when 5(x)=0, it is determined that there is no error.

FIG. 4 shows a schematic block diagram of a decoding circuit that performs this decoding process. 38, 39.40 are delay circuits with a unit delay amount, 42, 43, 44, 45.46 are multipliers that multiply by the constants go, g++ gt, g-s, g-, and 48, 49, 50.51 are Arithmetic circuit that takes exclusive OR of two inputs, 52 is a delay circuit 38.39.4
54 is an input terminal for the code word transmitted through the transmission line, and 56 is an output terminal for decoded information. The received word Y(x
) are yn-1, yn-2, ... y2. If input in the order of yl, a coefficient of 5(x) will be obtained in the delay element 38°39.40.

[Problems to be Solved by the Invention] In the conventional example described above, the encoding circuit or the decoding circuit operates with the same clock as the bit rate of the data, so it is not suitable for high bit rate data.

An object of the present invention is to provide a cyclic code processing circuit that can perform faster processing.

[Means for Solving the Problems] A cyclic code processing circuit according to the present invention is a circuit that encodes or decodes a cyclic code for data transmission error detection/correction. - It is characterized by comprising one or more data generation means for outputting predetermined data regarding the corresponding check bits with respect to the data.

[Operation] The data generating means generates the corresponding check bits or the data on which they are based by performing parallel processing on the information bits. can be obtained.

That is, high bit rate data can be processed at high speed.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

1A and 1B are block diagrams of an embodiment of the present invention, with FIG. 1A showing an encoding circuit and FIG. 1B showing a decoding circuit. In FIG. 1A, 60 is input data t
,,i,...+' is a memory that stores cyclic code data for -1, 1k as a table, and data i is stored at addresses A'o, At,...Ak-1. .

When il,..., 1k-1, ik is input manually, the corresponding check bit rO+' + +...+ rlI-1 is output from the data output Do,l)+,...,D,-□. . 62 is a latch circuit, and input data 1G+11+
. . , 1h-1+ik and the corresponding output of the memory 60, that is, the check bits r, , r, . . . -rm-1 are latched and output as code words.

In FIG. 1B, 64 is a memory having the same contents as the memory 60, and when information bits of a received code word including an error pattern are inputted, a corresponding check bit is outputted.

66 is a bit-by-bit comparator, which compares the check bits of the received code word containing the error pattern with the check bits from the memory 64, bit by bit, and outputs an error detection signal indicating the presence or absence and location of an error. . If all the bits compared by the comparator 66 match, it means that there is no error.

FIG. 2A is a schematic block diagram of a main part of a processing circuit according to a second embodiment of the present invention when the number of information bits and the number of check bits for the information bits are large.

That is, FIG. 2A shows an example of a modification of the memories 60 and 64 of the encoding circuit of FIG. 1A and the decoding circuit of FIG. 1B. 7
0, 71, 72.73 are memories that output check bits to be described later for address input, 76.77.78.79
is an arithmetic circuit that performs exclusive OR. In the illustrated example, 2
0 bit human power LO+i1. . . il, 8-bit check bits r O+ r 1 * . . . , r are generated. The theoretical background of the calculation will be explained assuming that it is based on the Galois field.

The following relationship exists between input data i and check bit r.

(ro+rl+..., r7) =(io, lt,...11111) Decomposing equation (9) into four parts, (r.

, rl , r*', r*') = (10+11+..., i,) (r4', re, ro, r7°) = (to, i,,..., i,) (ro, r ,',r tatamire'') = (11°+lII+...+l!9)(r4,re
−, re”, rt”) = (11°+111+..., LJ. However, r, = r, '+r,' (m = 0 to 7)
(14). The coefficient (g+,
Since +l is known in advance, (to, 1+, ...,
i,) for (ro” +r+ ’, r2°2r,
゛) is determined in advance, and the address is (io, L,...
, i, ), the output data is the formula (lO
) is stored in the memory 70, such as a data table from which (r.', r+', rz', r*') can be obtained. Similarly, data tables having the relationships of equations (11), (12), and (13) are stored in memories 71, 72, .
73.

Then, calculation circuits 76, 77; 78, 79 perform the calculation of equation (14) to obtain check bits (re, r'+, . . . , r7), which are the final target values.

Figure 2B shows a case where the number of information bits and the number of check bits are further increased than in the case of Figure 2A, and the number of information bits is (a-1
)n, the number of check bits is bm, and is a schematic block diagram of the main part of the embodiment, and similar to FIG. 2A, FIG. 1A,
An example of a modification of the memory 60, 64 portion of FIG. 1B is shown. As shown, in the configuration of FIG. 2B, memories 80 to 88 similar to the memories 70 to 73 of FIG. 2A are arranged in a matrix configuration, and input information bits 10+..., l (a
-N++-1 is divided into a sets, and the information bits of each set are manually entered into address inputs of the memory in the same row. Each memory 80
.about.88 outputs data related to the corresponding check bit, similar to FIG. 2A. Then, by calculating the outputs from the memories in the same column using the exclusive OR circuits 90 to 95, the target check bits ro+...rny can be obtained.

A decoding circuit using the circuits shown in FIGS. 2A and 2B uses the configuration shown in FIGS. 2A and 2B to obtain check bits for information bits in a received code word, as in the case of FIG. 1. , this check bit and the check bit in the received codeword may be compared by a bit comparator.

With the above configuration, data is processed in parallel, and the desired output can be obtained very quickly. Furthermore, since it is independent of bit rate, it can process high bit rate signals at high speed as well.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, check bits for information bits can be obtained quickly and independently of the bit rate. Therefore,
High bit rate data transmission can be easily achieved.

[Brief explanation of drawings]

FIG. 1A is a schematic block diagram of the encoding circuit according to the first embodiment of the present invention, FIG. 1B is a block diagram of the decoding circuit corresponding to FIG. 1A, and FIGS. 2A and 2B are the number of information bits. and a schematic block diagram of another embodiment of the present invention when the number of check bits is increased, FIG. 3 is a block diagram of a conventional encoding circuit, and FIG. 4 is a constitutional block diagram of a conventional decoding circuit. It is a diagram.

Claims (1)

[Claims] A circuit that encodes or decodes a cyclic code for data transmission error detection and correction, and outputs predetermined data regarding corresponding check bits for parallel data of information bits constituting one code word. 1. A cyclic code processing circuit, characterized in that it is provided with more than one data generating means.