JPS61242426A - Chained encoding and error correcting circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of hardware by performing error correcting and encoding processing for respective input data by using the same generating polynomial by plural chained encoders, and also making error corrections for the respective input data on a reception side by allowing plural chained decoders to share one error position deciding circuit. CONSTITUTION:The 1st BCH encoder 9 adds 15 error correction bits for BCH encoding to original data consisting of, for example, 112 bits and outputs a 127-bit error correction code. The 2nd BCH encoder 10 used the same code generating polynomial with the 1st BCH encoder 9 to adds a 15-bit error correction code to the 112-bit input data sequence and transmits a 127-bit data sequence. The reception side generates a syndrome from the received data by a BCH decoder 11 firstly. This syndrome is used as an address signal to a ROM circuit 12 for error position decision making to read a data error position out of the ROM circuit 12 for error position decision making, and corresponding bits of the input data are inverted to make an error correction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an error correction circuit, and in particular to a chain code in which a plurality of encoders are connected in a chain through a bit interleaving circuit in order to increase the coding gain due to error correction. This invention relates to an error correction circuit.

Summary of the invention The present invention relates to an error correction circuit using a chain connection method.

A plurality of chain-connected encoders all use the same generator polynomial to perform error correction encoding processing on each input data, and on the receiving side, a chain-connected plurality of decoders perform error correction encoding processing on each input data using the same generator polynomial. This is a chain encoding error correction circuit that uses a common error position determination circuit and outputs data obtained by performing error correction on each input data.

By sharing the error position determination circuit among multiple decoders, there is an effect that the hardware scale can be reduced.

Prior Art FIG. 3 is a block diagram showing an example of a conventional chain coding error correction circuit. That is, the outer code encoding circuit 2 performs error correction encoding on the original data input from the original data input terminal 1 using a certain algorithm, and outputs data with error correction bits added. The bit arrangement of the output data string of the outer code encoding circuit 2 is changed and inputted to the inner code encoding circuit 4.

The inner code encoding circuit 4 further performs error correction encoding processing on the output data string of the bit interleave circuit 3 using another algorithm different from the above-mentioned one, and then transmits the data.

On the receiving side, the received data is first error-corrected by the inner code decoding circuit 5. The inner code decoding circuit 5 performs error correction decoding corresponding to the inner code encoding circuit 4 on the transmitting side, but in order to do so, it first generates a syndrome from the received data, and uses the syndrome to determine the error position for the inner code. The position of the data error is known by referring to the circuit 18, the corresponding bit is inverted, and the error-corrected data is output to the dinterleave circuit 6. Inner code error position determination circuit 18
For example, a read-only memory can be used in which the syndrome is input as an address signal and information indicating the data error position is stored in advance at the corresponding address.

The remaining error bits that could not be corrected by the inner code decoding circuit 5 are dispersed by changing the bit arrangement in the dinterleave circuit 6. The bit arrangement change of the dinterleave circuit 6 is of course the inverse of the bit arrangement conversion of the bit interleave circuit 3 on the transmission side, so the bit arrangement of the output data of the dinterleave circuit 6 is the outer code of the transmission side. The bit arrangement of the output data of the encoder circuit 2 is the same. However, it contains some error bits.

Therefore, the outer code decoding circuit 7
If the error correction decoding corresponding to the error correction is performed to correct the error, the original data can be correctly reproduced. For this purpose, the outer code decoding circuit 7 generates a syndrome for the input data, and the outer code error position determination circuit 19 determines the error position based on the syndrome and notifies the outer code decoding circuit 7. The code decoding circuit 7 inverts the error bits and outputs the error-corrected data to the decoded data output terminal 8.

The above-mentioned conventional circuit disperses concentrated errors occurring on the transmission path by changing the bit arrangement.
Errors that cannot be corrected by one decoder can be corrected by the other decoder, and the coding gain can be increased. However, on the receiving side, the inner code decoding circuit 5 and the outer code decoding circuit 7 However, since the inner code error position determination circuit 18 and the outer code error position determination circuit 18 are separately required, the hardware becomes complicated and large-scale.

Problems to be Solved by the Invention The present invention solves the above-mentioned conventional drawbacks and provides a chain coding error correction circuit with a small circuit scale and high coding gain.

Structure of the Invention The chain-coded error correction circuit of the present invention includes, on the transmitting side, a plurality of encoders that perform error correction encoding using the same generator polynomial for each input data, and a plurality of encoders described above. and a bit interleave circuit for changing the arrangement of output bits of a previous-stage encoder among the encoders and inputting the output bits to the next-stage encoder, and the plurality of encoders are connected in a chain via the bit interleaving circuit. The transmitter transmits the transmission data that has been error-corrected encoded in multiple stages, and on the receiver side, a syndrome is calculated for each input data using the same generator polynomial used by the encoder on the transmitter side. A plurality of decoders that output error correction data by referring to a position determination circuit, and an error position that is shared by the plurality of decoders and outputs a signal indicating the position of each data error based on the syndrome input from each decoder. judgment circuit.

and a dinterleave circuit for restoring the bit arrangement of the output data of the decoder in response to bit interleaving on the transmission side, the plurality of decoders are connected in a chain via the dinterleave circuit. Each of the plurality of decoders refers to the error position determination circuit and outputs error-corrected data.
Configure it as follows.

Embodiments of the Invention Next, the present invention will be described in detail with reference to one drawing.

FIG. 1 is a block diagram showing an embodiment of the present invention.

That is, the original data input from the original data input terminal 1 is subjected to error correction encoding processing by BCH encoding by the first BCI encoder 9 and is input to the bit interleave circuit 3. The first BCH encoder 9 adds, for example, 15 bits of error correction bits by BCI encoding to the 112-bit original data, and outputs it as a 127-bit error correction code. This allows 2-bit error correction on the receiving side.

The bit interleaving circuit 3 changes the bit arrangement of the data string output from the first BCH encoder 9 and inputs it to the second BCH encoder 10. The bit arrangement conversion rule is arbitrary, but for example, if the 127-bit data string output from the first BCH encoder 9 is one frame, and the data string for 8 frames is converted, 8 bits jump from the 1st bit. Next, the data is arranged in 8-bit intervals starting from the second bit, and then converted into a 127×8-bit data string in the same manner. Such an arrangement conversion can be easily realized by using, for example, a matrix-arranged memory and swapping the rows and columns of the write address and read address.

The second BCH encoder IO is exactly the same encoder as the first BCI encoder 9, and uses the same code generating polynomial as the first BCH encoder 9 to generate 112-bit input data string.
A 5-bit error correction code is added and transmitted as a 127-bit data string.

On the receiving side, the second BCH decoder 11 first performs error correction decoding on the received data, that is, generates a syndrome from the received data, and uses the syndrome as an address signal for the error position determination ROM circuit 12 to determine the error position. It is possible to correct up to 2 errors in 127 bits of received data by reading the data error position from the ROM circuit 12 and inverting the corresponding bit of the input data. A 3-bit error can be detected but not corrected. However, if there is a 3-bit error, for example, when the bit array is converted by the dinterleave circuit 6, the error bits will be distributed over multiple frames. be done. The bit array conversion of the dinterleaving circuit 6 corresponds to the bit interleaving circuit 3,
The output data string of the dinterleave circuit 6 is the first BCI
It has the same bit arrangement as the output data string of the encoder 9. First BCH decryption! 113 generates a syndrome for the data input from the dinterleave circuit 6 in the same manner as the second BCH decoder 11, and reads the position of the error bit from the error position determination ROM circuit 12 based on the syndrome. Error correction is performed on the decoded data, and the decoded data is output to the decoded data output terminal 8. Therefore, the above 3-bit error is corrected. However, the timings at which the first and second BCH decoders access the error position determination ROM circuit 12 must be staggered.

In this embodiment, the circuit configurations of the first and second BCH decoders are exactly the same, and only one ROM circuit for error position determination is sufficient. Therefore, there is an effect that the design is simplified, the scale of one circuit is small, and a high encoding gain can be obtained.

FIG. 2 is a block diagram showing another embodiment of the present invention,
In this case, on the transmitting side, three identically configured first to third BCI encoders 9 and 10.15 are connected in a chain through the first and second bit interleaving circuits 3 and the second bit interleaving circuit 3, and on the receiving side, , a third BCH decoder 17 with the same configuration. The second BCH decoder 11 and the first BCH decoder 13 are connected in a chain by a second dinterleave circuit 16 and a first dinterleave circuit 6. 1st BCH
Decoder 13. Second BCH decoder! 1st and 3rd BC
H decoder! 7 uses one error position determination ROM circuit 12 in common by shifting the access timing. The first dinterleaving circuit 6 and the second dinterleaving circuit 1B correspond to bit arrangement conversion of the first bit interleaving circuit 3 and the second bit interleaving circuit 14 on the transmitting side, respectively. Of course, it is possible to restore the original state. Although the bit arrangement conversion rules for the first and second bit interleaving circuits are arbitrary, it is desirable to be able to disperse concentrated bit errors to positions as far apart as possible.
The error position determining ROM circuit 12 can be shared by all decoders, and it is possible to further improve the error correction ability than the embodiment using the double chain encoding method described above.

Effects of the Invention As described above, in the present invention, in the chain coding error correction circuit, the plurality of encoders all perform error correction coding using the same coding generating polynomial. It becomes possible for all the plurality of decoders on the receiving side to perform error correction using one ROM circuit for error position determination. Therefore, there is an effect that the circuit scale can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional chain coding error correction circuit. In the figure, l: original data input terminal, 2: outer code encoding circuit, 3: (first) bit interleave circuit,
4: Inner code encoding circuit, 5: Inner code decoding circuit, 6:
(first) dinterleave circuit, 7: outer code decoding circuit, 8: decoded data output terminal, 9: first BCH encoder, ! 0: second BCH encoder, 11: second 8CH decoder, 12: error position determination ROM circuit, 13: first BCH decoder, 14: second bit interleave circuit, 15: third OIC encoder, 18: second dinterleave circuit, 17: third BCH decoder, 18: error position determination circuit for inner code, 19: error position determination circuit for outer code.

Claims (1)

[Claims] A plurality of encoders on the transmitting side perform error correction encoding using the same generator polynomial for each input data, and an output of the preceding encoder among the plurality of encoders. and a bit interleave circuit that changes the bit arrangement and inputs it to the next-stage encoder, and the plurality of encoders are connected in a chain via the bit interleave circuit to perform multi-stage error correction encoding. The data is sent, and on the receiving side, a syndrome is calculated for each input data using the same generating polynomial used by the encoder on the sending side, and the syndrome is referred to by the error position determination circuit described later. a plurality of decoders that output error correction data, and an error position determination circuit that is shared by the plurality of decoders and outputs a signal indicating the position of each data error based on a syndrome input from each decoder; a deinterleaving circuit for restoring the bit arrangement of output data of the decoder in response to bit interleaving on the transmitting side, the plurality of decoders being connected in a chain via the deinterleaving circuit; A chain encoding error correction circuit, wherein each of the plurality of decoders refers to the error position determination circuit and outputs error-corrected data.