JPS6322736B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital information decoding system, and particularly to a system for performing double encoding such as a product code among code decoding systems having an error correction function for digital information.

Figure 1 is a block diagram showing a conventional product code encoding/decoding system. 1 is an information input terminal, E ₁ is C ₂
encoder, E ₂ is C ₁ encoder, 2 is encoding control device,
Reference numeral 3 indicates noise on a transmission path, 4 indicates a transmission path, 5 indicates a receiving side input terminal, D ₁ indicates a C ₁ decoder, D ₂ indicates a C ₂ decoder, 6 indicates a decoding control device, and 7 indicates an information output terminal. In the figure, the buffer memory that is required during encoding and decoding is not shown because it would be too complicated and can be constructed using conventional technology. Also, in the figure P ₁ , P ₂ , P ₃ ,
The upper part of FIG. 1 shows changes in the digital data bit format during each encoding/decoding process at points _P4 and _P5 .

Digital information with a rectangular arrangement of k ₂ × k ₁ bits is processed by a C ₂ encoder E ₁ based on the C ₂ encoding algorithm for each column, k ₂ data bits n ₂ bits of C ₂
is encoded into the code word. The C ₂ encoder E ₁ executes this encoding operation _k times according to the command from the encoding control circuit 2, and a rectangular arrangement of n ₂ ×k ₁ bits is completed. Next, row-wise encoding is performed, and the _C1 encoder _E1 encodes every _k1 data bits into _n1 bits based on the encoding algorithm of _C1 according to the instruction of the encoding control device 2. become This operation is performed n ₂ times and transmitted to the transmission path as a rectangular code format of n ₂ ×n ₁ bits.

On the receiving side, the received bits input from the receiving side input terminal 5 are input to the _C1 decoder _D1 . _C1 decoder
_D1 performs decoding based on the decoding algorithm of _C1 for each row of received words arranged in a rectangular arrangement of _n2 × _n1 bits. The C ₁ decoder D ₁ executes n ₂ decoding based on the command from the decoding control device 6, and performs n ₂ decoding in a rectangular arrangement.
×k ₁ bit is output from _C1 decoder _D1 and input to _C2 decoder _D2 . The C ₂ decoder D ₂ performs _{k 1 decoding} for each column of the input _{n 2} Obtain k ₂ × k ₁ bits of information corresponding to the original information.

A conventional type of system that is a further development of this conventional system is shown in FIG.

Figure 2 shows multi-stage decoding (decoding is performed more than once) in order to increase the correction ability without changing the encoding side hardware (transmission side) or code word format when the transmission path is in poor condition. The system is structured according to the following method. The method shown in FIG. 1 is called two-stage decoding. Numbers 1 to 7 in FIG. 2 indicate the same or equivalent parts in the configuration of FIG. 1. In the figure D ₁ is C ₁ decoder,
D ₂ is a C ₂ decoder, D ₃ is a C ₁ decoder, D ₄ is a C ₂ decoder,
D ₅ is a C ₁ decoder... and D _k at the final stage is a C ₁ or C ₂ decoder. Since the same decoder may be used repeatedly, there are not necessarily k decoders, but the number of decoding stages is k. Compared to the type of decoding system shown in Figure 1, _C1 decoding and
The number of stages of C ₂ decoding is increasing, and errors that cannot be corrected in decoder D ₁ are corrected in decoder D ₂ , errors that cannot be corrected are further corrected in decoder D ₃ , and so on. This increases the number of errors that can be corrected and improves reliability.

However, this conventional type of decoding system has the following disadvantages. The reason is that there is a specific residual error pattern, which cannot be improved no matter how many times the decoding is repeated.

Figure 3 is an explanatory diagram showing the contents of the RAM memory used for decoding. When a t _single correction code is used for C ₁ and a t _double correction code is used for C ₂ , the rows of t ₁ +1 and above and t ₂ +1
The grid-like error patterns in the above columns remain uncorrected. In the conventional type of decoding system, the residual error pattern X remains as it is, and no improvement can be expected even if the number of decoding stages is increased.

The present invention has been devised to address these disadvantages of the conventional system, and its configuration is as shown in FIG. 4, 5, 6, 7, D ₁ , D ₂ , ..., D _k is the first
It is the same or equivalent part as shown in the figure or FIG. 8 is a residual erasure estimation device; 9 is a residual erasure correction device; 10 is an input/output terminal for transmitting a signal from the residual erasure estimation device 8 to the residual erasure correction device 9;
Reference numeral 1 denotes a lead line for inputting decoding information for each decoding to the residual erasure estimating device 8.

The information input from the decoding side input terminal 5 is sequentially decoded by _C1 decoder _D1 , _C2 decoder _D2 , _C1 decoder _D3 ,..., _C1 decoder or _C2 decoder _Dk . While the residual error patterns are being filtered, information regarding the remaining error patterns is output to the residual erasure estimation device during decoding. This state is called filtering mode. In the present invention, D ₁ ,
D ₂ , ..., D _k are called filtering decoders. The residual erasure estimation device 8 estimates a residual error pattern from the decoding information obtained in the decoding stages from D ₁ to D _k , and uses it as an erasure during decoding in the residual erasure correction device 7. The residual erasure correction device 9 is the residual erasure estimation device 8.
The erasure symbols in the lattice arrangement estimated by are sequentially soft-decision decoded and predetermined data is output.

Hereinafter, a more detailed description will be given of specific examples using FIGS. 5, 6, 7, and 8. The C ₁ code is a 32,28,5,RS (Reed-Solomon) code on GF(2 ⁸ ), and the C ₂ code is 28,24,5,R- on GF(2 ⁸ ).
S code is used as a filtering C ₁ decoder and a filtering C ₂ decoder. 1 each
It is assumed that a soft-decision decoder is used for the erasure correction C ₁ decoder and the erasure correction C ₂ decoder, which has functions of error correction and 2 and 3 error detection, and that corrects up to four erasures. Here, the n, k, d code means a linear code with code length n, number of information symbols k, and distance d.

Figure 5 shows a filtering C ₁ decoder, a filtering C ₂ decoder, a RAM memory unit, and a part of the residual erasure estimation device that performs filtering decoding, and 12 stores data in a rectangular arrangement when decoding. X is the error pattern, 13 is the RAM address control circuit, 14 is the RAM memory to
Data input terminal to RAM memory, 15
Data output terminal from RAM memory, _D1 is filtering _C1 decoder, _D2 is filtering _C2 decoder, 16 is a 28-bit register that stores each decoding result of row code _C1 as erasure flag information. , 17 is a 32-bit register for storing each decoding result of column code _C2 as erasure flag information, and 18 is a register for filtering mode (mode for filtering decoding) and erasure correction mode (mode for performing erasure correction decoding). A mode switch for switching, 19 is a data output terminal from the first register 16 to the first counter (described later), 20 is a data output terminal from the second register 17 to the second counter (described later), and 21 is a data output terminal for the second counter (described later).
A control signal input terminal to the RAM address control circuit 13, 22 a control signal input terminal to the first register 16, 23 a control signal input terminal to the second register 17, 24 a filtering C ₁ decoder D ₁
control signal input terminal to, 25 is filtering
C ₂ is a control signal input terminal to the decoder D ₂ ; 26 is a control signal input terminal to the mode changeover switch;
Reference numeral 7 denotes an output terminal for transferring data from the RAM memory to the erasure correction decoding section in the erasure correction mode.

For convenience of explanation, an example will be described in which k=4, that is, filtering decoding is performed in four-stage decoding.

If nine errors occur as shown in FIG. 5 and they happen to be a ₃ × ₃ grid- _like error pattern X as shown in _FIG .
In each stage of decoding, the filtering decoders D ₁ and D ₂ correct only a single error, so the error is not corrected and the error pattern remains as is. During the _C1 decoding operation in the third stage, the filtering _C1 decoder performs _the first
"1" is stored in the register 16 as an erasure flag, and when no detection is detected, "0" is stored as an erasure flag. The fourth stage decoding, i.e.
When decoding _C2 , the filtering _C2 decoder sets "1" to the second register 17 as an erasure flag for columns in which two or more errors are detected when decoding each column code. When this happens, "0" is stored as an erasure flag.

In this way, information was stored corresponding to the rows and columns of the grid-like error pattern. Next, the mode changeover switch 18 is switched from the filtering decoding mode to the erasure correction decoding mode by a command from the control circuit. Figure 6 shows the remaining part of the erasure estimation device, 19, 20, 21, 22, 2
3, 24, 25, and 26 are the same as those in FIG. 28 is the first counter, 29 is the second counter, 30 is the first memory, and 31 is the second counter.
32 is a first comparator, 33 is a second comparator, 34 is a determination circuit, and 35 is a switch for selecting whether to perform erasure correction on row code _C1 or column code _C2 . 36 is a control signal output terminal to the erasure correction C ₁ decoder, and 37 is a control signal output terminal to the erasure correction C ₂ decoder.

In FIG. 6, output signals from the first register and the second register are inputted to first and second counters 28 and 29 through terminals 19 and 20. The first and second counters count the number of erasures stored in the first and second registers, and the first comparator 32 and second comparator 33 count the number of erasers stored in the first and second registers. The numerical values "d ₂ -1" and "d ₁ -1" (both 4 in the present embodiment) stored in the memory 31 and the first,
The numerical values of the second counter are compared in magnitude, and when the contents of the memory are greater or equal, "1" is outputted to inform the determination circuit 34 that erasure correction is possible.

FIG. 7 is an operation table of the determination circuit 24, which shows the operation of the determination circuit that indicates in which decoding direction the erasure correction can be performed in the row direction and the column direction.

In the table of FIG. 7, case a indicates that both the first comparator 32 and the second comparator 33 are capable of erasure correction in the column direction and the row direction. Now, for convenience, we will select a C ₂ decoder to decode the column code. Case b is a case where the number of code words in the row direction where the erasure flag is set is four or less, and the number of code words in the column direction where the erasure flag is set is five or more. If the codes C ₂ in the column direction are sequentially decoded, all errors can be corrected by performing erasure correction of 4 or less on the code word of each C ₂ code.

Case c is a case where the number of column direction code words with erasure flags set is 4 or less, but the number of row direction code words with erasure flags set is 5 or more, and the row direction code C ₁ If decoding is performed sequentially, erasure correction of 4 or less can be performed on each code word of code _C1 , and all errors can be corrected.

In case d, the number of erasures exceeds the correction ability in either the row or column direction, and secondary relief measures such as data interpolation and alarms are taken to prevent a decrease in reliability.

FIG. 8 is an explanatory diagram of the residual erasure correction device. In the figure, 27 is the same as or equivalent to that explained in FIG. 5, 35, 36, 37 are in FIG. 6, and 7 is the same as that explained in FIG. be. In the figure, 38 indicates whether the data is corrected by the _C1 erasure correction decoder or the _C2 erasure decoder or not, and the reliability of the data is determined by secondary relief measures such as data interpolation according to the instructions from the decision circuit 34. This is a switch to select whether to take measures to prevent the decline. The result of filtering decoding is C ₁ based on the command of the judgment circuit input from 35.
The remaining erasure is corrected by an erasure correction decoder or a _C2 erasure correction decoder, and then output from the information output terminal 7.

As described above, in addition to the configuration of a conventional decoder, the decoder according to the present invention includes a residual erasure estimation device,
Since it is equipped with a residual erasure correction device, it is possible to provide a highly reliable encoding/decoding system.

[Brief explanation of the drawing]

Figure 1 is a block connection diagram of a conventional encoding/decoding system, Figure 2 is a block connection diagram of another type of conventional encoding/decoding system, and Figure 3 is a block connection diagram of a conventional encoding/decoding system of the type shown in Figure 2. FIG. 4 is a diagram showing an example of a residual error pattern, FIG. 4 is a diagram showing a block connection part of a decoding system according to the present invention, and FIG. 5 is a diagram showing a part a of the filtering decoder and residual erasure estimation device of FIG. 4. 6 is a diagram showing the remaining part b of the residual erasure estimation device in FIG. 4, FIG. 7 is a diagram showing the operation of the determination circuit of the residual erasure estimation device in FIG. 6, and FIG. It is a diagram showing an erasure correction device, where D ₁ is a filtering C ₁ decoder, D ₂ is a filtering C ₂ decoder, 8 is a residual erasure estimation device, 9 is a residual erasure correction device, and 16 is an erasure in the row direction. A first register for storing flag information, 17 is a second register for storing erasure flag information in the column direction, 28
is the first counter, 29 is the second counter,
32 is a first comparator, 33 is a second comparator, 34
is a judgment circuit. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] 1. In a decoding system that performs multi-stage decoding on the receiving side of an encoding/decoding system that performs double encoding such as a product code, there are two types of decoders: a filtering decoder and an erasure correction decoder. 1. A decoding system comprising: a control device for switching between a filtering mode and an erasure correction mode to correct errors. 2. In a decoding system that performs multi-stage decoding on the receiving side of an encoding/decoding system that performs double encoding such as a product code, error patterns that cannot be corrected are sequentially decoded by a decoder with a predetermined correction ability. a plurality of filtering decoders that perform filtering, and a residual erasure estimation device that estimates residual error patterns that have not been completely corrected based on decoding information obtained when the filtering decoder performs decoding. and a residual erasure correction device that corrects the estimated error pattern by regarding it as erasure.