JPH0258815B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In a high-density magnetic recording device such as a digital VTR, code errors are likely to occur during reproduction, and therefore correction is performed using an error correction code. Furthermore, if there are many code errors, there is a possibility that the error correction itself will be performed incorrectly. For example, if a single error-correcting Hamming code is used as an error-correcting code, it is possible to correct one code error in one code word, but
If there are two or more code errors, there is a possibility that erroneous correction will be performed. Moreover, there is a problem in that after error correction is performed, it is impossible to determine whether or not an error correction has been made. To solve this problem, it is possible to improve the correction ability of the error correction code, but to do this, it is necessary to increase the number of check points in the error correction code, that is, the number of check bits, and as a result, the transmission efficiency It has the disadvantage that it decreases.

An object of the present invention is to add parity between each code word of an error correction code in an encoder, and to remove error correction by comparing the parity between code words after error correction with the received parity in a decoder. The purpose is to eliminate the above drawbacks.

Next, the principle of the present invention will be explained.

On the transmitting side, as shown in Figure 1, the code length is n+1.
One code block is constructed by using m (in the case of the figure, m=3) error correction codes W _i . Each code block has m error correction codes W ₁ to W _n and parity P _k between each code, where P _k = _n 〓 ⁱ⁼¹ W _ik (mod2), k = 0, 1,..., n (in the case of the same figure, P _i = ₃ 〓 ^j=1 W _ji (mod2)).

That is, in the figure, P ₀ =W ₁₀ +W ₂₀ +W ₃₀ (mod2). For example, the code constructed in this way is
Used for recording to VTR, etc.

FIG. 2 shows the received code after error correction and the subsequent error correction process.

On the receiving side, error correction processing is first performed, and the code word W _j ' with a code error (j = 3 in a of the same figure)
Remember. Then, the code after error correction
For W ₁ ′ to W _n ′ (m=3 in figure a), the parity between each code P _k ′ P _k ′= _n 〓 ⁱ⁼¹ W _ik ′ (mod2 ), k=0, 1, 2,...,
In other words, in the case of the same figure, find P ₀ ′=W ₁₀ ′+W ₂₀ ′+W ₃₀ ′ (mod2). Next, P _k ′ and received parity P _k are compared.

Here, if there is no error in the received parity P _k and if there is no erroneous correction in error correction, P _k and P _k ′ match.

On the other hand, if there is an error in error correction, the second
As shown in FIG. b, P _k and P _k ′ do not match in parity at the positions indicated by arrows. In this case, if there is only one previously stored code word W _j with a code error, the reception parity P _k of that code word is
If the code at the position where the code and the parity P _k ′ after error correction do not match, that is, the code of the hatched part of the code word W ₃ ′ as shown by the arrow in a in the same figure, is inverted, this code word errors (both code errors and errors due to miscorrection) are corrected.

Note that if there are multiple previously stored code words W _j with code errors, it is impossible to determine where the error correction occurred, so the code word with the code error has already been decoded. (in the case of a television signal, for example, the code of one line before). In this way, if an erroneous correction occurs during error correction, its influence can be removed.

Next, examples of the present invention will be described. Figure 3 shows an example of the configuration of the transmitting side, with an encoder 1 for error correction.
A correction code word W _i is created from the input code, and a parity P _k is determined for each code word W _i in the parity adding circuit 2. Then, the switch 3 selects the code word and parity to form one code block, which is sent out as a transmission code and recorded on, for example, a VTR.

The receiving side is constructed as shown in FIG. 4, and the error correction decoder 4 detects and corrects code errors in received codes from a VTR or the like. If a code word W _i with a code error exists, it is stored in the error code word display circuit 5. On the other hand, the error-corrected code obtained as the output of the error correction decoder 4 is applied to the parity check circuit 6, where the parity check circuit 6
Determine P _k ′ and receive parity P _k determined from the received code.
Compare with. If there is an erroneous code word in the error code word display circuit 5 and the parities P _k ' and P _k do not match in the parity check circuit 6, the error correction circuit 7 corrects the error. In this case, when there is only one error code word, correction is performed by inverting the code at the position where the parity does not match in the error code word. On the other hand, if a plurality of code words are mistaken, the error code word is replaced with the above-mentioned correction code.

Note that the parity code to be added may be limited to the information points of the error correction code, that is, the information bits. The reason for this is that in the received code, the effect of actual error correction is limited to the case where there is an error correction at an information point. Furthermore, television signals, etc.
Among bit PCM codes, there is a property that the image quality does not deteriorate much even if there is a code error in the lower 4 bits.Using this property, parity codes are applied only to the upper 4 bits of the information points. By using means that add
The number of bits to be added can be reduced. Moreover, any error correction code can be used as the error correction code used here.

In the present invention, the effect of error correction removal is large when there is only one code word with a code error in one code block. Therefore, if the number m of code words included in a code block is set in consideration of possible code errors so that the error is one code word, a large effect can be obtained.

As described above, according to the present invention, by adding a small amount of parity code, it is possible to remove error corrections that occur during error correction decoding, and the effect is significant.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the structure of a transmission code according to the present invention, FIG. 2a is an explanatory diagram also showing the structure of a reception code, and FIG. An explanatory diagram showing
FIGS. 3 and 4 are block diagrams showing embodiments of a transmitting section and a receiving section, respectively, of the present invention. 1... Encoder, 2... Parity addition circuit, 3...
...Switch, 4...Error correction decoder, 5...Error code word display circuit, 6...Parity check circuit, 7...
...Error correction circuit.

Claims (1)

[Claims] 1 A means for receiving a signal having a plurality of error correction codewords as one block and having parity added between the same digits of the plurality of error correction codewords, and an error correction code for each of the plurality of error correction codewords. an error correction means for correcting errors according to the rules of the above, a means for storing the position of a code word containing an error among the plurality of error correction code words, and a parity between the same digits of the code word from the error correction means. and if the two parities do not match, and the number of code words containing errors in a set of the same digits in the block is less than the correction ability of the parity, A decoding circuit comprising means for correcting errors in the code word and replacing the code word containing the error with a corrected code when the number of errors exceeds the correction capability.