JPS59131237A - Decoding circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION In high-density magnetic recording devices such as digital VTRs, code errors are likely to occur during reproduction, and therefore correction is performed using an error correction code. However, if there are many code errors,
There is a possibility that error correction itself is performed incorrectly. For example, when a single error correcting Hamming code is used as an error correcting code, it is possible to correct one code error in one code word, but it is possible to perform error correction if there are two or more code errors. There is sex. Moreover, there is a problem in that after error correction ψ is performed, it is impossible to determine whether or not there has been an error correction. To solve this problem, it is possible to improve the correction ability of the error correction code, but to do this, it is necessary to increase the number of check points in the error correction code, that is, the number of check bits, and as a result, the transmission efficiency It has the disadvantage that it decreases.

An object of the present invention is to add parity between each code word of an error correction code in an encoder, and to remove error correction by comparing the parity between code words after error correction and the received high IJ key in a decoder. By doing so, the above-mentioned drawbacks are eliminated.

Next, the principle of the present invention will be explained.

As shown in FIG. 1, on the transmitting side, one code block is constructed using m (m=3 in the figure) error correction codes Wi of code length n+1. Note that each code block includes m error correction codes W□ to 9 and parity P between each code.
k However, Pk = Σw, k (mod 2) + k 20 + 1 + = · + n = 1 (in the case of the same figure, p, = ΣW, l (mod 2)) j = 1.

That is, Po-W□ in the same figure. +W2o +W3o (mod 2). The code constructed in this way is used for recording on a VTR, for example.

FIG. 2 shows the received code after error correction and the subsequent error correction process.

On the receiving side, first, error correction processing is performed, and the code word Wj' (J=3 in FIG. 4A) containing a code error is stored. Next, the error-corrected codes W□′ to W1.
．． ′ (m=3 in FIG. 2(a)), as shown in FIG. 2(a), the parity between each code Pk′Pk′=ΣW,
ni' (mod 2), k = 0, 1, 2
+ -, n1==1 In other words, in the case of the same figure, Po'=W engineering. '+W2o'+W3o' (mod 2) is calculated. Next, /J/Pk/ is compared with the received parity Pk.

Here, if there is no error in the received harness Pl and if there is no erroneous correction in the error correction, Pk and Pk' match.

On the other hand, if there is an error correction in the error correction, as shown in Fig. 2(b)
As shown in the figure, Pk and P1' do not match in parity at the positions indicated by arrows. In this case, if the previously stored code word WI with the code error does not exist, the code word is received at a position where the parity P□ and the parity Pk' after error correction do not match. symbol, i.e. the same figure (
As shown by the arrows in a), by inverting the codes of the hatched portions of code word W3', errors in this code word (both code errors and errors due to erroneous correction) are corrected.

Note that if there are multiple previously stored code words W with code errors, it is impossible to determine where the error correction occurred, so the code word with the code error has already been stored in the decoder. Modification code (for television signals, for example 1
code before the line). In this way, if there is an erroneous correction during error correction, its influence can be removed.

Next, examples of the present invention will be described. FIG. 3 shows an example of the configuration on the transmitting side, in which an error correction encoder 1 creates a correction code word W from an input code, and a parity adding circuit 2 calculates a parity Pk for each code embryo.

Then, the switch 3 selects the code word and parity to form one code block and sends it out as a transmission code.
For example, it is recorded on a VTR.

The receiving side is constructed as shown in FIG. 4, and the received code from a VTR or the like undergoes code error detection and correction in an error correction post-encoder 4. If the code word W that contains a code error,
If it exists, it is stored in the error code word display circuit 5. On the other hand, the error-corrected code obtained as the output of the error correction decoder 4 is applied to a parity check circuit 6, where parity Pk' is calculated, and the received parity Pk calculated from the received code is
Compare with. There is an erroneous code word in the error code word display circuit 5, and the parity check circuit 6 detects the parity P.
If k/ and Pk do not match, the error correction circuit 7 performs error correction. In this case, the error code word is 1
If there is only one error code word, the code at the position where the parity does not match in the error code word is inverted and corrected. On the other hand, if a plurality of code words contain erroneous 1's, the erroneous code words are replaced with the above-mentioned correction code.

Note that the parity code to be added may be limited to the information points of the error correction code, that is, the information bits.

The reason for this is that in the received code, the effect of actual error correction is
This is because it is limited to cases where there is an erroneous correction in the information point. Furthermore, in television signals, etc., there is a property that the lower 4 bits of the 8-bit PCM code do not deteriorate the image quality significantly even if there is a code error. , for example, by adding a parity code only to the upper 4 bits,
The number of bits to be added can be reduced. Moreover, any error correction code can be used as the error correction code used here.

Note that in the present invention, the effect of error correction removal is large when there is only one code word with a code error in one code block. Therefore, considering the possible code errors,
If the number m of code words included in a code block is set so that the error is one code word, a large effect can be obtained.

As described above, according to the present invention, by adding a small amount of harrity code, it is possible to remove erroneous corrections that occur during error correction decoding, and the effect is significant.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the structure of a transmission code according to the present invention, FIG. 2(a) is an explanatory diagram also showing the structure of a passive code, and FIG. FIGS. 3 and 4 are block diagrams showing embodiments of the transmitter and receiver of the present invention, respectively. l... Encoder, 2... Parity addition circuit, 3...
switch, 4... error correction decoder, 5... error code word display circuit, 6... parity check circuit, 7... error correction circuit. spear f illustrator 2 fig.

Claims (1)

[Claims] The error correction code includes means for adding parity between code words, error correction means, means for determining parity between code words after error correction, and means for comparing the added parity and the parity after error correction. If the parities do not match in the parity comparison means, the added parity is used to correct the error again or replace it with a correction code, thereby preventing the error correction code from being erroneously corrected. decoding circuit.