JP2518827B2 - Encoding / decoding device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a coding / decoding device for error correcting code.

[Prior Art] In digital audio equipment, communication equipment, etc., an error correction code is used to correct an error occurring in a transmission path.

FIG. 3 is a diagram showing an example of the code configuration, and in the figure, “symbol” indicates 8-bit data. In this code structure, data arranged in 26 symbols in the x direction and 28 symbols in the y direction are doubly encoded by C ₁ code and C ₂ code. The C ₁ code is a Reed-Solomon code with an inter-code distance d = 5 by adding four P check symbols (P _{0 to} P ₃ ) to 28-symbol data in the y direction, and x = x ₁ of
The C ₁ code satisfies the following expression (1).

H ₁ [D (x ₁ , 0), D (x ₁ , 1) ... D (x ₁ , 27), P ₀ (x ₁ )
… P ₃ (x ₁ )] ^T = 0… (1) The C ₂ code is encoded in the x direction, and the code of y = y ₁ is an inter-code distance d to which 6 Q check symbols (Q _{0 to} Q ₅ ) satisfying the following expression (2) are added. = 7 is the Reed-Solomon code.

H ₂ [D (0, y ₁ ), D (1, y ₁ ) ... D (25, y ₁ ), Q ₀ (y ₁ ).
… Q ₅ (y ₁ )] ^T = 0… (2) FIG. 4 is a block diagram showing an encoding / decoding device for this code. In the figure, (100) is an encoding device, and (11
0) is a decoding device, (101) is a data input terminal, (102)
Is a C ₂ encoder, (103) is a C ₁ encoder, (104) is a C ₁ decoder,
(105) is a C ₂ decoder, (106) is a data output terminal, (10
7) is the data and check symbol output of the C ₁ decoder (104), (108) is a flag output indicating the correction state of the C ₁ decoder, and (109) is a transmission line or a recording medium.

In the encoding device, a Q check symbol is added to the data symbol input from the input terminal (101) in the C ₂ encoder (102) based on the equation (2), and then in the C ₁ encoder (103). The P check symbol is added based on the equation (1) to form the code shown in FIG.

In the decoding device (110), the C ₁ decoder (104) _first performs error correction or detection, and the C ₂ decoder (105) in the next stage performs C
Performing error correction using ₁ decoder (104) data from (107) flag (108).

The number of correctable errors E, the number of erasures N, and the inter-code distance d satisfy the following expression (3).

2E + N ≦ d−1 (3) Here, “error” refers to an error in which the position of the error symbol is unknown, and “erasure” refers to an error in which the position of the error symbol is known.

An example of C ₁ decoding and C ₂ decoding is shown below.

(1) C ₁ Decoding Using the received C ₁ code r = (r ₃₁ , r ₃₀ ... r ₀ ), the syndrome S = [S ₀ , S ₁ ,
S ₂ , S ₃ ] ^T is calculated.

If S = 0, the C ₁ flag is reset as “no error”, and if S ≠ 0, the C ₁ flag is set for all 32 symbols as “error exists”.

(2) C ₂ decoding An example will be described in which only erasure correction is performed.

From the equation (3), if the error E = 0, up to 7 erasures (N = 6) can be corrected. FIG. 5 is a diagram showing an example of the correction flow of the conventional apparatus, and the correction is performed in the following steps (1) to (3).

Syndrome calculation (301) Using the received C ₂ code B = [B ₃₁ , B ₃₀ ... B ₀ ] and the following equation (5), the syndrome S = [S ₀ , S ₁ , ... S ₅ ] ^T Ask for.

Syndrome judgment (310) If the syndrome S = 0, the flag is reset (307) as "no error" and the operation is ended.

 When S ≠ 0, the following correction operation is executed.

Correcting operation When the number of C ₁ flags N = 6, 6 erasure value calculations (302) are performed and correction (305) is performed.

Now, assuming that the location and the valley of the six erasures are α ₁ , α ₂ , ... α ₆ , e ₁ , e ₂ , ... e ₆ , respectively, the syndrome becomes the following equation (6).

By solving e ₁ to e ₅ using these 6 equations,
I want an erasure yavariu. The correction (305) operation is performed by adding the e _{1 to} e ₆ to the symbols indicated by the erasure locations α _{1 to} α ₆ .

When the C ₁ flag number N is 1 ≦ N ≦ 5, N erasure value calculations (303) are executed in the same manner as described above. In the case of 2 erasure, in equation (6), e ₃
The value with 0 for e ₆ is obtained as the syndrome. Since there are _two unknowns, e ₁ and e ₂ , we use S ₀ and S ₁ Is obtained as. At this time, since S _{2 to} S ′ ₅ are not used, they can be used for checking.

That is, from e ′ ₁ and e ′ ₂ obtained by the erasure value calculation (303), the following equation (8) is obtained. The check calculation (304) is performed, and the check determination (308) as to whether or not the following expression (9) S _i = S ′ _i (i = 2 to 5) (9) is satisfied is performed.

If the check result is check OK (when the expression (9) is satisfied), the correction (305) is executed with e as an error pattern, and if the check is NG (when the expression (9) is not satisfied), N is returned. C ₂ flags set (30
6) Then, the correction operation using the C ₂ flag is performed without performing the correction operation.

In this way, when 1 ≦ N ≦ 5, error rechecking is performed to prevent erroneous correction due to an error and improve reliability.

On the other hand, if N> 6 or N = 0, it cannot be corrected despite an error. Therefore, the C ₂ flag set (306) is performed and the operation is ended.

The above encoding can be performed using the flow of FIG. That is, at the time of encoding, since the check symbol location to be added is known, the check symbols P _{0 to} P ₃ and Q _{0 to} Q ₅ to be added are used as erasures according to the correction flow of FIG. By performing the erasure correction, the correct check symbol can be added. That is, at the time of C ₁ encoding, check symbols P _{0 to} P ₃ are added with N = 4, and at the time of C ₂ encoding,
The encoding shown in FIG. 3 is completed by adding the check symbols Q _{0 to} Q ₅ with N = 6.

[Problems to be Solved by the Invention] Since the conventional encoding / decoding device is configured as described above, N ≦ 6 at the time of encoding, and the check calculation (304) is performed even though there is no erroneous correction. And check judgment (3
Since 08) is performed, there is a problem that the processing time is long.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain an encoding / decoding device having a short processing time at the time of encoding.

[Means for Solving Problems] An encoding / decoding device according to the present invention includes a mode determination means for discriminating between an encoding mode and a decoding mode,
In the decoding mode, error check calculation and check determination are used together to correct the error, and in the coding mode, error check calculation and check determination are not performed and the error is corrected. is there.

[Operation] The mode determination means discriminates the operation mode of the encoding / decoding device. The encoding / decoding device corrects the discrimination result based on the result of the check determination when it is in the decoding mode, and corrects it without performing the check determination when it is in the encoding mode. .

Embodiment of the Invention FIG. 1 is a flow chart of an embodiment of the present invention. The flow of decoding in this embodiment is similar to that of FIG. 5, and therefore its explanation is omitted, and the difference in flow of encoding will be described below.

If S ≠ 0 in the syndrome determination (310), the encoding / decoding mode determination (RECMODE) (403) is performed,
Then, in the case of "encoding mode", C ₁ / C ₂ judgment (40
1) is performed, in the case of C ₁ mode as the N = 6 in the case of N = 4, C ₂ mode, Lee storage Yaba Reuse calculation (30
2) and (303) are performed. Then, when N = 4, the coding / decoding mode determination (RECMODE) (402) is performed, and in the "coding mode", the check calculation (304) and the check determination (308) are omitted. A correction (305) is performed by the erasure variable thus obtained, the correct check symbol is added, and the encoding is completed.

This operation shortens the processing time of the check calculation (304) and the check determination (308).

FIG. 2 is a diagram showing an example of a block circuit for executing the flow chart of FIG.

In the figure, (1) is the first memory, (2) is the control circuit of the first memory (1), (3) is the syndrome generation circuit, and (4) is the second location detecting means C ₁
Location detection circuit for flagged symbols,
(5) is a second memory, (6) is a ROM storing the location of the check symbol that constitutes the first location detecting means, (7) is a Galois field arithmetic circuit on GF (2 ⁿ ), (8) ) Is an exclusive OR gate, (9) is a register, (10) is the first data bus, (11) is a program counter, (12) is a program ROM storing the program of the operation flow, and (13) is a program. Decoder for decoding, (14) mode determination circuit for determining encoding / decoding mode, etc. (15) input terminal to which a mode selection signal indicating whether the mode is the encoding mode or the decoding mode is input , (16) is a decoding circuit, (17) is an input terminal to which a C ₁ / C ₂ selection signal for selecting C ₁ code and C ₂ code is input, and (18) is a second data bus. ing.

Next, the operation of this block circuit will be first described with reference to C ₂ decoding.
This will be described with reference to FIGS.

The reception data is controlled by the memory control circuit (2) from the first data bus (10) and written in the first memory (1). The syndromes S _{0 to} S ₅ are generated in the syndrome generation circuit (3) based on the received data stored in the first memory (1). On the other hand, the C ₁ flag added during C ₁ decoding is written in the first memory (1) and is read out again during C ₁ decoding. At this time, the location detection circuit (4) detects the location value α ^{m of the} symbol to which the C ₁ flag is added and the number N of C ₁ flags. The syndromes S _{0 to} S ₅ , the location α ^m, and the C ₁ flag number N are written in the second memory (5). The arithmetic circuit (7) performs basic operations such as multiplication, division, and addition and binary comparison, and based on the data in the second memory (5), via the second data bus (18). The erasure values e _{1 to} e ₆ are sequentially calculated and stored in the second memory (5), and the obtained erasure values are calculated.
The symbols e _{1 to} e ₆ are added to the symbols corresponding to the locations α _{1 to} α ₆ by the exclusive OR gate (8) to correct them. After the corrected symbol is latched in the register (9), it is written again in the first memory (1) via the first data bus (10) to complete the correction operation.

The control of each circuit based on the flow described above is performed by the program stored in the program ROM (12), and the program ROM (12) operates with the output of the program counter (11) starting from 0. The instruction is decoded by the program decoder (13) and its output signal (13
Each circuit is controlled by a). On the other hand, output signal (13b)
Is input to the mode decision circuit (14) and output signal (13c)
Is input to the parallel input of the program counter (11).
The jump of the program is executed by loading the value of the output signal (13c) into the counter (11) by the output signal (14a) of the mode determination circuit (14).

The coding / decoding judgments (402) and (403) and the C ₁ / C ₂ judgment (401) shown in FIG. 1 are mode judgments based on selection signals input from the input terminals (15) and (17). Circuits (14)
The mode is determined by and is performed by jumping the program counter (11). Check calculation (30
4) is performed by using the arithmetic circuit (7) and the second memory (5), and the check judgment (308) of the equation (9) compares S and S'in the comparison circuit in the arithmetic circuit (7). When they match, a match signal is output to the mode determination circuit (14). The mode determination circuit (14) receives the coincidence signal and jumps the program counter (11) to a predetermined program address.

The location of the check symbol at the time of encoding is stored in the ROM (6), and this is used as the erase location.

Although the above embodiment shows the encoding / decoding device by program control, it can be configured in the same way with dedicated hardware or a general-purpose microcomputer, and similar effects can be obtained.

Further, the mode determination (403) and the C ₁ / C ₂ determination (401) are not always necessary, and even without them, a correction flow having the same function can be configured.

In the above embodiment, the case where only the erasure correction is described as the decoding flow has been explained. However, even in the case of the error correction satisfying the expression (3) and the error correction in which the erasure and the error are mixed, the check is performed at the time of the decoding and the time of the encoding is performed. The same effect can be obtained by omitting the check.

In the above embodiment, the location of the check symbol at the time of encoding is stored in the ROM (6) and is used as the error location. However, instead of the ROM (6), it is input to the location detection circuit (4). The C ₁ flag may be forcibly set in the check symbol portion, and the location of this check symbol may be detected by the location detection circuit (4).

[Effects of the Invention] As described above, according to the present invention, the correction result is checked at the time of decoding by the coding / decoding device, and the result of the coding is not checked at the time of coding. Since it is configured, it is possible to obtain an encoding / decoding device in which the processing time at the time of encoding is shortened without lowering the reliability of error correction of the received signal.

[Brief description of drawings]

FIG. 1 is a flow chart showing an encoding / decoding process according to an embodiment of the present invention, FIG. 2 is a block circuit diagram showing an example of a circuit for executing this embodiment, and FIG. 3 is an example of an error correction code. FIG. 4 is a signal processing system diagram for explaining a coding / decoding procedure, and FIG. 5 is a flow chart showing a conventional coding / decoding process. (100) …… encoding device, (110) …… decoding device, (30
1) …… Syndrome calculation means, (302), (303) ……
Erasure value calculation means, (304) ... check calculation means, (305) ... correction means, (308) ... check determination means, (402), (403) ... mode determination means. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. At the time of encoding, a plurality of check symbols for error correction or detection are added based on a code structure defined for input data, and at the time of decoding, correction or detection of an error included in received data. A coding / decoding device for performing the above, wherein a syndrome generation means for generating a syndrome based on input data or received data, and a location of a check symbol to be added to input data in the case of encoding Location detection means for detecting and outputting the location of the error symbol in the data, error value calculation means for calculating an error pattern from the output values of the location detection means and the syndrome generation means, and a symbol corresponding to the location Correct based on the pattern calculated by the above value calculation means Correcting means, mode determining means for discriminating between the encoding mode and the decoding mode, whether the correction can be made from the calculated values of the location detecting means and the error value calculating means, and the syndrome from the syndrome generating means. A coding means for judging and executing a correcting means only when possible, and it is decided whether or not to execute the operation of the checking means according to the judgment result of the mode judging means. Decoding device. 2. The encoding / decoding apparatus according to claim 1, wherein the location detecting means includes a memory storing the location of the check symbol.