KR100239798B1 - Error correction method in the reproduction of digital signal and apparatus therefor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data error correction in digital signal reproduction, and more particularly, to an error correction method for correcting an error in data using a Reed-Solomon code and an apparatus applied thereto. In the error correction method for correcting an error of data using a Reed-Solomon code in the reproduction of a digital signal, the method comprising: calculating a syndrome from a received signal (step 400); Determining an error number using an error number determination equation based on the syndrome calculated in the syndrome calculation step (step 400); Performing error correction according to the number of errors determined in the error number determination step (402) (step 404); A status search step (406) of performing a status search of a system after performing the error correction step (404) or the number of errors determined in the error number determination step (402); And setting the plug to "0" or "1" by determining whether the state searched in the state search step (406) is good or the number of errors determined in the error number determination step (402) is greater than or equal to '3'. A C1 decoding process having a plug setting step (408), and a syndrome calculation step (500) for calculating a syndrome from the received signal; An error number determination step (502) of determining an error number using an error number determination equation by the seed calculated in the syndrome calculation step (500); If the number of errors determined in the error number determination step (502) is determined to be '2', it is determined whether the current error position matches the error position set in the plug setting step (408) of the C1 decoding process. Determining whether a plug is matched (step 504); If the number of errors determined in the error number determination step (502) through the error number determination step (502) and / or the plug match determination step (504) is '1' error correction is performed. An error correction step (506) of performing a “2” error correction when the location of the error detected in the plug matching determination step (504) and the location of the error set in the C1 decoding process coincide; An erasure correction determination step (508) of determining whether or not the error count determination step (502) determines whether the error is corrected when the number of currently detected errors exceeds '2'; A first plug determination step (510) of determining the number of plugs when the determination of the erasure correction determination step (508) is 'ON'; '3' / '4' erasure correction step for performing '3' / '4' erasure correction when the number of plugs determined in the first determination step (510) is '3' or '4' (Step 512); After the '3' or '4' eraser correction is performed in the '3' / '4' eraser correcting step (step 512), a checking step of performing checking to confirm whether the eraser correction is performed correctly. (Step 514); In the plug matching determination step (504) and / or the erasure correction determination step (508), the determination of the plug value determination step (504) is performed in the position of the currently detected error and the C1 decoding process. A second plug determination step (516) of determining the number of plugs when the position of the set error does not match or the determination of the eraser correction determination (508) is 'OFF'; And a plug setting step (518) for setting a plug after the syndrome calculation step (500) to the plug number second determination step (516) are performed.

Description

Error correction method in the reproduction of digital signal and apparatus therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data error correction in digital signal reproduction, and more particularly, to an error correction method for correcting an error in data using a Reed-Solomon code and an apparatus applied thereto.

In general, when transmitting or recording a digital signal, an error may occur in the data due to noise on the transmission system. In order to prevent such an error if possible, a check word is added when data is transmitted or recorded to correct the error data.

The code used for error correction in compact disc players is typically the Reed-Solomon code, which is a class of Non-binary BCH codes. Reed-Solomon code's ability can correct not only random error but also burst error. However, the disadvantage of using the Reed-Solomon code is that the Reed-Solomon code is a block-based code that uses the element of the finite field GF (2 ^m ) as a symbol, so unlike the binary BCH code, it is an error value. The decoding process is very complicated, such as the need to obtain an error value. In particular, the complexity of the system depends largely on the error correction capability, the size of the finite field, the type and number of finite field operations, and the time required for decoding also increases in proportion to the complexity of the system.

FIG. 1A illustrates a C1 decoding algorithm according to a plug processing method of error correction in the prior art.

Calculate the Syndrome (Step 100)

It is determined whether the number of errors is "0" with respect to the syndrome calculated in step 100 (step 102).

In step 102, if the number of errors is " 0 ", the plug is set to " 0 " (step 104).

In step 102, if the number of errors is not "0", it is determined whether the number of errors is "1" (step 106).

In step 106, if the number of errors is "1", 1 error correction is performed (step 108).

After 1 error correction is performed in step 108, the plug is set to " 0 " (step 104).

In step 106, if the number of errors is not "1", it is determined whether the number of errors is "2" (step 110).

In step 110, if the number of errors is "2", 2 error correction is performed (step 112).

In step 110, the number of errors is not "2", or after performing 2 error correction in step 112, the plug is set to "1" and ends (step 114).

FIG. 1B illustrates a C2 decoding algorithm according to a plug processing method of error correction in the prior art.

Calculate the Syndrome (Step 150)

It is determined whether the number of errors is "0" for the syndrome calculated in step 150 (step 152).

If the determination of step 152 is that the number of errors is "0", the plug is set to "0" and ends (step 154).

In step 152, if the number of errors is not "0", it is determined whether the number of errors is "1" (step 156).

In step 156, if the number of errors is "1," 1 error correction is performed.

After 1 error correction is performed in step 158, the plug is set to " 0 " (step 154).

In step 156, if the number of errors is not "1", it is determined whether the number of errors is "2" (step 160).

In step 160, if the number of errors is "2", the plug is checked.

If the checked result of step 162 is "good", 2 error correction is performed.

After performing 2 error corrections in step 164, the plug is set to " 0 " (step 154).

If the checked result of step 162 is "bad", it is determined whether the number of plugs is larger than "2" (step 166).

If the number of plugs is greater than "2" in step 166, the plug is copied and ends.

If the number of plugs is not greater than " 2 ", the determination of step 166 ends with the plug " 1 " (step 170).

The Reed-Solomon error correcting device used in the compact disc player device can correct up to 2 errors in the C1 code, and up to 4 erasures in the C2 code, but only up to 2 errors. If only 2 errors are corrected, if 8 or more burst errors occur as the number of codewords, error correction is not possible.However, if 4 errors are corrected, error correction is possible even if 16 errors occur consecutively. There is an advantage to doing this. However, when the maximum error correction is performed, the probability of miscorrection becomes very large if the 8/14 modulation data is incorrect or the player operation state is unstable.

Accordingly, an object of the present invention is to provide an error correction method having a decoding algorithm that is designed to improve the problems of the prior art, while exhibiting the maximum error correction capability and having a simpler structure.

Another object of the present invention is to provide an error correction apparatus applied to the error correction method of the above object.

1A is a diagram illustrating a C1 decoding algorithm according to a plug processing method of error correction in the prior art.

FIG. 1B illustrates a C2 decoding algorithm according to a plug processing method of error correction in the prior art.

2 is a block diagram of a syndrome generator of a general Reed-Solomon code according to the present invention.

3A is a schematic diagram of a device for implementing s ₀ of Equation 5 as a syndrome generator of a general Reed-Solomon code to which the present invention is applied.

FIG. 3b is a device diagram of s ₁ of Equation 5 as a syndrome generator of a general Reed-Solomon code to which the present invention is applied.

FIG. 3C is a schematic diagram of a device for implementing s ₂ of Equation 5 as a syndrome generator of a general Reed-Solomon code according to the present invention.

FIG. 3D is a device diagram implementing s ₃ of Equation 5 as a syndrome generator of a general Reed-Solomon code to which the present invention is applied.

4 is a flowchart of a C1 decoding algorithm as an error correction method according to the present invention.

5 is a flowchart of a C2 decoding algorithm as an error correction method according to the present invention.

6A to 6B are block diagrams of an error correction apparatus according to the present invention.

The error correction method of the present invention for achieving the above object is to calculate the syndrome in the error correction method for correcting the error of the data using the Reed-Solomon code in the reproduction of the digital signal Step (step 400); Determining an error number using an error number determination equation based on the syndrome calculated in the syndrome calculation step (step 400); Performing error correction according to the number of errors determined in the error number determination step (402) (step 404); A status search step (step 406) of performing a status search of a system after performing the error correction step (404) or the number of errors determined in the error number determination step (402); And the plug is determined to be "0" or "1" in the state retrieval step (406) to determine whether the retrieval state is good and the number of errors determined in the error number determination step (402) is greater than or equal to '3'. A C1 decoding process having a plug setting step (408) step of setting and a syndrome calculation step (step 500) of calculating a syndrome from a received signal; An error number determination step (502) of determining an error number using an error number determination equation by the syndrome calculated in the syndrome calculation step (500); If the number of errors determined in the error number determination step (502) is determined to be '2', it is determined whether the current error position matches the position of the error set in the plug setting step (408) of the C1 decoding process. Determining whether a plug is matched (step 504); If the number of errors determined in the error number determination step (502) through the error number determination step (502) and / or the plug match determination step (504) is '1' error correction is performed. An error correction step (506) of performing error correction if the location of the error detected in the plug matching determination step (504) and the location of the error set in the C1 decoding process match; An erasure correction determination step (508) of determining whether an error is corrected if the number of errors currently detected in the error number determination step (502) exceeds '2'; A first plug determination step (510) of determining the number of plugs when the determination of the erasure correction determination step (508) is 'ON'; If the number of plugs determined in the first determination step (510) is '3' or '4', the '3' / '4' eraser correction is performed by '3' / '4' erasure correction (512). step); After the '3' or '4' eraser correction is performed in the '3' / '4' eraser correcting step (step 512), a checking step of performing checking to confirm whether the eraser correction is performed correctly. The determination of the plug matching determination step (504) through the plug matching determination step (504) and / or the erasure correction determination step (508) is performed by the step (504). A second plug determination step (516) of determining the number of plugs when the position of the error set during the C1 decoding process does not match or the determination of the erasure correction step (508) is 'OFF'; And a plug setting step (step 518) of setting a plug after the plug number second determination step 516 is performed.

The syndrome when a single symbol error occurs in the syndrome calculation step 400 is

When the double symbol error occurs, the syndrome is

When the triple symbol error occurs, the syndrome is

The syndrome when a quadruple symbol error occurs

It is characterized by that.

The error number determination step (402)

This is called,

a) If no error occurs

b) when a single symbol error occurs

c) a double symbol error occurs

d) an error of more than three symbols occurs

Other than a), b) and c) above

As a result, the number of errors is determined.

The error number determination step (step 402) may include determining whether the error number is '0' (step 402-1); Determining whether the number of errors is '1' (step 402-2); And determining whether the error number is '2' (step 402-3).

In the error correcting step (404), if the number of errors determined in the error number determining step (402) is '0', error correction is not performed. If the determined number of errors is '1', '1' If error correction is performed (step 404-1), and if the number of the determined errors is '2', '2' error correction is performed (step 404-2), and the '1' error correction (step 404-1) is performed. The conduct of

이라 정의하면, 상기 다항식으로부터

으로 치환하면, 상기 다항식은 다음의 수학식 14와 같이 나타낼 수 있고,Performing the '2' error correction (step 404-2) is an error position polynomial having the error positions X1 and X2 in the case of a double symbol error occurrence.

In this definition, from the polynomial

When substituted with, the polynomial can be represented by the following equation (14),

이고,

) 또한, k의 트레이스(trace)인

를

와

로 구별하여 식을 쓰면(here,

ego,

) Is also a trace of k

To

Wow

If you write

와

는 각각 수학식 15와 16과 같이 나타낼 수 있으며,And taking the trace on the finite field GF (2 ⁸ ), m = 8,

Wow

Can be represented as in Equations 15 and 16, respectively.

이고,

이면, 수학식 14에서 표현된

의 두근

과

는 다음의 수학식 17과 같이 표현할 수 있는 바,From Equations 15 and 16

ego,

If is expressed in equation (14)

Pounding

and

Can be expressed as in Equation 17 below.

이나

가 되는 경우에는 다음의 수학식 18과 같이 표현할 수 있고,But

or

If it becomes can be expressed as the following equation (18),

이 되는

내의 한 원소이며

이라 할 때

을 만족시킴으로서 상기 수학식 18로 표현되는 두 근이 결정되는데, 상기 과정을 통하여 얻은

과

를 이용하여 에러 위치 X1, X2는 다음의 수학식 19와 같고, 에러값 Y1, Y2는 다음의 수학식 20과 같음을 특징으로 하고,Where y is

Being

Is an element within

When called

By satisfying the two roots represented by the equation (18) is determined, obtained through the process

and

The error positions X1 and X2 are represented by Equation 19 below, and the error values Y1 and Y2 are represented by Equation 20 below.

If the number of errors determined in the error correction step (404) is other than '0', '1', or '2', error correction is not performed.

The state search step (406) is a step of searching for system characteristics, data, and player status, and confirms whether there is an abnormality of EFM (Eight / Fourteen Modulation) data, a player operating state, a frame sync detection, etc. A step for variably adding a next plug,

STATUS FLAG C1 FLAG Set / Reset Frame Sync Detected Player operating state No error One error Two error reset (OK) reset (OK) reset reset reset / set reset (OK) set (NG) reset reset / set set set (NG) reset (OK) reset reset / set set set (NG) set (NG) reset / set set set

It is characterized by that.

The plug setting step (408) sets the plug to '0' if the detected state is good in the state searching step (406), and sets the plug to '1' if the detected state is not good, and the number of errors If the number of errors determined in the determination step (402) is greater than or equal to '3', the plug is directly set to '1' without going through the error correction step (404) and the status search step (406). It features.

The plug setting step (408) may include setting a plug to '0' (step 408-1) if the state found in the state searching step (406) is good; And the error correction step (404) when the status searched in the status search step (406) is not good or the number of errors determined in the error number determination step (402) is determined to be '3' or more. It is characterized in that it is subdivided into the step (408-2) of setting the plug directly to '1' without going through the state search step (406).

In the syndrome calculation step (500), a syndrome when a single symbol error occurs

When the double symbol error occurs, the syndrome is

When the triple symbol error occurs, the syndrome is

The syndrome when a quadruple symbol error occurs

It is characterized by that.

The error number determination step (502)

This is called,

a) If no error occurs

b) when a single symbol error occurs

c) a double symbol error occurs

d) an error of more than three symbols occurs

Other than a), b) and c) above

As a result, the number of errors is determined.

The error number determination step (step 502) may include determining whether the error number is '0' (step 502-1); Determining whether the number of errors is '1' (step 502-2); And determining whether the number of errors is '2' (step 502-3).

The error correction step (506) is a '1' error correction step (step 506-1) and the '2' error correction step (step 506-2), the '1' error correction step (506-1) The conduct of

이라 정의하면, 상기 다항식으로부터

으로 치환하면, 상기 다항식은 다음의 수학식 14와 같이 나타낼 수 있고,Performing the '2' error correction step (step 506-2), the error position polynomial having the error position X1, X2 in the case of a double symbol error occurrence

In this definition, from the polynomial

When substituted with, the polynomial can be represented by the following equation (14),

<Equation 14>

이고,

) 또한, k의 트레이스(trace)인

를

와

로 구별하여 식을 쓰면(here,

ego,

) Is also a trace of k

To

Wow

If you write

상에서 트레이스를 취하면 m=8이므로, 상기

와

는 각각 수학식 15와 16과 같이 나타낼 수 있으며,And finite body

Taking trace on m = 8, so

Wow

Can be represented as in Equations 15 and 16, respectively.

<Equation 15>

<Equation 16>

이고,

이면, 수학식 14에서 표현된

의 두근

과

는 다음의 수학식 17과 같이 표현할 수 있는 바,From Equations 15 and 16

ego,

If is expressed in equation (14)

Pounding

and

Can be expressed as in Equation 17 below.

<Equation 17>

이나

가 되는 경우에는 다음의 수학식 18과 같이 표현할 수 있고,But,

or

If it becomes can be expressed as the following equation (18),

<Equation 18>

이 되는

내의 한 원소이며

이라 할 때

을 만족시킴으로서 상기 수학식 18로 표현되는 두 근이 결정되는데, 상기 과정을 통하여 얻은

과

를 이용하여 에러 위치 X1, X2는 다음의 수학식 19와 같고, 에러값 Y1, Y2는 다음의 수학식 20과 같음을 특징으로 하고,Where y is

Being

Is an element within

When called

By satisfying the two roots represented by the equation (18) is determined, obtained through the process

and

The error positions X1 and X2 are represented by Equation 19 below, and the error values Y1 and Y2 are represented by Equation 20 below.

<Equation 19>

<Equation 20>

The determination of the erasure correction step (508) is as shown in the following table.

STATUS FLAG MICOM DATA Erasure Correction Frame Sync Detection Player operating state forced Erasure OFF reset (OK) reset (OK) reset ON reset (OK) set (NG) reset ON / OFF set (NG) reset (OK) reset ON / OFF set (NG) set (NG) reset ON / OFF don't care don't care set OFF

는 다음의 수학식 21과 같이 표현되고,In the '3' / '4' erasure correction step (step 512), the '3' erasure correction is a syndrome request.

Is expressed as in Equation 21 below,

In addition, the error position polynomial is represented by the following Equation 22,

는 다음의 수학식 23과 같이 표현할 수 있는 바,Coefficient of each order in Equation 22

Can be expressed as Equation 23 below.

를 이미 알고 있다고 가정하고 상기 수학식 21의 3원 일차 연립 방정식을 풀면 에러값 Y1, Y2, Y3는 다음의 수학식 24와 같고,Equation 22 becomes '0' if a triple symbol error occurs. Error location

Assuming that we already know the equation, solving the three-dimensional linear system of equations (21), the error values Y1, Y2, Y3 are equal to the following equation (24),

는 다음의 수학식 25와 같고,'4' eraser correction syndrome element

Is equal to the following Equation 25,

In addition, the error position polynomial is represented by the following Equation 26,

In Equation 26, the coefficient of each order is as shown in Equation 27 below.

를 이미 알고 있다고 가정하고 상기 수학식 25의 4원 일차 연립방정식을 풀면 에러값 Y1, Y2, Y3, Y4는 다음의 수학식 28과 같음을 특징으로 한다.Equation 26 becomes '0' if a quadruple symbol error occurs, and an error position

Suppose we already know the equation and solve the quadratic linear equations of Equation 25, the error values Y1, Y2, Y3, Y4 are characterized by the following Equation 28.

The plug setting step (step 518) includes plug '0' setting step (step 518-1), plug '1' setting step (step 518-2), plug 'copy' setting step (step 518-3) In the plug '0' setting step (step 518-1), the determination of the step (502-1) of determining whether the error number '0' of the error number determination step (502) is currently detected. If no error is detected, or if the error '1' or '2' is corrected in the '1' / '2' error correction step (step 506), or the result of the check in the check step (514) is satisfactory, In the step of setting the plug '1' (step 518-2), the number of plugs determined in the first determination step (510) of the plug number is '0', '1', '2'. Or the plug is set to '1' when the number of plugs determined in the checking step (514) is bad or the number of plugs determined in the second judging step 516 is '1' or '2'. In the plug 'copy' setting step (step 518-3), the number of plugs determined in the plug number first determination step (510) is '5', or the plug number second determination step (516). When the number of plugs determined in step 2 exceeds '2', the plug is set to 'copy'.

In addition, the apparatus for achieving the other object of the present invention

상의 임의의 원소

를 정수값

로 변환하는

변환기; 상기 데이터 버스에 접속되고, 정수값

를 유한체

상의 임의의 원소

로 변환하는

변환기; 상기 데이터 버스에 접속되고, C2부호 에러정정시 C2부호 데이터를 읽은 후 C1 플러그를 읽어들이는데 이때 C1 플러그의 개수를 계수화하는 C1 플러그 카운터; 상기 데이터 버스에 접속되고, 제로 데이터를 검출하여 개수를 측정 후 측정 개수를 출력하는 제로 카운터; 상기 데이터 버스에 접속되고, 부호 데이터 및 플러그 등을 입출력하는 입출력 레지스터; 상기 어드레스 발생기로부터 출력되는 일측의 출력신호와 상기

변환기로부터 출력되는 일측의 출력신호를 입력신호로 하여 에러정정 연산 도중에 발생된 에러의 위치를 정수값으로 저장하거나 상기 어드레스 발생기로부터 출력되는 이레이저의 위치를 정수값으로 저장하는 에러위치 저장 레지스터; 상기 어드레스 발생기로부터 출력된 및 상기 에러위치 저장 레지스터로부터 출력된 신호를 선택적으로 출력하는 제1신호선택기; 상기 데이터 버스에 접속되고, 유한체

상의 임의의 원소

를

혹은

표현으로 변환 출력하는 역원기; 상기 데이터 버스에 접속되고, 2중 심벌 에러정정에 사용되며 에러 위치 다항식

의 근을 구하는 트레이스 변환기; 상기 데이터 버스에 접속되어 8비트 내부 데이터 버스상의 데이터 혹은 상기 역원기로부터 출력되는 데이터를 선택적으로 출력하는 제2신호선택기; 상기 데이터 버스에 접속되어 8비트 내부 데이터 버스상의 데이터 혹은 상기 트레이스 변환기를 거친 데이터를 선택적으로 출력하는 제3신호선택기; 상기 제2신호선택기로부터 출력된 신호를 일시적으로 저장하는 MA레지스터; 상기 제3신호선택기로부터 출력되는 데이터를 일시적으로 저장하는 MB레지스터; 상기 데이터 버스에 접속되어 데이터를 일시적으로 저장하는 AB레지스터; 상기 데이터 버스에 접속되어 연산도중에 발생된 템포러리(Temporary) 데이터를 일시적으로 저장하는 TEMP레지스터; 상기 데이터 버스에 접속되어 부호 데이터로부터 신드롬 요소

를 구하는 신드롬 생성기; 상기 데이터 버스에 접속되고, 에러정정 처리 후 각 부호 데이터에 플러그 정보를 부가하거나 혹은 플러그 정보를 복사하는 C1/C2 플러그 생성기; 상기 데이터 버스에 접속되어 에러정정 연산 도중 발생된 중요 계수 데이터나 각종 근을 저장하는 RAM; 상기 MA레지스터로부터 출력된 신호와 상기 MB레지스터로부터 출력된 신호를 입력신호로 하여 유한체

상의 원소들을 곱하는 곱셈기; 및 상기 곱셈기로부터 출력된 신호와 상기 AB레지스터로부터 출력된 신호로 입력신호로 하여 유한체

상의 원소들을 더하는 덧셈기를 갖는 에러정정연산부를 포함한다.An error correction apparatus for correcting an error of data by using a Reed-Solomon code in reproduction of a digital signal, comprising: a program ROM in which an error correction decoding algorithm is coded and embedded; A program register for storing an instruction output from the program ROM; A program decoder configured to output a control signal according to a predetermined coding type from an instruction stored in the program register; Generates a control signal by determining whether to maintain a specific step or instruction for a certain period or branch to another step when correcting an error using the signal output from the program decoder and the signal output from the error correction operation unit as input signals. A jump controller; A program address counter that counts an address based on a signal output from the program register, a signal output from the program decoder, and a control signal output from the jump controller; And an error correction control unit having an operation control unit for generating an input / output control signal of code data necessary for error correction by the signal output from the program decoder, and a data bus for interfacing signals between components. An address generator for generating code data necessary for error correction and an address for reading / writing plugs; A finite body connected to the data bus

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To an integer value

Convert to

converter; An integer value connected to the data bus

To finite body

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Convert to

converter; A C1 plug counter connected to the data bus and reading the C1 plug after reading the C2 code data when correcting the C2 code error; A zero counter connected to the data bus and configured to detect zero data, measure a number, and output a measured number; An input / output register connected to the data bus to input and output code data, a plug, and the like; An output signal of one side output from the address generator and the

An error position storage register for storing, as an integer value, a position of an error generated during an error correction operation using an output signal of one side output from the converter as an integer value or storing the position of an eraser output from the address generator as an integer value; A first signal selector for selectively outputting a signal output from the address generator and output from the error position storage register; A finite body connected to the data bus

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To

or

An inverter for converting and outputting into a representation; Error location polynomial connected to the data bus and used for double symbol error correction

A trace converter for finding the root of the tracer; A second signal selector connected to the data bus and selectively outputting data on an 8-bit internal data bus or data output from the inverse generator; A third signal selector connected to the data bus and selectively outputting data on an 8-bit internal data bus or data passed through the trace converter; A MA register for temporarily storing a signal output from the second signal selector; An MB register for temporarily storing data output from the third signal selector; An AB register connected to the data bus to temporarily store data; A TEMP register connected to the data bus to temporarily store temporal data generated during a calculation; A syndrome element connected to the data bus from symbol data

A syndrome generator for obtaining a; A C1 / C2 plug generator connected to the data bus for adding plug information or copying plug information to each code data after an error correction process; A RAM connected to the data bus and storing important coefficient data or various roots generated during an error correction operation; Finite field using the signal output from the MA register and the signal output from the MB register as input signals

A multiplier for multiplying the elements of the phase; And a signal output from the multiplier and a signal output from the AB register as finite elements as input signals.

It includes an error correction operation unit having an adder for adding the elements of the phase.

The inverse generator is used when performing a division operation during an error correction operation.

The adder is composed of an exclusive-OR gate.

Hereinafter, preferred embodiments of the present invention will be described in detail.

In general, the decoding process of the Reed-Solomon code is concentrated in five steps as follows.

1) Calculate the syndrome from the receiving code.

2) Compute the error locator polynomial.

3) Calculate the error location number.

4) Calculate the error value.

5) Perform error correction.

If an error e (x) occurs during transmission when the transmission code c (x) is transmitted, the reception code r (x) may be expressed as Equation (1).

r (x) = c (x) + e (x)

상의 원시원(premitive element)이라 하면

은 생성다항식 g(x)의 근이 되고, 이근을 상기 수학식 1에 대입하면 다음의 수학식 2와 수학식 3과 같이 표현할 수 있다.a is a finite field

The primitive element

Is the root of the generated polynomial g (x), and can be expressed as Equation 2 and Equation 3 by substituting the root value in Equation 1 above.

The I-th syndrome element may be expressed as in Equation 4 below.

In practice, a double error correction (32, 28), (28, 24) Reed-Solomon code syndrome generator applied on a compact disc player is shown in FIG.

2 is a block diagram of a syndrome generator of a general Reed-Solomon code according to the present invention.

을 곱하여 가산기(204)로 출력한다.Referring to the configuration of FIG. 2, the received signal 200 r (x) and the signal output from the multiplier 202 are input to the adder 204, and the signal output from the adder 204 is flip-flop. A signal input from 206 and output from flip-flop 206 is input to multiplier 202, and a multiplier 202 outputs signal from flip-flop 206 and the root 208 of the generated polynomial.

Multiply by and output to the adder 204.

상의 임의의 원소

에

을 곱할 경우 다음의 수학식 5와 같이 표현된다.For example, finite

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on

When multiply by, it is expressed as Equation 5 below.

The apparatus for Equation 5 is configured as shown in Figs. 3a to 3d.

를 구현한 장치도이다.3A is a syndrome generator of a general Reed-Solomon code to which the present invention is applied.

This is also a device implementation.

을 구현한 장치도이다.Figure 3b is a syndrome generator of the general Reed-Solomon code to which the present invention is applied

This is also a device implementation.

를 구현한 장치도이다.3c is a syndrome generator of a general Reed-Solomon code to which the present invention is applied.

This is also a device implementation.

를 구현한 장치도이다.3d is a syndrome generator of a general Reed-Solomon code to which the present invention is applied.

This is also a device implementation.

An error occurring during the transmission is shown in Equation 6 below.

개의 오류가 발생한다면, 상기 수학식 6을 다음의 수학식 7과 같이 표현할 수 있다.Also, actually

If 6 errors occur, Equation 6 may be expressed as Equation 7 below.

는 수신부호에 생성 다항식의 근

을 대입하여 구해지고 각각의 신드롬요소는 다음의 수학식 8과 같다.Syndrome element defined by Equation 4

Is the root of the polynomial

Obtained by substituting for each syndrome element is shown in Equation (8).

를

라 하고 에러 위치 번호

를

라 하면 다음의 수학식 9와 같다.Error value in Equation 8

To

Error location number

To

In the following equation (9).

와

를 구하여 상기 수학식 7로 표현되는 에러 e(x)를 알아내는 것이 리드-솔로몬 부호를 이용하여 복호하는 과정을 말한다.From Equation 9

Wow

Finding the error e (x) represented by Equation 7 refers to a process of decoding using Reed-Solomon code.

Then, after calculating the error from the received signal, the error syndrome determination described next is performed.

인 경우 신드롬 요소는 상기 수학식 8로부터 다음의 수학식 10을 얻을 수 있다.Double error

In the case of the syndrome element, the following Equation 10 can be obtained from Equation 8.

Using Equation 10

와 같이 변형시켜 전개시키면 다음의 수학식 11과 같은 2차 방정식을 얻을 수 있다.

By transforming and developing as follows, a quadratic equation can be obtained as shown in Equation 11 below.

Each coefficient of Equation 11 is substituted as in Equation 12 below.

When substituted as in Equation 12, Equation 11 is expressed as follows.

By using this, it can be used as error count discrimination formula.

1) If no error occurs

2) Single symbol error occurs

3) In case of double symbol error

4) If an error of more than 3 symbols occurs

When other than 1), 2), 3) above

After determining the number of errors in 1), 2), 3), and 4), the error position and error value for the corresponding error should be determined.

* In case of single symbol error

이고, 에러위치와 에러값은 다음의 수학식 13과 같이 구한다.If a single error occurs, the syndrome

The error position and error value are obtained as in Equation 13.

* When double symbol error occurs

이라 정의한다. 상기 다항식으로부터

으로 치환하면, 다음의 수학식 14와 같이 나타낼 수 있고,In case of double symbol error, the error position polynomial with error positions X1 and X2

This is defined as. From the polynomial

If replaced with, the following equation (14),

<Equation 14>

이고,

이다. 그리고, k의 트레이스(trace)인

를

와

로 구별하여 식을 쓰면 다음과 같다.here,

ego,

to be. And k's trace

To

Wow

If you write the formula as follows:

상에서 트레이스를 취하면 m=8이므로,

와

는 각각 수학식 15와 16과 같이 나타낼 수 있으며,Finite body

If you take a trace on m = 8,

Wow

Can be represented as in Equations 15 and 16, respectively.

<Equation 15>

<Equation 16>

이고,

이면, 수학식 14에서 표현된

의 두근

과

는 다음의 수학식 17과 같이 표현할 수 있는 바,From Equations 15 and 16

ego,

If is expressed in equation (14)

Pounding

and

Can be expressed as in Equation 17 below.

<Equation 17>

이나

가 되는 경우에는 다음의 수학식 18과 같이 표현할 수 있다.But

or

When can be expressed as shown in Equation 18 below.

<Equation 18>

이 되는

내의 한 원소이며

이라 할 때

을 만족시킴으로서 상기 수학식 18로 표현되는 두 근이 결정된다.Where y is

Being

Is an element within

When called

By satisfying the two roots represented by the equation (18) is determined.

를 이용하여 k의 값을 구한 다음 k값을 롬(Read Only Memory;ROM)의 어드레스 입력으로 넣어 미리 계산된 두 근 중의 하나인

을 바로 ROM의 출력으로 얻어 구할 수 있다. 다음의 표 1에 (32,28) 리드-솔로몬 부호인 경우의 k값의 예를 들어 보면 다음과 같다.In addition to calculating the two roots by calculating like this

Find the value of k by using and insert the value of k into the address input of ROM (Read Only Memory; ROM).

Can be obtained directly from the ROM output. Table 1 below shows an example of the value of k in the case of the (32,28) Reed-Solomon code.

Table 1 below is a trace conversion table for finding the root of Equation 14.

k x 10 11101001 10000111 10000101 11001001 10001110 10001111 10101001 110 11 11000000 1110100 10010100 1010100 100110 100110 11010010 1110010 11011110 10110100 11000010 10011101 1011110 11100101 10001001 10101010 11110 11000000 11011111 1100010 11000111 10100000 11011010 1011110 1001111 11011101 10000100 10111011 10101 11010011 1001001 11011111 10010010 1010110 11010101 10100111 11011011 10001001 1000001 11110011 11001000 1011001 11011101 10001010 1010011 11110100 1001 11111010 11001011 1100111 10110 11101100

The technical relationship showing the k value for x in Table 1 is disclosed in detail in Korean Patent Application No. 90-21950 (Applicant Samsung Electronics), which is already filed, and thus description thereof will be omitted.

과

를 이용하여 에러 위치 X1, X2를 다음의 수학식 19와 같이 나타낼 수 있다.If the value of k is outside the range shown in Table 1, the error is treated as three or more errors. Obtained through the above process

and

The error positions X1 and X2 can be expressed by Equation 19 below.

<Equation 19>

In addition, the error values Y1 and Y2 may be represented by Equation 20 below.

<Equation 20>

* In case of triple symbol error

는 다음의 수학식 21과 같이 표현된다.Syndrome element if a triple symbol error occurs

Is expressed by Equation 21 below.

<Equation 21>

The error position polynomial is represented by the following equation (22).

<Equation 22>

는 다음의 수학식 23과 같이 표현할 수 있다.Coefficient of each order in Equation 22

Can be expressed as Equation 23 below.

<Equation 23>

를 이미 알고 있다고 가정하고 상기 수학식 21의 3원 일차 연립 방정식을 풀면 에러값 Y1, Y2, Y3는 다음의 수학식 24와 같다.Equation 22 becomes '0' if a triple symbol error occurs. Error location

Suppose we already know, and solve the ternary first-order simultaneous equation of Equation 21, the error values Y1, Y2, Y3 are given by Equation 24 below.

<Equation 24>

* In case of quadruple symbol error

는 다음의 수학식 25와 같다.Syndrome element if a quad symbol error occurs

Is as shown in Equation 25 below.

<Equation 25>

In addition, the error position polynomial is represented by Equation 26 below.

<Equation 26>

In Equation 26, the coefficient of each order is expressed by Equation 27 below.

<Equation 27>

Equation 26 becomes '0' if a quadruple symbol error occurs.

를 이미 알고 있다고 가정하고 상기 수학식 25의 4원 일차 연립방정식을 풀면 에러값 Y1, Y2, Y3, Y4는 다음의 수학식 28과 같다.Error location

Suppose we already know the equation and solve the quadratic first-order system of equation 25, and the error values Y1, Y2, Y3, Y4 are given by

<Equation 28>

The Reed-Solomon code can be decoded according to the error correction method described so far, and the error correction code used in digital devices is CIRC (Cross Interleaved Reed-Solomon Code) and consists of two types of codes: C1 and C2 . That is, the error correction decoding process is divided into two stages.

까지 에러정정이 가능하며, 이레이저(erasure) 정정인 경우

까지 에러정정이 가능하다. 여기서, t는 에러정정 능력을 말한다.If the minimum distance of the C1 and C2 codes is assumed to be 5, in case of error correction,

Error correction is possible up to the case of erasure

Error correction is possible. Where t is the error correction capability.

The decoding sequence used in the algorithm of the present invention performs C1 error correction using C1 code, and then performs C2 error / eraser correction using C2 code and C1 plug information. This will be described with reference to the drawings.

4 is a flowchart of a C1 decoding algorithm as an error correction method according to the present invention.

First, a syndrome is calculated from the received signal (step 400).

The number of errors is determined using an error number discrimination equation based on the syndrome calculated in step 400 (step 402).

The syndrome when a single symbol error occurs

to be.

In addition, the syndrome when a double symbol error occurs is shown in Equation (10). The syndrome when a triple symbol error occurs is represented by Equation 21 above. The syndrome when a quadruple symbol error occurs is shown in Equation 25 above.

An example of determining the number of errors in Equations 10 to 12 has already been described.

In the case where there is no error, a single error occurs, a double error occurs, and a triple or more error occurs, the description of the discrimination equation is as described above.

That is, in FIG. 4, determining whether the error number is '0' (step 402-1), determining whether the error number is '1' (step 402-2), and determining whether the error number is '2' ( Step 402-3) is determined by the above discriminant.

Error correction is performed according to the number of errors determined in step 402 (step 404).

If the number of errors determined in step 402 is '0', error correction is not performed. If the determined number of errors is '1', error correction is performed (step 404-1). If the number of determined errors is '2', '2' error correction is performed. step)

'1' error correction (step 404-1) is as described above in Equation (13). In addition, if the determined number of errors is '2', '2' error correction is performed (step 404-2).

'1' error correction (step 404-1) is as described above in Equation (13). In addition, the '2' error correction (step 404-2) is the same as already described in the equations (14) to (20). In addition, if the number of errors determined in step 404 is other than '0', '1', or '2', error correction is not performed.

The number of errors determined in the error count determination step (402) is '0' or the state search is performed after the error correction step (404).

The status search step (406) is a step for searching for system characteristics, data, and player status. That is, after checking whether there is an abnormality of EFM (Eight / Fourteen Modulation) data, a player operation state, a frame sync detection, etc., it is a step for variably adding a plug.

The explanation on the abnormality of EFM data is as follows.

가지의 채널 데이터중

가지의 채널 데이터만 변환한다. 나머지 16384-256=16128가지의 데이터는 불필요한 데이터이다. 만일 이러한 불필요한 데이터가 디스크로부터 입력된다면 정상적인 8비트 데이터로 복조될 수 없다. 이때 EFM 데이터 이상 유무 상태 플러그를 셋(set) 시킨다. 마찬가지로, 한 프레임(frame)의 시작 혹은 끝을 지시하는 프레임 싱크 데이터를 7.35㎑(=136㎲)마다 검출하지 못하면 해당 프레임분의 데이터가 이상이 있을 가능성이 크므로 프레임 싱크 검출유무 상태 플러그를 셋시킨다. 플레이어 동작 상태는 정상 동작과 비정상 동작으로 구분되는데 비정상적으로 플레이어가 동작할 때 플레이어 상태 플레그를 셋시킨다. 정상 상태란 노말(normal) 플레이 상태를 의미하며 비정상 상태는 패스트 포워드(fast forward), 리뷰(review), 서치(search) 등의 상태를 의미한다. C1 디코딩에서 사용되는 상태(STATUS)와 그때 부가되는 C1 플러그는 다음의 표 2와 같다.The 14-bit channel data input from the disc is demodulated into 8 bits.

Of channel data

Convert only channel data. The remaining 16384-256 = 16128 data are unnecessary data. If such unnecessary data is input from the disc, it cannot be demodulated into normal 8-bit data. At this time, the plug of EFM data status is set. Similarly, if frame sync data indicating the start or end of one frame is not detected every 7.35 ms (= 136 ms), the data for the corresponding frame is likely to be abnormal, so set the frame sync detection status plug. Let's do it. The player action state is divided into normal action and abnormal action. When the player operates abnormally, the player state flag is set. The normal state refers to a normal play state, and the abnormal state refers to states such as fast forward, review, and search. STATUS used in C1 decoding and the C1 plug added at that time are shown in Table 2 below.

STATUS FLAG C1 FLAG Set / Reset Frame Sync Detected Player operating state No error One error Two error reset (OK) reset (OK) reset reset reset / set reset (OK) set (NG) reset reset / set set set (NG) reset (OK) reset reset / set set set (NG) set (NG) reset / set set set

In addition, as shown in the case of "reset / set" in Table 2, setting two situations simultaneously means that the characteristics of the system and various application circuits may vary.

The plug is set to "0" or "1" by determining whether the state searched in the state search step (406) is good or the number of errors determined in the error number determination step (402) is greater than or equal to '3'. (Step 408)

The plug is set to '0' if the state found in the state searching step 406 is good (step 408-1). On the other hand, the state found in the state searching step 406 is not good or the error is detected. If the number of errors determined in the number determination step (402) is determined to be '3' or more, the plug is directly set to '1' without going through the error correction step (404) and the status search step (406). (Step 408-2)

5 is a flowchart of a C2 decoding algorithm as an error correction method according to the present invention.

First, a syndrome is calculated from the received signal (step 500).

The number of errors is determined using an error number discrimination equation by the syndrome calculated in the syndrome calculation step (step 500).

As shown in FIG. 4, the syndrome of occurrence of a single symbol error is

to be.

In addition, the syndrome when a double symbol error occurs is shown in Equation (10). The syndrome when a triple symbol error occurs is represented by Equation 21 above. The syndrome when a quadruple symbol error occurs is shown in Equation 25 above.

An example of determining the number of errors in Equations 10 to 12 has already been described.

In the case where there is no error, a single error occurs, a double error occurs, and a description of the discrimination equation for determining the case where a double error or more occurs has been described above.

That is, the step of determining whether the error number '0' (step 502-1), the step of determining whether the error number '1' (step 502-2), the step of determining whether or not the error number '2' in FIG. Step 502-3) is determined by the discriminant.

If the determination of the number of errors in step 502 determines whether the number of errors is '2' (step 502-3), and the number of errors is determined to be '2', the current error position is determined by the plug set in the C1 decoding algorithm. In operation 504, it is determined whether the error position coincides with the set error position.

If the number of errors determined in the error number determination step (502) through the error number determination step (502) and / or the plug match determination step (504) is '1' error correction is performed. In step 504, if the position of the currently detected error and the position of the error set by the C1 decoding algorithm coincide with each other, the operation of determining whether the plug is determined to be matched (step 504) is performed.

The '1' / '2' error correction step (step 506) is divided into an '1' error correction step (step 506-1) and a '2' error correction step (step 506-2). An error correction step 506-1 is performed as described in Equation 13 above. In addition, the '2' error correction step (step 506-2) is performed as described in equations (14) to (20).

The determination of the step (502-3) of the error number determination step (502) determines whether the error is corrected if the number of detected errors is not '2'. 508 steps)

The determination of the erasure correction step (508) is described in detail in Table 3 below.

STATUS FLAG MICOM DATA Erasure Correction Frame sync detection married Player operating state forced Erasure OFF reset (OK) reset (OK) reset ON reset (OK) set (NG) reset ON / OFF set (NG) reset (OK) reset ON / OFF set (NG) set (NG) reset ON / OFF don't care don't care set OFF

As shown in Table 2, the selective setting of two states of ON or OFF ("ON / OFF") also in Table 3 means that the characteristics of the system and various application circuits may vary.

If the determination of the erasure correction step 508 is 'ON' according to Table 3, the number of plugs is determined.

If the number of plugs determined in the first determination step (510) is '3' or '4', the '3' / '4' erasure correction is performed (step 512).

In the '3' / '4' erasure correction step (step 512), the '3' erasure correction is performed as described in Equations 21 to 24 above. In addition, the '4' erasure correction is performed as described in Equations 25 to 28.

After the '3' or '4' erasure correction is performed in the '3' / '4' erasure correction step (step 512), a check is performed to confirm whether the erasure correction is correctly performed. Step 514)

The determination of the plug matching determination step (504) through the plug matching determination step (504) and / or the erasure correction determination step (508) is performed in the position of the currently detected error and the C1 decoding algorithm. If the position of the set error does not match or the determination of the eraser correction determination step 508 is 'OFF' according to Table 3, the number of plugs is determined (step 516).

The plug is set after the syndrome calculation step (500) to the plug number second determination step (516) is performed (step 518).

The plug setting step (step 518) includes plug '0' setting step (step 518-1), plug '1' setting step (step 518-2), plug 'copy' setting step (step 518-3) Separated by.

In the plug '0' setting step (step 518-1), the determination of the step (502-1) of determining whether the error number '0' in the error number determination step (502) does not include an error currently detected; When the error '1' or '2' is corrected in the '1' / '2' error correction step (step 506) or the result of the check in the check step (514) is satisfactory, the plug is changed to '0'. Set it.

In the plug '1' setting step (518-2), the number of plugs determined in the plug number first determination step (510) is '0', '1', or '2', or the checking step (514). The plug is set to '1' when the result checked in step) is bad or the number of plugs determined in the plug determination second determination step 516 is '1' or '2'.

In the plug 'copy' setting step (step 518-3), the number of plugs determined in the plug number first determination step (510) is '5', or the plug number is determined in the second determination step 516. When the number of plugs plugged exceeds '2', 'plug' is set.

Now, an error correction apparatus for achieving another object of the present invention will be described.

6A to 6B are block diagrams of an error correction apparatus according to the present invention.

In particular, FIG. 6A is a block diagram of an error correction control unit of the error correction apparatus according to the present invention, and FIG. 6B is a block diagram of an error correction operation unit.

First, the error correction control unit illustrated in FIG. 6A uses a program ROM 600, a program register 6020 having an output signal of the program ROM 600 as an input signal, and an output signal of the program register 6020 as an input signal. A jump control unit 606 and the jump control unit 606 that use an output signal of one side of the program decoder 604, an output signal of the program decoder 604, and an output signal of an error correction operation unit as shown in FIG. 6B. A program address counter 608 that takes an output signal of the program register 602, an output signal of the program register 602, and another output signal of the program decoder 604, and an output signal of the program decoder 604 as an input signal. And an arithmetic control unit 610 for outputting to an error correction operation unit (FIG. 6B).

변환기(652),

변환기(654), C1 플러그 카운터(656), 제로 카운터(658), 입출력(i/o) 레지스터(660), 에러위치 저장 레지스터(662), 제1신호선택기(664), 역원기(666), 트레이(trace) 변환기(668), 제2신호선택기(670), 제3신호선택기(672), MA 레지스터(674), MB 레지스터(676), AB 레지스터(678), TEMP 레지스터(680), 신드롬 생성기(682), C1/C2 플러그 발생기(684), RAM(686), 곱셈기(688), 덧셈기(690), 및 데이터 버스(data bus)로 구성된다.On the other hand, the error correction operation unit shown in Figure 6b, the address generator 650,

Converter 652,

Converter 654, C1 plug counter 656, zero counter 658, input / output (i / o) register 660, error position storage register 662, first signal selector 664, invertor 666 , Tray converter 668, second signal selector 670, third signal selector 672, MA register 674, MB register 676, AB register 678, TEMP register 680, It consists of a syndrome generator 682, a C1 / C2 plug generator 684, a RAM 686, a multiplier 688, an adder 690, and a data bus.

Next, a description will be given of the mutual organic operation between the components constituting the error correction control unit and the error correction operation unit shown in FIGS. 6A and 6B.

The error correction control unit as shown in FIG. 6A generates a control signal such that the error correction function is performed according to the flow of the algorithm as described with reference to FIGS. 4 and 5. The program ROM 600 includes a coded error correction decoding algorithm. That is, the C1 and C2 decoding algorithms described with reference to FIGS. 4 and 5 are coded and embedded. The program register 602 stores instructions output from the program ROM 600. The program decoder 604 outputs a control signal for the instructions stored in the program register 602 according to a predetermined coding format. The jump controller 606 uses a signal output from the program decoder 604 and a signal output from the error correction operator shown in FIG. 6B as input signals to maintain a specific step or instruction for a predetermined period during error correction. Or, it determines whether to branch to another step and generates a control signal suitable for the situation at that time. The program address counter 608 counts an address by a signal output from the program register 602, a signal output from the program decoder 604, and a control signal output from the jump controller 606. counting). The operation controller 610 generates an input / output control signal of code data necessary for error correction by the signal output from the program decoder 604.

변환기(652)는 데이터 버스(692)에 접속되고, 유한체

상의 임의의 원소

를 정수값(i)로 변환한다. 상기

변환기(652)에서 변환된 정수들은 에러위치 저장 레지스트(662)로 출력된다.

변환기(654)는 데이터 버스(692)에 접속되고, 정수값(i)를 유한체

상의 임의의 원소

로 변환한다. 이들 임의의 원소들은 에러정정 연산에 사용된다. C1 플러그 카운터(656)는 데이터버스(692)에 접속되고, C2 부호 에러정정시 C2 부호 데이터를 읽은 후 C1 플러그를 읽어들이는데 이때 C1 플러그의 개수를 계수화한다. 제로 카운터(658)는 데이터버스(692)에 접속되고, 제로 데이터를 검출하여 개수를 측정 후 측정 개수를 출력한다. 입출력 레지스터(660)는 데이터 버스(692)에 접속되고, 부호 데이터 및 플러그 등을 입출력할 때 사용되는 인터페이스 회로이다. 에러위치 저장 레지스터(662)는 상기 어드레스 발생기(650)로부터 출력되는 일측의 출력신호외 상기

변환기(652)로부터 출력되는 일측의 출력신호를 입력신호로 하여 에러정정 연산 도중에 발생된 에러의 위치를 정수값으로 저장하거나 상기 어드레스 발생기(650)로부터 출력되는 이레이저의 위치를 정수값으로 저장한다. 제1신호선택기(664)는 상기 어드레스 발생기(650)로부터 출력된 및 상기 에러위치 저장 레지스터(662)로부터 출력된 신호를 선택적으로 출력한다. 역원기(666)는 데이터 버스(692)에 접속되고 유한체

상의 임의의 원소

를

혹은

표현으로 변환 출력한다. 역원기(666)는 에러정정 연산중 나눗셈 연산을 수행할 때 사용된다. 트레이스 변환기(668)는 데이터 버스(692)에 접속되고, 2중 심벌 에러정정에 사용되며 에러위치 다항식

의 근을 구한다. 이에 대한 변환표는 상기 표 1에서 이미 설명한 바와 같이 수행한다. 제2신호선택기(670)는 데이터 버스(692)에 접속되어 8비트 내부 데이터 버스상의 데이터 혹은 상기 역원기(666)로부터 출력되는 데이터를 선택적으로 출력한다. 제3신호선택기(672)는 데이터버스(692)에 접속되어 8비트 내부 데이터 버스상의 데이터 혹은 상기 트레이스 변환기(668)를 거친 데이터를 선택적으로 출력한다. MA 레지스터(674)는 상기 제2신호선택기(670)로부터 출력된 신호를 일시적으로 저장한다. MB 레지스터(676)는 상기 제3신호선택기(672)로부터 출력되는 데이터를 일시적으로 저장한다. AB 레지스터(678)는 데이터 버스(692)에 접속되어 데이터를 일시적으로 저장한다. TEMP 레지스터(680)는 데이터 버스(692)에 접속되어 연산도중에 발생된 템포러리(Temporary) 데이터를 일시적으로 저장한다. 신드롬 생성기(682)는 데이터 버스(692)에 접속되어 부호 데이터로부터 신드롬 요소

를 구하는 회로이며

내지

까지 구하는 실시예를 상기 도 3a 내지 도 3d에서 보인 바 있다. C1/C2 플러그 생성기(684)는 데이터버스(692)에 접속되고, 에러정정 처리 후 각 부호 데이터에 플러그 정보를 부가하거나 혹은 플러그 정보를 복사한다. RAM(686)은 데이터 버스(6920)에 접속되어 에러정정 연산 도중 발생된 중요 계수 데이터나 각종 근을 저장한다. 곱셈기(688)는 상기 MA, 레지스터(674)로부터 출력된 신호와 상기 MB 레지스터(676)로부터 출력된 신호를 입력신호로 하여 유한체

상의 원소들을 곱한다. 덧셈기(690)는 상기 곱셈기(688)로부터 출력된 신호와 상기 AB 레지스터(678)로부터 출력된 신호를 입력신호로 하여 유한체

상의 원소들을 더한다. 상기 덧셈기(690)는 익스클루시브-오아(Exclusive-OR) 게이트로 구성된다.On the other hand, the error correction operation unit as shown in Fig. 6b generates an operation process for error correction and an address necessary for reading / writing the sign data and the C1 / C2 plug. The address generator 650 generates an address that uses code data and plugs necessary for error correction during read / write. The sign data refers to C1 data and C2 data. In addition, a plug refers to a C1 plug and a C2 plug.

Converter 652 is connected to data bus 692 and is a finite field

Elements on Pinterest

Is converted to an integer value (i). remind

The integers converted by the converter 652 are output to the error location storage register 662.

The converter 654 is connected to the data bus 692 and is a finite field of integer value i.

Elements on Pinterest

Convert to These arbitrary elements are used for error correction operations. The C1 plug counter 656 is connected to the data bus 692. When the C2 code error is corrected, the C1 plug counter 656 reads the C1 plug and then counts the number of C1 plugs. The zero counter 658 is connected to the data bus 692, detects zero data, measures the number, and outputs the measured number. The input / output register 660 is an interface circuit connected to the data bus 692 and used for inputting and outputting sign data, plugs, and the like. The error position storing register 662 may be output from one side of the output signal output from the address generator 650.

Using the output signal of one side output from the converter 652 as an input signal, the position of the error generated during the error correction operation is stored as an integer value, or the position of the eraser output from the address generator 650 is stored as an integer value. The first signal selector 664 selectively outputs a signal output from the address generator 650 and output from the error location storage register 662. Inverter 666 is connected to data bus 692 and is a finite field

Elements on Pinterest

To

or

Convert to output the output. The inverter 666 is used to perform the division operation during the error correction operation. Trace converter 668 is connected to data bus 692 and is used for double symbol error correction and error location polynomials.

Find the root of. The conversion table for this is performed as already described in Table 1 above. The second signal selector 670 is connected to the data bus 692 and selectively outputs data on the 8-bit internal data bus or data output from the inverter 666. The third signal selector 672 is connected to the data bus 692 and selectively outputs data on an 8-bit internal data bus or data passed through the trace converter 668. The MA register 674 temporarily stores the signal output from the second signal selector 670. The MB register 676 temporarily stores data output from the third signal selector 672. The AB register 678 is connected to the data bus 692 to temporarily store data. The TEMP register 680 is connected to the data bus 692 to temporarily store temporary data generated during the operation. The syndrome generator 682 is connected to the data bus 692 to allow syndrome elements from the sign data.

Is a circuit to find

To

An embodiment obtained until has been shown in Figures 3a to 3d. The C1 / C2 plug generator 684 is connected to the data bus 692, adds plug information to each code data or copies the plug information after error correction processing. The RAM 686 is connected to the data bus 6920 to store important coefficient data or various roots generated during the error correction operation. The multiplier 688 uses a signal output from the MA and the register 674 and a signal output from the MB register 676 as input signals.

Multiply the elements of the phases. The adder 690 uses a signal output from the multiplier 688 and a signal output from the AB register 678 as input signals.

Add the elements of the phase. The adder 690 is configured with an Exclusive-OR gate.

According to the present invention as described above has the following effects.

The Reed-Solomon error correction device used in the conventional digital A / V (Audio / Video) device corrects up to 2 errors in the C1 code, and up to 4 erasers in the C2 code, but only up to 2 errors. If only 2 errors are corrected If 8 or more burst errors occur as the number of code words, error correction cannot be performed. However, if 4 erasure correction is performed as in the present invention, up to 16 code words can be used continuously. Even if the error occurs, the error correction can be performed.

Claims (11)

An error correction method for correcting an error of data by using a Reed-Solomon code in reproduction of a digital signal, Calculating a syndrome from the received signal (step 400); Determining an error number using an error number determination equation based on the syndrome calculated in the syndrome calculation step (step 400); Performing error correction according to the number of errors determined in the error number determination step (402) (step 404); A status search step (406) of performing a status search of a system after performing the error correction step (404) or the number of errors determined in the error number determination step (402); And The plug is set to "0" or "1" by determining that the status searched in the status search step (406) is good or the number of errors determined in the error number determination step (402) is greater than or equal to '3'. C1 decoding process with plug setting step (408) And, A syndrome calculation step (500) of calculating a syndrome from the received signal; An error number determination step (502) of determining an error number using an error number determination equation by the syndrome calculated in the syndrome calculation step (500); If the number of errors determined in the error number determination step (502) is determined to be '2', it is determined whether the current error position matches the error position set in the plug setting step (408) of the C1 decoding process. Determining whether a plug is matched (step 504); If the number of errors determined in the error number determination step (502) through the error number determination step (502) and / or the plug match determination step (504) is '1' error correction is performed. An error correction step (506) of performing a “2” error correction when the location of the error detected in the plug matching determination step (504) and the location of the error set in the C1 decoding process coincide; An erasure correction determination step (508) of determining whether the error number determination step (502) determines whether or not the eraser is corrected when the number of currently detected errors exceeds '2'; A first plug determination step (510) of determining the number of plugs when the determination of the erasure correction (step 508) is 'ON'; '3' / '4' erasure correction step for performing '3' / '4' erasure correction when the number of plugs determined in the first determination step (510) is '3' or '4' (Step 512); After the '3' or '4' eraser correction is performed in the '3' / '4' eraser correcting step (step 512), a checking step of performing checking to confirm whether the eraser correction is performed correctly. (Step 514); In the plug matching determination step (504) and / or the erasure correction determination step (508), the determination of the plug matching determination step (504) is performed in the position of the currently detected error and the C1 decoding process. A second plug determination step (516) of determining the number of plugs when the position of the set error does not match or the determination of whether the erasure is corrected (step 508) is 'OFF'; And a plug setting step (step 518) of setting a plug after the syndrome calculation step (500) to the plug number second determination step (516) are performed. The method of claim 1, wherein the error correction is performed (step 404). If the number of errors determined in the error number determination step (402) is '0', error correction is not performed. If the number of errors determined is '1', error correction is performed (404-1 multisystem). If the determined number of errors is '2', '2' error correction is performed (404-2). Performing the '1' error correction (step 404-1)

And, performing the '2' error correction (step 404-2) In case of double symbol error, the error position polynomial with error positions X1 and X2

In this definition, from the polynomial

If replaced with, the polynomial can be expressed as <Equation 14>

(here,

ego,

) Also,

Is a trace of

To

Wow

If you write the expression as

, Finite field GF

If you take a trace on m = 8,

Wow

May be represented as in Equations 15 and 16, respectively. <Equation 15>

<Equation 16>

When T ₂ (k) = 0 and T ₄ (k) = 1 from Equations 15 and 16, the weights x ₁ and x ₂ of z (x ') expressed in Equation 14 are represented by Equations 17 and Can be expressed together, <Equation 17>

However, when T ₂ (k) = 0 or T ₄ (k) = 0, it can be expressed as Equation 18 below. <Equation 18>

Where y is an element in GF (2 ⁸ ) such that T ₂ (y) = 1 and satisfying T ₄ (c) = T ₄ (k + k ₁ ) = 1 when k ₁ = y + y ² By doing so, two roots represented by Equation 18 are determined. By using x ₁ and x ₂ obtained through the above process, the error positions X1 and X2 are represented by Equation 19, and the error values Y1 and Y2 are represented by Equation 20, <Equation 19>

<Equation 20>

And error correction is not performed if the number of errors determined in the error correction performing step (404) is other than '0', '1', or '2'. The method of claim 1, wherein the status retrieval step (406) is performed. As a step to search system features, data and player status, check whether there is an abnormality of EFM (Eight / Fourteen Modulation) data, player operation status, frame sync detection, etc. Are the steps to do this, STATUS FLAG C1 FLAG Set / Reset Frame Sync Detection Player operating state No error One error Two error reset (OK) reset (OK) reset reset reset / set reset (OK) set (NG) reset reset / set set set (NG) reset (OK) reset reset / set set set (NG) set (NG) reset / set set set Error correction method characterized in that. The method of claim 1, wherein the plug setting step (408) If the detected state is good in step 406, the plug is set to '0'. If the detected state is not good, the plug is set to '1'. If the number of errors is determined to be greater than or equal to '3', the error correction method of setting a plug directly to '1' without going through the error correction step (404) and the status search step (406). The method of claim 1, wherein the plug setting step (408) Setting the plug to '0' if the state found in the state search step (406) is good (step 408-1); And If the status searched in the status search step (406) is not good or if the number of errors determined in the error count determination step (402) is determined to be '3' or more, the error correction step (404 step) and the state Error setting method characterized in that the subdivided into the step (408-2) to directly set the plug to '1' without going through the search step (406). The method of claim 1, wherein the error correction step (506) is divided into a '1' error correction step (506-1) and a '2' error correction step (506-2). Performing the '1' error correction (step 506-1)

And the '2' error correction (step 506-2) is performed In case of double symbol error, the error position polynomial with error positions X1 and X2

In this case, if x = z ₁ x 'is substituted from the polynomial, the polynomial can be expressed as Equation 14 below. <Equation 14>

(here,

ego,

Also, if we write T _r (k) which is trace of k as T ₂ (k) and T ₄ (k),

, Finite field GF

If you take a trace on m = 8,

Wow

May be represented as in Equations 15 and 16, respectively. <Equation 15>

<Equation 16>

When T ₂ (k) = 0 and T ₄ (k) = 1 from Equations 15 and 16, the weights x ₁ and x ₂ of z (x ') expressed in Equation 14 are represented by Equations 17 and Can be expressed together, <Equation 17>

However, when T ₂ (k) = 0 or T ₄ (k) = 0, it can be expressed as Equation 18 below. <Equation 18>

Where y is an element in GF (2 ⁸ ) such that T ₂ (y) = 1 and satisfying T ₄ (c) = T ₄ (k + k ₁ ) = 1 when k ₁ = y + y ² By determining the two roots represented by Equation 18, the error positions X1 and X2 are represented by the following Equation 19 using x ₁ and x ₂ obtained through the above process, and the following equations of the error values Y1 and Y2 Error correction method characterized by the same as Equation 20. <Equation 19>

<Equation 20>

The error correction method according to claim 1, wherein the determination of whether to correct the eraser (step 508) is as follows. STATUS FLAG MICOM DATA Erasure Correction Frame Sync Detected Player operating state forced Erasure OFF reser (OK) reset (OK) reset ON reset (OK) set (NG) reset ON / OFF set (NG) reset (OK) reset ON / OFF set (NG) set (NG) reset ON / OFF don't care don't care set OFF The method of claim 1, wherein the plug setting step (518) The plug '0' setting step (step 518-1), the plug '1' setting step (step 518-2), and the plug 'copy' setting step (step 518-3) In the plug '0' setting step (step 518-1), the determination of the step (502-1) of determining whether the error number '0' in the error number determination step (502) does not include an error currently detected; When the error '1' or '2' is corrected in the '1' / '2' error correction step (step 506) or the result of the check in the check step (514) is satisfactory, the plug is changed to '0'. Set it up, In the plug '1' setting step (step 518-2), the number of plugs determined in the plug number first determination step (510) is '0', '1', '2', or the checking step (514). The plug is set to '1' when the result of the check in step) is bad or the number of plugs determined in the plug number second determination step 515 is '1' or '2'. In the plug 'copy' setting step (step 518-3), the number of plugs determined in the plug number first determination step (510) is '5', or in the plug number second determination step (516). An error correction method, characterized in that the setting of the "copy" of the plug when the number of the determined plug exceeds "2". An error correcting apparatus for correcting an error in data by using a Reed-Solomon code in reproduction of a digital signal, A program ROM in which an error correction decoding algorithm is coded and embedded; A program register for storing an instruction output from the program ROM; A program decoder configured to output a control signal according to a predetermined coding type from an instruction stored in the program register; Generates a control signal by determining whether to maintain a specific step or instruction for a certain period or branch to another step when correcting an error using the signal output from the program decoder and the signal output from the error correction operation unit as input signals. A jump controller; A program address counter that counts an address based on a signal output from the program register, a signal output from the program decoder, and a control signal output from the jump controller; And An error correction controller having an operation control section for generating an input / output control signal of code data necessary for error correction by the signal output from the program decoder And, A data bus for interfacing signals between components; An address generator for generating code data necessary for error correction and an address for reading / writing a plug; An a ⁱ / i converter connected to the data bus and converting any element (a ⁱ ) on the finite field GF (2 ^m ) to an integer value (i); An i / a ⁱ converter connected to the data bus and converting an integer value (i) to any element (a ⁱ ) on the finite field GF (2 ^m ); A C1 plug counter connected to the data bus and reading a C1 plug after reading C2 code data when correcting a C2 code error; A zero counter connected to the data bus and configured to detect zero data, measure a number, and output a measured number; An input / output register connected to the data bus to input and output code data, a plug, and the like; Storing the position of a subject to output signal of the one side and the output signal of one output from the address generator to be output from the a ⁱ / i transducer as the input signal is generated during the error correction operation error to an integer value or output from the address generator An error position storage register for storing the position of the eraser as an integer value; A first signal selector for selectively outputting a signal output from the address generator and output from the error position storage register; Is connected to the data bus, the finite field GF (2 ^m) a random element (a ⁱ⁾ to 1 / ^l, or a prototype of the station which converts the output into a ^-1 on the expression; A trace converter connected to the data bus and used for double symbol error correction to find the root of the error location polynomial z '(x); A second signal selector connected to the data bus and selectively outputting data on an 8-bit internal data bus or data output from the inverse generator; A second signal selector connected to the data bus and selectively outputting data on an 8-bit internal data bus or data output from the inverse generator; A third signal selector connected to the data bus and selectively outputting data on an 8-bit internal data bus or data passed through the trace converter; A MA register for temporarily storing a signal output from the second signal selector; An MB register for temporarily storing data output from the second signal selector; An AB register connected to the data bus to temporarily store data; A TEMP register connected to the data bus to temporarily store temporal data generated during a calculation; A syndrome generator connected to the data bus to obtain a syndrome element (s _i ) from code data; A C1 / C2 plug generator connected to the data bus for adding plug information or copying plug information to each code data after an error correction process; A RAM connected to the data bus and storing important coefficient data or various roots generated during an error correction operation; A multiplier for multiplying elements on the finite field GF (2 ^m ) by using the signal output from the MA register and the signal output from the MB register as input signals; And And an error correcting operation unit having an adder for adding elements on the finite field GF (2 ^m ) by using the signal output from the multiplier and the signal output from the AB register as input signals. 10. The error correcting apparatus of claim 9, wherein the inverse generator is used when performing a division operation during an error correction operation. 10. The error correcting apparatus of claim 9, wherein the adder is configured of an exclusive-OR gate.

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