JP2685180B2 - Error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Field of the Invention The present invention relates to PCM (Pulse Code Modulation).
The present invention relates to an error correction device in digital code transmission that can be applied when reproducing voice. Conventional technology When transmitting digital signals such as PCM voice, the sending side adds an error correction check code to correct bit errors during transmission, and then the receiving side uses an error correction device to send bits. A method of correcting the error is used. For example,
There is a BCH code as the correction code, and an error correction device such as that shown in FIG. 4 is well known. Hereinafter, an example of the above-mentioned conventional error correction device will be described with reference to the drawings. FIG. 4 shows a block diagram of a conventional error correction device. In FIG. 4, reference numerals 41 and 42 denote dividers, which divide an input signal based on two irreducible polynomials that form a generator polynomial for code generation and output the respective remainders. Four
3, 44 is a code converter, which inputs the remainder code obtained by the dividers 41, 42 and outputs an error position code indicating the position of the input signal in error, which is usually a ROM (read only memory) ) Is realized. 45 and 46 are coincidence detectors, 47 is a counter, and 50 is an OR circuit.The position of the signal output by the counter 47 is counted, and the coincidence detectors 45 and 46 compare the error position code with the output of the counter 47. , OR circuit outputs error correction signal when the position of the output signal is incorrect.
The logical sum of the above two error correction signals is taken by 50. A delay device 48 delays the input signal to match the timing with the error correction signal. Reference numeral 49 is a bit inverter, which inputs the input signal delayed by the delay unit 48 into an OR circuit.
The error is corrected and output by bit inversion with the error correction signal obtained in 50. Regarding the error correction device configured as above, BCH
This will be described using the (15,7) code. The BCH (15,7) code adds 8-bit error correction code to 7-bit information and transmits it with 15 bits, and an error correction device can correct two or less errors in the code generated during transmission. Code (Reference, Toshihide Hamono "Error Correction by BCH Code", Broadcasting Technology, 58.11, p.1111). For example, the generator polynomial for BCH (15,7) code is G = x ⁸
+ X ⁷ + x ⁶ + x ⁴ +1, the two irreducible polynomials are G ₁ = x ⁴ + x +
1 and G ₂ = x ⁴ + x ³ + x ² + x + 1, and the generator polynomial G is obtained by multiplying _two irreducible polynomials G ₁ and G ₂ . In FIG. 4, the dividers 41, 42 are replaced by irreducible polynomials G ₁ , G ₂
If the divider is based on, the configurations are as shown in FIGS. 2 and 3, respectively. In FIGS. 2 and 3, 21a to 21d and 31a to 31d are flip-flops, which delay the signal by one clock. 22a ~ 22b, 32a ~
32d is an adder circuit that performs addition modulo 2, EX
It can be realized with an OR circuit. 23a to 23d and 33a to 33d are output terminals of the respective dividers, and 24 and 34 are input terminals of the respective dividers. In FIG. 4, the code converters 43 and 44 can be composed of ROM,
When the remainder code output from the dividers 41 and 42 is concatenated to the ROM address, and for all errors of 2 or less, when the remainder code output from the dividers 41 and 42 at that time is given as the address , RO so that the position of the error is output
Set M data. Now, when the transmitted signal is input from the input terminal 51, the input signal is input by the delay unit 48 for one code (15 in this example).
The input signal is simultaneously divided by a divider 4
It is divided by 1,42. When the input signal is input by one code, the remainder code is obtained by the dividers 41 and 42, and the code indicating the error position in the signal input by the code converters 43 and 44 is obtained. Then, the dividers 41 and 42 are stopped, the counter 47 is activated, and the counter 47 outputs the signal from the delay device 48 while counting the position of the output signal. At this time,
The output of the code converters 43, 44 is compared with the output of the counter 47 by the coincidence detectors 45, 46, and the position of the error indicated by the code converters 43, 44 and the position of the output code indicated by the counter match. An error correction signal is sometimes output, and an error correction signal logically ORed by the OR circuit 50 inverts the output signal by the bit inverter 49 to correct the error and output from the output terminal 52. The initial states of the flip-flops in the dividers 41 and 42 are all zero, and the input signal is the code generated by the generator polynomial G. Problems to be Solved by the Invention However, in the configuration as described above, the ROM used in the code converter has an address of the number of bits in which two residue codes are concatenated, and each address can represent an error position. Therefore, there is a problem that the ROM having the output of the number of bits is required, the capacity of the ROM is very large, and the circuit scale of the error correction device becomes large. Furthermore, when the code length used for error correction increases, the ROM capacity increases exponentially with the code length, and the circuit scale of the error correction device becomes enormous. For example, in the case of a BCH (15,7) code having a code length of 15 bits, each remainder code output from the two dividers is 4 bits, and the ROM address is 8 bits. The number is 4 bits to indicate the bit position in the code length of 15 bits, and since there are two ROMs, one for each of the code converters 43 and 44, the total capacity of the ROM is 20.
It requires 48 (= 2 × 4 × 2 ⁸ ) bits, and the BCH (63,51) code having a code length of 63 bits requires a ROM capacity of 49152 bits. Therefore, the present invention provides an error correction device having a small circuit scale and a small ROM capacity. Means for Solving the Problem In order to solve the above-mentioned problems, the error correction device of the present invention is a primitive polynomial of two irreducible polynomials forming a generator polynomial for generating an error correction code for correcting two or less errors. A first divider that performs division by a first irreducible polynomial that is a second irreducible polynomial, a second divider that performs division by a second irreducible polynomial that is another irreducible polynomial, and a first divider A code converter that converts the first remainder code obtained in step 1 and outputs a check code, and the second remainder code obtained by the second divider and the check code are compared, and an error correction signal is output. And a coincidence detector. According to the present invention, when the ROM is used as the code converter, the remainder code input as the address of the ROM is only the remainder code output from one of the two dividers, and the coincidence detector has the above-described configuration. By comparing the remainder code output from the other divider with the output of the code converter to generate the error correction signal, the capacity of the ROM used for the code converter can be reduced and the circuit scale of the error correction device can be reduced. can do. Embodiment An error correction device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the error correction device of the present invention. In FIG. 1, 1 is a divider,
This is to perform division based on a first irreducible polynomial, which is a primitive polynomial, out of two irreducible polynomials that form a generator polynomial for generating an error correction code, and output a residue code. Reference numeral 2 denotes a divider, which performs division based on a second irreducible polynomial, which is one of the two irreducible polynomials that is not the first irreducible polynomial, and outputs a remainder code. Reference numeral 3 denotes a code converter which inputs the remainder code obtained by the divider 1 and outputs a check code. Reference numeral 4 is a coincidence detector, which inspects the coincidence between the remainder code and the check code obtained by the divider 2 and outputs an error correction signal. A selector 5 is controlled to select either the input signal or the error correction signal and input it to the divider 1 and the divider 2. Reference numeral 6 denotes a delay device, which delays the input signal by a predetermined number of clock pulses and takes timing with the error correction signal. Reference numeral 7 is a bit inverter, which inverts the input signal delayed by the delay device 6 with an error correction signal, and can be realized by an EX-OR circuit. The error correction device configured as described above will be explained using the BCH (15,7) code described above. Here, the generator polynomial G and the irreducible polynomials G ₁ and G ₂ are the same as those described above, the irreducible polynomial that is a primitive polynomial is the irreducible polynomial G ₁ , and the divider 1 is based on the irreducible polynomial G ₁ . The division is performed, for example, as shown in FIG. The divider 2 performs division based on the irreducible polynomial G ₂ , and is, for example, as shown in FIG. Now, numbers are sequentially assigned from the signal transmitted prior to the error correction code, and the first bit to the fifteenth bit are set. Further, when an error correction code in which an error occurs in the i-th bit and the j-th bit is input to the dividers 1 and 2 during transmission, the 4-bit remainder code output from the dividers 1 and 2 is R ₁ respectively. (I, j), R ₂
(I, j) (where i <j), and when an error occurs only in the i-th bit, the remainder codes output from the dividers 1 and 2 are R ₁ (i, i) and R ₂ (respectively). i, i). The code converter 3 is configured by using a ROM, and for 1 ≦ i ≦ 15, R ₁ (1, i) is used as the ROM address, and R ₂ (1, i) is output at that address. R in advance
Set OM. Here, since the divider 1 performs division based on an irreducible polynomial that is a primitive polynomial, 1 ≦ i ≦
For i and j such that 15,1 ≦ j ≦ 15, i ≠ j, R ₁ (1,
It is easy to show that i) ≠ R ₁ (1, j). In Table 1
Indicates the data to be set in ROM. The left side of the address and data remainder codes R ₁ (1, i) and R ₂ (1, i) in Table 1 indicates the least significant bit, and the leftmost bits of the remainder code R ₁ (1, i) are listed in order from the leftmost bit. The remainder code R is output to the output terminals 23a to 23d in FIG.
₂ Output terminal 33a in Fig. 3 in order from the bit on the left side of (1, i)
Corresponds to ~ 33d output. The processing when the remainder code output from the divider 1 is zero (0000), that is, when there is no error will be described later. Here, if the remainder code of R ₁ (i, j) is output from the divider 1 at i, j and k such that 2 ≦ i ≦ 15, i ≦ j ≦ 15, 1 ≦ k ≦ 15, R ₁ Remainder code such that (i, j) = R ₁ (1, k)
R ₁ (1, k) exists and the code converter 3 (ROM) has a residue code R ₁
The input of (1, k) outputs R ₂ (1, k) as a check code.
From the definition of the error correction code, R ₁ (i, j) = R ₁ (1, k) and R
_{Since 2} (i, j) = R ₂ (1, k) does not hold at the same time, the check code R ₂ (1, k) obtained by converting the remainder code R ₁ (i, j) by the code converter 3 And the remainder code R ₂ (i, j) obtained by the divider 2
Therefore, no error correction signal is output from the coincidence detector 4. The operation of the error correction device of the present invention will be described below assuming that a signal having an error in the second bit and the sixth bit is input. First, all the shift registers in the dividers 1 and 2 are set to zero, and the selector 5 is controlled so that the input signal from the input terminal 8 is input to the dividers 1 and 2. Next, the input signal from the input terminal 8 is given to the delay unit 6 and the selectors 1 and 2 via the selector 5. A signal is sequentially input while operating the dividers 1 and 2 and the delay device 6, and when the signal is input by one code, the selector 5 is controlled and the error correction signal obtained by the coincidence detector 4 is a divider. Make sure that it is input to 1,2.
The input signal is output after being delayed by one code by the delay device 1, and then sequentially output. When the signal for one code is input, the dividers 1, 2
Output the residual codes R ₁ (2,6) and R ₂ (2,6), respectively, and the code converter 3 supplies the check code obtained by converting R ₁ (2,6) to the coincidence detector 4. In this case, the check code obtained by converting R ₁ (2,6) by the code converter 3 and R ₂ (2,6)
, The error correction signal is not output and the delay unit 6
The signal of the first bit output from the output terminal 9 passes through the bit inverter 7 and is output from the output terminal 9 as it is. Then, when the delay unit 6 and the dividers 1 and 2 are operated for one clock, the delay unit 6 outputs the signal of the second bit,
The remainder codes R ₁ (1,5) and R ₂ (1,5) are output from the dividers 1 and 2, respectively. The operation of the divider at this time can be easily confirmed from the circuit diagrams of the divider shown in FIGS. For example, in the case of the above-described operation in the divider 1, the remainder code R ₁ (2,6) is 1110, that is, the states of the flip-flops 21a to 21d in FIG.
At 1,0, since the error correction signal is not output from the coincidence detector 4, the input of the divider 1 is 0. If the divider is operated for one clock from that state, the flip-flops 21a to 21a in FIG. The states of 21d are 0,1,1,1 respectively,
It can be seen that the remainder code is 0111, that is, R ₁ (1,5). The operation of the divider 2 can be similarly confirmed using FIG. 3, and the detailed operation of the divider will be omitted in the following description. In this case, R ₁ (1,
The check code converted from 5) and R ₂ (1,5) match, an error correction signal is output, and the signal of the second bit output from the delay unit 6 by the error correction signal is inverted by the bit inverter 7. , The error is corrected and output from the output terminal 9. Then, when the delay unit 6 and the dividers 1 and 2 are operated for one clock, the delay unit 6 outputs the signal of the third bit,
The remainder codes R ₁ (4,4) and R ₂ (4,4) are output from the dividers 1 and 2, respectively. In the operation of the dividers 1 and 2, the above error correction signal is input to the dividers 1 and 2 through the selector 5, so that the input terminals 24 and 34 of the dividers in FIGS. 1 has been entered. In this case, the check code R ₂ (4,4) obtained by converting R ₁ (4,4) by the code converter 3
, The error correction signal is not output and the delay unit 6
The third bit signal output from the output terminal 9 is output from the output terminal 9 as it is through the bit inverter 7. With the same operation,
The signals of the 4th and 5th bits are directly output from the output terminal 9. Then, when the delay unit 6 and the dividers 1 and 2 are operated for one clock, the 6th bit signal is output from the delay unit 6,
The remainder codes R ₁ (1,1) and R ₂ (1,1) are output from the dividers 1 and 2, respectively. In this case, the check code obtained by converting R ₁ (1,1) by the code converter 3 matches R ₂ (1,1), the error correction signal is output, and the error correction signal is output from the delay unit 6. The signal of the sixth bit is inverted by the bit inverter 7, the error is corrected, and the signal is output from the output terminal 9. Further, the error correction signal passes through the selector 5 and the divider 1,
It is input to 2, the residual code becomes zero, and shows the error-free state thereafter. Then, when the delay unit 6 and the dividers 1 and 2 are operated for one clock, the delay unit 6 outputs the signal of the 7th bit,
The zero code is output from each of the dividers 1 and 2. In this case, the coincidence detector does not output the error correction signal, and the signal of the 7th bit output from the delay device 6 is output from the output terminal 9 as it is through the bit inverter 7. Thereafter, in the same operation, the signals of the 8th to 15th bits are output from the output terminal 9 as they are, and the error correction is completed. Further, from the operation of the error correction device after the third bit described above, it can be understood that even if only one bit in the code is erroneous, it can be corrected correctly. In this embodiment, in order to prevent the error correction signal from being output when there is no error or when all the errors are corrected in the middle, that is, when the remainder code output from the dividers 1 and 2 is zero, The code converter 3 outputs a correction control signal together with a check code when the remainder code output from the divider 1 is zero, and prevents the coincidence detector 4 from outputting an error correction signal or outputs the output from the divider 1. When the remainder code is zero, the code converter 3 outputs a code other than zero as a check code, and when there is no error, the match detector matches the remainder code (zero) of the divider 2 with the check code. Try not to. If the error correction device is configured as in this embodiment as described above, when a ROM is used as the code converter, one residue code is input as the address of the ROM, and the remaining residue is detected by the coincidence detector. ROM used for the code converter by comparing the code and the output of the code converter to generate an error correction signal
Can be reduced, and the circuit scale of the error correction device can be reduced. For example, in the case of a BCH (15,7) code having a code length of 15 bits, the remainder code is 4 bits, the ROM address is 4 bits, and the number of bits of data output at one address is 4 bits.
Since the capacity of the ROM is 64 bits (= 4 × 2 ⁴ ) in total, the ROM capacity of the present invention is extremely small, and further, the BCH (63,
For the 51) code, the capacity of the ROM only needs to be 384 bits, and the effect of the present invention becomes more remarkable as the code length of the error correction code increases. Table 2 shows the capacity of the ROM used in the code converter of the conventional error correction device shown in FIG. 4 and the error correction device of the present invention shown in FIG. 1 with respect to the code length of the error correction code. . As can be seen from Table 2, the error correction device of the present invention can make the ROM capacity extremely small, and the effect of the present invention becomes more remarkable as the code length of the error correction signal increases. EFFECTS OF THE INVENTION As described above, the present invention performs division by the first irreducible polynomial, which is a primitive polynomial, of two irreducible polynomials that form a generator polynomial for generating an error correction code that corrects two or less errors. The first divider, the second divider that performs division with the other second irreducible polynomial, and the remainder code obtained by the first divider are converted to check code Of the ROM used for the code converter by providing a code converter for outputting the code and a match detector for checking the match between the remainder code and the check code obtained by the second divider and outputting an error correction signal. The capacity can be made extremely small, and an error correction device having an extremely small circuit scale can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an error correction device according to the present invention, and FIGS. 2 and 3 are the configuration of a divider used in the error correction device of FIG. 1 or 4. Circuit diagram showing the fourth
FIG. 1 is a block diagram showing the structure of a conventional error correction device. 1 ... Divider based on irreducible polynomials that are primitive polynomials, 2
…… Divider based on the remaining irreducible polynomials, 3 …… Sign converter, 4 …… Match detector, 5 …… Selector, 6,48 …… Delayer, 7,49 …… Bit inverter, 21a, 21b, 31a to 31d ... flip-flops, 22a to 22d, 32a to 32d ... adders, 41, 42
...... Divider, 43,44 …… Code converter, 45,46 …… Match detector, 47 …… Counter.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) Reference JP-A-58-175334 (JP, A)                 JP-A-61-288524 (JP, A)                 JP-A-56-44974 (JP, A)                 JP-A-55-109054 (JP, A)

Claims (1)

(57) [Claims] An error correction device that corrects 1.2 or less errors, and includes two irreducible polynomials that form a generator polynomial for error correction code generation that corrects two or less errors First dividing means for performing division by the first irreducible polynomial, which is a primitive polynomial,
A second irreducible polynomial that is not the first irreducible polynomial
Second division means for performing division with the irreducible polynomial, code conversion means for converting the first residue code obtained by the first division means and outputting a check code, and the second division means. Coincidence detection means for comparing the second remainder code obtained in step 1 and the check code and outputting an error correction signal, and the first division means for selecting either the input signal or the error correction signal, Selection means controlled to be input to the second division means, delay means for delaying the input signal by a predetermined number of clock pulses, and bit inversion for inverting the output signal of the delay means with the error correction signal. And means,
A second residue obtained by the second division means is a first residue code obtained by the first division means when the code conversion means makes an error in a predetermined bit or the predetermined bit and another one bit. An error correction device characterized by converting to a remainder code and outputting as a check code.