JP2591164B2 - Parity operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In digital multiplex communication in which communication is performed in a frame in which a plurality of digital data are multiplexed, a digital parity operation inserted at the same bit position in each frame and repeated at a period of m bits is performed. And a parity operation circuit for performing parity operation of data inserted at different bit positions of each frame and repeated at a period of n bits. An object of the present invention is to provide a small, small-scale, highly reliable parity operation circuit. Means for performing a parity operation on data having different repetition periods, and a repetition period in the operation means is m
The first initialization means for initializing the bit data, the second initialization means for initializing the data having a repetition period of n bits in the arithmetic means, the first initialization means, and the second initialization means. A first selection unit for selecting an initialization signal; and a second selection unit for selecting and outputting a parity operation result of the operation unit in accordance with the m-bit data and the n-bit data in a repetition period. I do.

[Industrial applications]

The present invention relates to a multiplexed signal parity operation circuit in which data of m bits and n bits having a repetition period are multiplexed.

There are various methods of error detection in digital data transmission. One bit of data is added to transmission data so that the number of "1" in the data is always an even number (or an odd number). The parity check, which checks that the number of “1” in the received data is always even (or odd) and that no error occurs, has low redundancy and can be easily executed. Widely used from.

In digital multiplex communication, data having different repetition periods is multiplexed. FIG. 6 shows an example of a parity operation of multiplexed data. In the figure, one frame is composed of 8 bits b0 to b7, and the repetition period of each data is 8 bits. Here, when data is inserted into b0 and b4, the repetition period becomes 4 bits, and data having different repetition periods is multiplexed into the frame. It is necessary to accurately check the parity of such data with a simple circuit.

[Conventional technology]

FIG. 4 is a diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a parity operation.

The configuration shown in FIG. 4 includes a shift register (m) 10A that shifts m-bit data by m bits, an initialization circuit (m) 20A that initializes the shift register (m) 10A, and input data and a shift register. (M) an exclusive-NOR circuit (hereinafter referred to as an EX-NOR circuit) which performs a parity operation by taking an exclusive-NOR with the output of 10A (m) 30A, and n-bit data having a repetition period of n bits A shift register (n) 10B for shifting, an initialization circuit (n) 20B for initializing the shift register (n) 10B, and a parity operation by taking exclusive NOR of input data and an output of the shift register (n) 10B EX-NOR circuit (n) 30B, shift register (m) 10A and shift register (n) 10B
This is an example in which the selector 40A selects and outputs any one of the above.

FIG. 5 is a diagram for explaining the parity calculation. Here, m = 8 and n = 4 as an example.

Is input data, 1, 2, 3, 4, 6, 7, 8
Is a subscriber number, 1 is data repeated every 4 bits, and other than 1 is data repeated every 8 bits.

 Represents data obtained by shifting the input data by 4 bits, and represents data obtained by shifting the input data by 8 bits.

The data of the subscriber number 1 is shifted by 4 bits, the EX-NOR of the previous data and the current data is taken as the parity, the result is input to a 4-bit shift register, and the data shifted by 4 bits and the next data are shifted. Ex-NOR with data and parity operation.

Similarly, for the subscriber data other than 1, a parity operation is performed by taking EX-NOR between the signal shifted by 8 bits and the input signal.

Is a selection signal. When the subscriber number is 1, the selection signal becomes "0", and the output of the 4-bit shift register is selected and output. Select and output the output of the shift register.

[Problems to be solved by the invention]

In the above-described conventional example, it is necessary to use a plurality of parity operation circuits, shift registers, and the like for data with different repetition periods, which increases the circuit scale.

In recent years, various circuits have been built into LSIs, and for this purpose, it is necessary to reduce the circuit scale.

An object of the present invention is to provide a small, small-scale, and highly reliable parity operation circuit.

[Means for solving the problem]

 FIG. 1 is a block diagram illustrating the principle of the present invention.

In the principle block diagram shown in FIG. 1, reference numeral 10 denotes an operation means for performing a parity operation of multiplexed data having different repetition periods, and 20 initializes data of the operation unit 10 having a repetition period of m bits. Reference numeral 30 denotes first initialization means, reference numeral 30 denotes second initialization means for initializing data having a repetition period of n bits in the arithmetic means 10, and reference numeral 40 denotes first initialization means 20 and second initialization means 30. A first selection means for selecting the generated initialization signal, 50 is a parity calculation result of the calculation means, and a repetition period is m.
This is second selection means for selecting and outputting the bit data and the n-bit data in accordance with the data, and is provided as a means for solving this problem by including such means.

(Operation)

The arithmetic means 10 shifts the data having a repetition period of m and n by m bits and n bits, respectively, and performs a parity operation on the input data.

The result of the parity operation is output at a predetermined cycle, and the first selecting means 40 uses the first initializing means for data having a repetition cycle of m, and the data for data having a repetition cycle of n. Second initialization means 30
Select and initialize.

The result of the parity operation performed by the operation unit 10 is a second selection unit that determines a parity for data having a repetition period of m and a parity for data having a repetition period of n.
By configuring so as to select and output data according to 50, a small, small-scale, and highly reliable parity operation circuit can be realized.

〔Example〕

Hereinafter, the gist of the present invention will be specifically described with reference to the embodiments shown in FIGS.

FIG. 2 is a diagram for explaining the embodiment of the present invention, and FIG. 3 is a diagram for explaining a time chart of the embodiment of the present invention. The same reference numerals indicate the same objects throughout the drawings.

The embodiment of the present invention shown in FIG. 2 will be described with an example where m = 28 and n = 7. The configuration shown in FIG. 2 is based on the arithmetic means described in FIG.
An exclusive-OR circuit (hereinafter referred to as an EX-OR circuit) 11 for performing an exclusive-OR operation on the result of the previous parity operation and the present input data and performing a parity operation, and a 28-bit shift register 12, A NAND circuit (hereinafter referred to as a NAND circuit) 21 as the first initialization means 20, a NAND circuit 31 as the second initialization means 30, and two AND circuits (hereinafter AN) as the first selection means 40
D circuits) 41 and 42, a NOR circuit (hereinafter referred to as NOR circuit) 43, and two AND circuits 51 and 52 and NOR
This is an example of a configuration including a circuit 53 and an inverter 11 for inverting multiplexed information.

In this configuration, depending on the shift register 12, n shifts 7 bits with respect to the input data, m shifts 28 bits with respect to the input data, performs a parity operation on the shifted data and the input data, and outputs the result. .

Timing 1 and timing 2 are timing signals for initializing the result of the parity operation.

FIG. 3 is a time chart showing an example of the parity operation.

The input data is data having a repetition cycle of 28 bits and 7 bits, and up to 28 subscribers can be accommodated.

(1) is 1 of which the repetition period is 7 bits.
Data about the subscriber is extracted.

(2) is the data output from the NOR circuit 43 by shifting the output (3) of the EX-OR circuit 11 by 7 bits, and (3) is the EX-OR of (1) and (2). When the two data match, "0" is output, and when they do not match, "1" is output, and this output is the parity calculation result required. (In this example, when the number of "1" in the data is an odd number, the parity output becomes "1".) (4) is a signal of the initialization timing 2, and a repetition period of 7 bits is added. Is a signal for resetting the data of the user.

At the point where (3) and (2) in the figure are connected by a broken line,
Since the data of (3) is "1", the corresponding data of (2) shifted by 7 bits also becomes "1". However, since the data is reset at the initialization timing 2, the corresponding of (2) The data to be executed is “0”.

(5) is data obtained by shifting the data of (3) by 7 bits, and is input to the AND circuit 51. The other input is "1" obtained by inverting the multiplexed information by the inverter I1. The signal is output with the polarity, input to the NOR circuit 53, the polarity is inverted, and output as the parity operation result PTY. In FIG. 6, the object of the parity operation has been described as digital multiplexed data in which digital data is multiplexed and communicated as a frame. However, the present invention applies to a plurality of data having a constant repetition period and different repetition periods. The present invention is not limited to data communicated as a frame.

As described above, by outputting data delayed by m bits and n bits from one shift register and performing a parity operation, it is possible to perform a parity operation on data having different repetition periods with one arithmetic circuit. Becomes

〔The invention's effect〕

According to the present invention as described above, it is possible to provide a small-sized, small-scale, and highly reliable parity operation circuit that can perform a parity operation on data having different repetition periods with a single operation circuit. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating a time chart of the embodiment of the present invention, and FIG. FIG. 5 illustrates an example of a parity operation, and FIG. 6 illustrates an example of a parity operation of multiplexed data. In the figure, 10 is arithmetic means, 11 is an EX-OR circuit, 10A, 10B and 12 are shift registers, 20 is first initializing means, 20A and 20B are initialize circuits, 21 and 31 are NAND circuits, and 30 is a second circuit. Initializing means, 30A and 30B are EX-NOR circuits, 40 is first selecting means, 40A is a selector, 41, 42, 51, and 52 are AND circuits, 43 and 53 are NOR circuits, and 50 is second selecting means. , I1 indicate an inverter, respectively.

Claims (1)

(57) [Claims] 1. In digital multiplex communication in which communication is performed in a frame in which a plurality of digital data are multiplexed, a parity calculation of data inserted at the same bit position of each frame and repeated at a period of m bits, and A parity calculation circuit for calculating parity of data inserted at different bit positions and repeated at a cycle of n bits, a calculation means (10) for performing a parity calculation of multiplexed data having different repetition cycles, and the calculation means First initialization means (20) for initializing data having a repetition cycle of m bits in (10); and second initialization means for initializing data having a repetition cycle of n bits in the arithmetic means (10). (30), the first initialization means (20), and a second initialization means. First selecting means (40) for selecting an initialization signal generated in the stage (30); and a parity operation result of the arithmetic means (10), wherein a repetition cycle is set in accordance with m-bit data and n-bit data. ,
And a second selecting means (50) for selecting and outputting.