JP2797569B2 - Euclidean circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field of Use B Summary of Invention C Prior Art C ₁ Description of Encoder for Error Correcting Code C ₂ Description of Overall Configuration of Decoder for Error Correcting Code (No. 9
Figure) Description of derivation circuit of a conventional error locator polynomial using the C ₃ Euclidean (FIG. 10, FIG. 11) C ₄ describes the derivation circuit of the conventional improved error location polynomial (Figure 12, FIG. 13) D Problems to be Solved by the Invention E Means for Solving the Problems F Function G Example G ₁ Description of the Mutual Reciprocating Unit Used in One Example (FIG. 14 to FIG. 14)
Description of derivation circuit of the error locator polynomial of FIG. 18) G ₂ an embodiment (first
Figure, Fig. 2) G ₃ more descriptive of a specific configuration of mutual division unit (Figure 3,
Figure 4) G ₄ Description of another example of the mutual division unit (FIG. 5-FIG. 8) H FIELD The present invention on the effect A industrial invention, for example, suitable Euclidean applied to the decoder of an error correction code , And an alternation circuit.

B SUMMARY OF THE INVENTION The present invention relates to a Euclidean mutual elimination circuit suitable for application to, for example, an error correction code decoder, and relates to a quotient and a remainder when a polynomial including a first input polynomial as a factor is divided by a second input polynomial. And the quotient and the entire quotient up to the third input polynomial are obtained, and the remainder, the first input polynomial or the second input polynomial and the entire quotient are respectively obtained as a first output polynomial, One or a plurality of cascade-connected reciprocal units forming an output polynomial of 2 and a third output polynomial, and an initial polynomial of each of the first, second and third input polynomials is supplied to one input port. Data selecting means for supplying the output data to the one mutual unit or the first mutual unit among the plural units, and the output data of the one mutual unit or the plural The output data of the mutual division unit end and a other feedback means for supplying to an input port of the data selection means,
By using one or a plurality of cascade-connected reciprocal units, respectively, a plurality of times, the number of reciprocal units can be reduced and the circuit size can be reduced.

Digital processing techniques for recording and reproducing described audio signal and the video signal of C encoder of the prior art C ₁ error correction code, etc. in the form of digital signals are becoming widespread. An important technique in this digital signal processing technique is a technique of encoding and decoding an error correction code. Error correction codes include BCH codes in a broad sense, Goppa codes, etc., and the present invention can be applied to these error correction codes.However, in this specification, only the Reed-Solomon code, which is a special case of the BCH code, is used. Treat.

In the Reed-Solomon code, an element of a finite field GF (2 ^m ) (m is an integer of 1 or more) is associated with each symbol. The irreducible generator polynomial of the finite field GF (2 ^m ) is represented by G (X),
Assuming that the root of (X) = 0 is α, each element of the finite field GF (2 ^m ), that is, each symbol, can be represented by a power of α. Further, the power of α ⁱ (i is an integer) can be represented by an m-bit binary number in a vector representation, and the vector representation is convenient in digital signal processing.

In order to encode the Reed-Solomon code, first, the following parity check matrix H is defined using the above α.

In this case, n represents the code length, t represents the number of correctable symbols, and the original information is represented by (n−2t) symbols u ₀ to u ₀ .
If u _n-2t-1 and parity information are represented by _2t symbols p _{0 to} p _2t−1 , the transmission codeword f can be represented by a vector having n symbols as elements as follows. Note that [‥‥] ^t indicates a transposed matrix.

f = [p ₀ p ₁ ‥‥ p _2t-1 u ₀ u ₁ ‥‥ un _-2t-1 ] ^{t A} (2A) Then, the encoder operates such that Hf = 0 ‥‥ (3) holds. Number of symbols of parity information p _{0 to} p
Determine _2t-1 . Also, the transmission codeword f is represented by a polynomial expression f
When (X), f (X) = p 0 + p 1 X + ‥‥ + p 2t-1 X 2t-1 + u 0 X 2t + ‥‥ + u n-2t-1 X n-1 ‥‥ (2B) , and the By sequentially substituting α, α ² , ‥‥, α ^2t into the variable X of the equation (2B), the equation (3) can be expressed as follows.

f (α) = 0, f (α ² ) = 0, ‥‥, f (α ^2t ) = 0 ４ (4) Description of overall configuration of decoder for C ₂ error correction code (ninth embodiment)
When a transmission error e is given to the transmission codeword f, the reception codeword r becomes r = f + e ‥‥ (5A) in vector expression, and when this expression (5A) is represented by a polynomial expression, r (X) = f ( X) + e (X) = r 0 + r 1 X + ‥‥ + r n-1 X n-1 ‥‥ become (5B). In the Reed-Solomon code, when the code length is n and the number of symbols of parity information is 2t, error correction can be performed when the number of non-zero error symbols in the transmission error e is t or less.

FIG. 9 shows the overall configuration of the decoder for error correction code,
In FIG. 9, (1) is a syndrome generating circuit, and the syndrome generating circuit (1) generates a syndrome S by multiplying the parity check matrix H of the equation (1) by r after the reception code. I do. This syndrome S is expressed as S = [S ₁ S ₂ ‥‥ S _2t ] ^t ‥‥ (6A) in the vector expression, and S (X) = S ₁ + S ₂ X + S ₃ X ² + ‥‥ + S _2t X ^{2t in the} polynomial expression. ^-1 ‥‥ (6B). Then, when S = Hr is expressed using each element, the following is obtained.

To summarize this equation (7A), Where the polynomial expression of the transmission error e is e (X) = e ₀ X + e
_{Using 1} × ² + ‥‥ + en _-1 ^Xn-1 and the condition in the encoder of Expression (4), Expression (7B) can be expressed as follows.

S _j = e (α ^j ) (i = 1,2, ‥‥ 2t) ‥‥ (7c) In FIG. 9, (2) shows a circuit for deriving an error locator polynomial. 2) calculates each coefficient of the error locator polynomial σ (X) and each coefficient of the error evaluation polynomial ω (X) from the syndrome polynomial S (X) (actually, each coefficient of S (X)), and calculates Each coefficient is supplied to an error position detection circuit (3) and an error pattern calculation circuit (4).

In this case, when an error occurs at the j-th position from the beginning of the received codeword r (that is, when e _j ≠ 0), α ^j is referred to as an error position. Then, assuming that the number of non-zero elements of the transmission error e is ν (ν ≦ t), the error position of these ν non-zero elements (error symbols) is X _i , and the error pattern is Y _i
Assuming that (i = 1,2, ‥‥ ν), the ν error symbols can be represented by (X _i , Y _i ), respectively, and the equation (7C) can be represented as follows.

Equation (7D) shows 2t equations, and the unknowns are (X _i , Y _i )
Since these are 2ν (2ν ≦ 2t), these unknowns (X _i ,
Y _i ) can be uniquely determined. However, unknowns (X _i , Y _i ) (i = 1, 2, ‥‥,
In order to easily find ν), the error locator polynomial σ
(X) and the error evaluation polynomial ω (X) are introduced.

ω (X) = S (X) · σ (X) (modX ^2t ) ‥‥ (9) From equation (8), σ (X _i ⁻¹ ) = 0 (i = 1, 2, ‥‥, ν) Holds, the coefficient σ _{i of} this error locator polynomial σ (X)
Is obtained, α ^-j (j = 0,1, ‥‥ n-1) is sequentially converted to σ
By substituting into (X) and performing a full search for α ^-j when σ (α ^-j ) = 0, the error position X _i (i = 1,2, ‥‥,
v) can be detected.

On the other hand, when the error pattern for error position X _i and Y _i, the error pattern Y _i by using the error evaluation polynomial omega (X) is known to be calculated as follows.

As described later, the error locator polynomial σ (X) and the error evaluation polynomial ω (X) can be derived from the syndrome polynomial S (X) by the Euclidean algorithm. The detection circuit (3) of the error position in FIG. 9 detects the error position X _i from the error position polynomial sigma (X), and generates a digital signal which becomes high level "1" at the error position The signal is supplied to one input terminal of each of the AND gates (5). Further, m calculation circuit of the error pattern (4) is a vector representation of the error pattern Y _i calculated using equation (10)
When a binary number of bits is supplied to each other input terminal of the AND gate group (5) at each error position, a vector representation of each coefficient of the transmission error polynomial e (X) is obtained from the AND gate group (5). Are generated in chronological order. Then, a vector representation of a coefficient obtained by delaying each coefficient of the received codeword polynomial r (X) by a predetermined time in the delay circuit (7) and a vector representation of each coefficient of the transmission error polynomial e (X) are obtained. mod2
, The vector representation of each coefficient of the error-corrected transmission codeword polynomial f (X) is obtained. This uses the fact that addition and subtraction are the same operation in mod2.

Description of derivation circuit of a conventional error locator polynomial using the C ₃ Euclidean (FIG. 10, FIG. 11) two polynomials _{r -1 (X), r 0} (X) is given, deg
If (degree) r ₀ ≦ deg r ₋₁ , the following division is repeatedly executed in the Euclidean algorithm.

Then, the last divisible non-zero r _j (X) is r
The greatest common polynomial between _-1 (X) and r ₀ (X) (Greatest Com
mon Devisor: GCD).

The following theorem is derived based on this Euclidean algorithm. That is, given two polynomials r _-1 (X), r ₀ (X), and if deg r ₀ ≤ deg r _-1 and GCD is h (X), U (X) · r _-1 ( X) + V (X) · r ₀ (X) = h
(X) There are U (X) and V (X) satisfying ‥‥ (12), and both degU and degV are smaller than deg r _-1 . To determine U (X) and V (X), U ₋₁ (X) = 0, U ₀ (X) = 1 ‥‥ (13A) V ₋₁ (X) = 1, V ₀ (X) = 0 By defining ‥‥ (13B), the quotient q _i (i =
1,2, Ｘ, j + 1) and U _i (X), V
Calculate _i (X).

U _i (X) = q _i (X) · U _i−1 (X) + U _i−2 (X) ‥‥ (14A) V _i (X) = q _i (X) · V _i−1 (X) + V _i−2 (X) ‥‥ (14B) In this case, (−1) ^{j + 1} V _j (X) becomes U (X), and (−1) ^j U _j (X) becomes V (X). Become.

Applying the Euclidean algorithm of Equations (11A) to (11Z) and Equations (14A) and (14B), the syndrome polynomial S
Step (100) shown in FIG. 11 from (X) (Equation (6B))
Error location polynomial σ by the algorithm of ~ (105)
(X), it is known that an error evaluation polynomial ω (X) is required.

Step (100) Assuming that the upper limit of the number of symbols that can be corrected is t,
Let r _-1 (X) and r ₀ (X) be X ^2t and S (X), respectively.
Set U _-1 (X) and U ₀ (X) to 0 and 1, respectively.

Step (101) The number of steps i is set to 1.

Step (102) The quotient obtained by dividing r _i-2 (X) by r _i-1 (X) is defined as q _i (X), and the expression (11Y) in which j is replaced by i and the expression (14A)
Calculate r _i (X) and U _i (X). _{That, r i (X) = r} i-2 (X) -q i (X) r i-1 (X) ‥‥ (15A) U i (X) = U i-2 (X) -q i ( X) U _i−1 (X)） (15B) Step (103) It is checked whether the order of r _i (X) is equal to or less than the (t−1) order. deg when the _{r i (X) ≦ t-} 1 moves to step (105), when the _{deg r i (X)> t} -1 proceeds to step (104).

Step (104) The number of steps i is incremented by 1 and the process returns to step (102).

Step (105) δ times of U _i (X) becomes the error locator polynomial σ (X), and r _i
(−1) ⁱ δ times (X) becomes the error evaluation polynomial ω (X).

δ is a constant for setting σ ₀ (coefficient of the 0th order in equation (8)) to 1. In an actual calculation, only X _i where σ (X _i ) = 0 is a problem. can do. Also, addition and subtraction are the same on the finite field GF (2 ^m ),
(-1) ⁱ can also be 1.

FIG. 10 shows a virtual circuit (specific configuration of a conventional error locator polynomial derivation circuit (2)) for executing the algorithm of FIG. 11, and in FIG.
(8Z) are mutual units with the same configuration as a whole, (9
A) to (9Z) correspond to q _i in step (102) in FIG. 11, respectively.
The main calculation unit for calculating (X) and r _i (X), (10
A) to (10Z) are sub-calculation units for calculating U _i (X), respectively. Also, the function r is added to the first mutual unit (8A).
Initial values of _i (X) and U _i (X) r ₋₁ (X) = X ^2t , r ₀ (X) =
Given S (X), U _-1 (X), U ₀ (X), these functions gradually become (r
₀ (X), r ₁ (X), U ₀ (X), U ₁ (X)), (r ₁ (X), r
₂ (X), U ₁ (X), U ₂ (X)), ‥‥, and ω (X) and σ (X) are output from the rear end mutual unit (8Z).

When the Euclidean algorithm is used in this way, a cascade connection of the identical units (8A) to (8Z) forms a systolic-array architectur.
e) There are benefits that can be taken. However, in the main calculation units (9A) to (9Z), the polynomial r
_The problem is how to realize the division between _i-2 (X) and r _i-1 (X).

C ₄ Description of the conventional improved circuit for deriving an improved error locator polynomial (FIGS. 12 and 13) The division between the above-mentioned polynomials is divided and reduced to the division between the coefficients of these polynomials. An improved Euclidean algorithm based on IEEE Trans.on Computers, Vol. C-34, No. 5, M.
ay 1985, pp. 393-403.
This improved algorithm basically evolves the theorem of equation (12) so that in the i-th iterative procedure, γ _i (X) · X ^2t + λ _i (X) · S (X) = R _i (X ) Polynomials R _i (X), γ _i (X), λ satisfying ‥‥ (16)
_i (X) is sequentially calculated. And the remainder
The algorithm stops when the order of R _i (X) becomes less than the t order. This algorithm is shown in steps (106) to (114) of FIG.

Step (106) Assuming that the upper limit of the number of symbols for which error correction is possible is t, R ₀ (X), Q ₀ (X), λ ₀ (X), μ
₀ (X), γ ₀ (X) and λ ₀ (X) are represented by X ^2t , S
(X), set to 0, 1, 1 and 0.

Step (107) Step i is set to 1.

Step (108) The difference l _i-1 between the order of R _i-1 (X) and the order of Q _i-1 (X) is determined, and the maximum of R _i-1 (X) and Q _i-1 (X) is determined. The following coefficients are a
_i-1 and b _i-1 .

Step (109) Depending on the sign of the degree difference l _i−1 , if l _i−1 ≧ 0, the process proceeds to step (112) via step (110), and if l _i−1 <0, step (111) Then, the process proceeds to step (112).

Step (110) is the next number or more in the case the operation of the next communication Q _i-1 (X) (normal mode) l _i-1 ≧ 0 That _{R i-1 (X),} R i (X by the formula ), Λ _i
(X), γ _i (X) are calculated.

R _i (X) = R _i-1 (X) + (a _i-1 / b _i-1 ) Q _i-1 (X) · X ^li-1 ‥‥ (17A) λ _i (X) = λ _{i -1} (X) + (a _i-1 / b _i-1 ) μ _i-1 (X) · X ^li-1 ‥‥ (17B) γ _i (X) = γ _i-1 (X) + (a _i-1 / b _i-1 ) λ _i-1 (X) · X ^li-1 ‥‥ (17B) Also, Q _i (X) = Q _i-1 (X), μ _i (X) = μ
_i-1 (X), and _{η i (X) = η i} -1 (X). This is obtained by dividing the division R _i-1 (X) / Q _i-1 (X) by the highest order coefficient a
_i-1 / b _i-1 .

Step (111) (cross mode) This operation is performed when l _i-1 <0, that is, when the order of R _i-1 (X) is smaller than the order of Q _i-1 (X).
_{i (X), λ i (} X), to calculate the γ _i (X).

R _i (X) = Q _i−1 (X) + (b _i−1 / a _i−1 ) R _i−1 (X) · X ^−li−1 ‥‥ (18A) λ _i (X) = μ _i-1 (X) + (b _i-1 / a _i-1 ) λ _i-1 (X) · X ^-li-1 ‥‥ (18B) γ _i (X) = η _i-1 (X) + (B _i-1 / a _i-1 ) γ _i-1 · X ^-li-1 18 (18C) Also, Q _i (X) = R _i-1 (X), μ _i (X) = λ
_i-1 (X), and _{η i (X) = γ i} -1 (X). This is R
_This is equivalent to exchanging _i-1 (X) and Qi _-1 (X).

Step (112) It is checked whether or not the order of the remainder R _i (X) in the equation (16) is smaller than the t-th order. If the order of R _i (X) is smaller than the t-th order, the process proceeds to step (114). If it is equal to or greater than t, the process proceeds to step (113).

Step (113) The number of steps is incremented by 1 and the process returns to step (108).

Step (114) As final processing, λ _i (X) and R _i (X) are converted into an error locator polynomial σ (X) and an error evaluation polynomial ω (X), respectively.
In this case, i is 2t. FIG. 12 shows a specific configuration of a conventional improved error locator polynomial derivation circuit (2) for executing the algorithm of FIG. 13. In FIG. 12, (11A) to (11D) are Each is a mutual unit having the same configuration as a whole. For example, the first mutual unit (11
In (A), (12A) and (13A) indicate a pair of switch circuits, (14A) and (15A) indicate another pair of switch circuits, and input ports of these switch circuits (12A) to (15A) R ₀ (X), Q ₀ (X), λ ₀ (X) and μ ₀ (X), respectively
Supply the coefficient of When deg R ₀ (X) −deg Q ₀ (X) = 1 ₀ is 0 or positive, the switch circuits (12A) to (15A) directly transmit the coefficients supplied to the input ports to the output port side. On the other hand, when l ₀ is negative, the switch circuit (12
A) and (13A) operate so as to intersect, and switch circuits (14A) and (15A) operate so as to intersect.

The coefficient appearing at the output port of the switch circuit (12A) is supplied to the dividend input port of the divider (19A) and one input port of the adder (20A), and the coefficient appearing at the output port of the switch circuit (13A) is divided. (19A) to the divisor input port and one input port of the multiplier (23A),
The quotient first obtained by the divider (19A) is supplied to the other input port of the multiplier (23A) via the data holding register (22A), and the output of the multiplier (23A) is added to the adder ( 20A)
To the other input port. In addition, switch path (14
The coefficients appearing at the output ports of (A) and (15A) are supplied to one input port of an adder (21A) and one input port of a multiplier (24A), respectively, and the coefficients held in a register (22A) are obtained. The output is supplied to the other input port of the multiplier (24A), and the output of the multiplier (24A) is supplied to the other input port of the adder (21A).

Note that the adder, multiplier and divider of this example are all finite fields GF
(2 ^m ) is performed between elements.

Numerals (16A to 18A) denote delay registers each composed of a D-type flip-flop, and a start flag signal SF for synchronizing the input coefficient with the highest coefficient is inputted to the next stage via the register (16A). And the coefficients appearing at the output ports of the switch circuits (13A) and (15A) are converted into polynomials Q ₁ (X) and μ ₁ (X) via registers (17A) and (18A), respectively. Is supplied to the next-stage reciprocation unit (11B) as a coefficient of the adder (20A) and (21A)
The coefficients appearing at the output port of the polynomial R ₁ (X) and λ _i
It is supplied to the next-stage mutual exchange unit (11B) as a coefficient of (X). The polynomials R _i-1 (X), Q _i-1 (X), λ _i-1 (X), and μ are also input to the other mutual units (11B), (11C), and ‥‥.
The coefficients of polynomials R _i (X), Q _i (X), λ _i (X), and μ _i (X) are generated from the coefficients of _i−1 (X) in synchronization with the start flag signal SF.

In order to explain a specific application example of the circuit in the example of FIG. 12, the irreducible generator polynomial G (X) has a finite field GF of X ⁴ + X + 1.
Each symbol is represented by each element of ( ²⁴ ). That is, X ⁴
Assuming that the root of + X + 1 = 0 is α, each symbol can be represented by a power of α. If the code length n is 11 and the number of correctable symbols is t, the symbol number of the original information is 7
And the number of symbols of parity information is 2t (= 4). In this case, the vector of the original information as m, specifically when the m = ^{[α 11 α 10 α 9 α 8} α 7 α 6 α 5 ] ^t ‥‥ (19), symbols of the parity information from the formula (3) p _{0 to} p ₃
Are 0, α ¹² , α ⁶ , and α ^{11 respectively} , and f after transmission code is as follows.

f = ^{[0α 12 α 6 α 11 α 11} α 10 α 9 α 8 α 7 α 6 α 5 ]
^t ‥‥ (20) Further, if the transmission error vector e is e = [α ³ α ⁹ 000000000] ^t ‥‥ (21), there are two error symbols in the received codeword r (= f + e). . In this case, by multiplying the parity check matrix H and the received codeword r according to equation (7A), the syndrome polynomial S (X) becomes as follows: S (X) = S ₁ + S ₂ X + S ₃ X the initial value of each polynomial in the _{^{2 S 4 X 3 = α 12}} + α 5 X + α 10 X 2 + α 8 X 3 ‥‥ (22) FIG. 13 step (106) is as follows.

R ₀ (X) = X ⁴ , Q ₀ (X) = S (X) λ ₀ (X) = 0, μ ₀ (X) = 1, σ ₀ (X) = 1, η
₀ (X) = 0 As shown in FIG. 12, the coefficients of R ₀ (X) and λ ₀ (X) are supplied to the reciprocation unit (11A) in order from the higher-order (X ⁴ ) coefficient, and Q ₀ (X ) And μ ₀ (X) are supplied to the mutual elimination unit (11A) in order from the higher-order (X ³ ) coefficient, and the start flag signal SF is raised to a high level “1” in synchronization with the highest-order coefficient. .

(Operation in the mutual exchange unit (11A)) In this case, l ₀ = deg R ₀ (X) −deg Q ₀ (X) = 4-3
Since = 1.gtoreq.0, the switch counts (12A) to (15A) pass the supplied coefficients as they are. Also,
The highest order coefficients a ₀ and b _{0 of} R ₀ (X) and Q ₀ (X) are respectively 1
And for a alpha ^8, the register _{(22A) a 0 / b =} 1 / α
⁸ = alpha ⁷ is set, R ₁ (X) and X ₁ (X) becomes each follows.

R ₁ (X) = X ⁴ + α ⁷ (α ⁸ X ³ + α ¹⁰ X ² + α ⁵ X + α ¹² )
^{· X = α 2 X 3 +} α 12 X 2 + α 4 X λ 1 (X) = 0 + α 7 X = α 7 X _{Further, Q 1 (X) = Q} 0 (X), μ 1 (X) = 1, γ
₁ (X) = 1, η ₁ (X) = 0. Note that the multiplication of X ^{10, that} is, X in Expressions (17A) and (17B) is, in this example, Q _{0 in} advance.
(X) and mu ₀ their Q ₀ by the coefficient of _(X) with running by previously shifting one place to the higher-order side via register (17A) and (18A) (X) and mu
The coefficient of ₀ (X) is shifted by one digit to the lower order.

(Operation in the mutual exchange unit (11B)) Since l ₁ = deg R ₁ (X) −deg R ₁ (X) = 3-3 = 0, the switch circuits (12B) to (15B) are supplied respectively. Pass the coefficient as is. Also, R ₁ (X)
And the highest order coefficients a ₁ and b _{1 of} Q ₁ (X) are α ² and α, respectively.
Since it is ^8, in the register _{(22B) a 1 / b 1} = α 2 / α 8 =
α ⁹ is set, and R ₂ (X) and λ ₂ (X) are respectively as follows.

R ₂ (X) = R ₁ (X) + (a ₁ / b ₁ ) Q ₁ (X) = α ⁶ X ² + α ⁹ X + α ⁶ λ ₂ (X) = λ ₁ (X) + (a ₁ / b ₁ ) μ ₁ (X) = α ² X + α ⁹ Also, Q ₂ (X) = Q ₁ (X), μ ₂ (X) = 1, γ
₂ (X) = 1, η ₂ (X) = 0.

(Operation in mutual unit (11C)) l ₂ = deg R ₂ (X) −deg Q ₂ (X) = 2−3 = −1 <0
Therefore, the switch circuits (12C) and (13C) and the switch circuits (14C) and (15C) cross the coefficients of the input polynomials and transmit them to the output port side. Accordingly, the operation substantially proceeds to step (111) in FIG. And R ₂
The highest order coefficients a ₂ and b _{2 of} (X) and Q ₂ (X) are α ⁶
And α ⁸ , the register (22C) has b ₂ / a ₂ = α ⁸ /
α ⁶ = α ² is set, and R ₃ (X) and λ ₃ (X) are as follows, respectively.

R ₃ (X) = Q ₂ (X) + (b ₂ / a ₂ ) R ₂ (X) · X = α ¹⁴ X ² + α ⁴ X + α ¹² λ ₃ (X) = μ ₂ (X) + (b ₂ / a ₂ ) λ ₂ (X) · X = α ⁹ X ² + α ¹¹ X + 1 Also, Q ₃ (X) = R ₂ (X) = α ⁶ X ² + α ⁹ X + α ⁶ , μ ₃
(X) = λ ₂ (X) = α ⁷ X + α ⁹ , γ ₃ (X) = η
₂ (X) + α ² X = α ² X, η ₃ (X) = 1.

(Operation in the mutual exchange unit (11D)) Since l ₃ = deg R ₃ (X) −deg Q ₃ (X) = 2-2 = 0, the switch circuits (12D) to (15D) are supplied respectively. Pass the coefficient as is. In addition, R ₃ (X) and Q ₃
Leading coefficient a ₃ and b ₃ of (X), since a respective alpha ¹⁴ and alpha ^6, in the register (22D) is set ^{_{a 3 / b 3 = a 14}} / α 6 = α 8 is, R ₄ (X) and λ ₄ (X) are as follows.

R ₄ (X) = R ₃ (X) + (a ₃ / b ₃ ) Q ₃ (X) = α ¹⁰ X + α ⁵ λ ₄ (X) = λ ₃ (X) + (a ₃ / b ₃ ) μ ₃ (X) = α ⁹ X ² + α ¹² X + α ⁸ Also, Q ₄ (X) = Q ₃ (X), μ ₄ (X) = μ ₃ (X)
It is. In this case, since deg R ₄ (X) = 1 <2, the algorithm stops at step (112) in FIG. 13, and the error locator polynomial σ (X) and the error evaluation polynomial ω
(X) is σ (X) = λ ₄ (X) = α ⁹ X ² + α ¹² X + α ⁸ = α ⁸ (αX ² + α ⁴ X + 1) ω (X) = α ¹⁰ Xα ⁵ . In this example, since G (α) = α ⁴ + α + 1 = 0, σ (α ⁰ ) = α ⁸ (α + α ⁴ +1) = 0, σ (α ⁻¹ )
= Α ⁷ (α + α ⁴ +1) = 0 holds, and X ₁ = α ⁰ , X ₂ = α
¹ that the two error location could be accurately detected (formula (21)
reference).

As described above, the error locator polynomial can be accurately derived in principle according to the algorithm in FIG.
_{In the case} where the order of _i (X) does not decrease one by one but decreases by two or more, even if l _i−1 <0, the step (11)
The process proceeds to the normal mode of 0). Further, in the algorithm based on the Euclidean algorithm, the order of R _i (X) can in principle be reduced by only one at a time. Therefore, in a code capable of correcting t error symbols, the mutual unit in FIG. 11A), (11B), and ‥‥ require 2t.

D Problems to be Solved by the Invention When the Reed-Solomon code is used, at present, 3-symbol correction has already been realized in applications requiring real-time properties (clock frequency of about 15 MHz) such as digital VTRs. On the other hand, up to eight-symbol correction has been realized for applications such as optical disks that do not require real-time properties. Furthermore, recently, there has been a demand for the development of a decoder for a multiplex error correction code in which the number of symbols t capable of error correction is about 16 for a code length n of about 150.

However, in the above-described conventional circuit for deriving an error locator polynomial (FIG. 12), assuming that the number of correctable symbols t is 16, 2t units (11A), (11B), and ‥‥ are cascaded. Therefore, there is an inconvenience that the circuit scale increases in proportion to the number of correctable symbols t.

In view of the above, an object of the present invention is to propose a Euclidean mutual exclusion circuit that can increase the number of error-correctable symbols t and reduce the circuit size.

E Means for Solving the Problem The Euclidean mutual-commutation circuit according to the present invention converts a polynomial including a _first input polynomial R _i-1 (X) into a second input polynomial as shown in FIGS. 1 and 3, for example. The quotient and the remainder R _i (X) when divided by Q _i-1 (X) are obtained, and the quotient and the total quotient λ up to the third input polynomial λ _i-1 (X) are obtained.
_i (X), its remainder R _i (X), its first input polynomial R _i-1 (X) or second input polynomial Q _i-1 (X), and its total quotient λ _i (X ) Is the first output polynomial R
_i (X), one or a plurality of cascade-connected mutual units (43A) to (43H) which form the second output polynomial Q _i (X) and the third output polynomial λ _i (X); Input ports of the first, second and third input polynomials R _i-1 (X), Q
The initial polynomials of _i-1 (X) and λi _-1 (X) are supplied, and the output data is supplied to the one unit or one of the plurality of units (43A). Selecting means (42) and the output data of one of the mutual exchange units or the rearmost mutual exchange unit (43H) of the plurality of units
Feedback means (45) for supplying the output data to the other input port of the data selection means (42), and one or a plurality of cascade-connected reciprocal units (43A) to (43H). Delay means (44) for making the number of correctable symbols t equal to or more than 2t + 1, the time in clock pulse units required for performing the processing, and one or a plurality of cascade-connected Each of the units (43A) to (43H) is used a plurality of times.

According to the invention, the first, second and third input polynomials are initially selected by the data selection means (42).
Each of the initial polynomials (or the coefficients of the polynomials) of R _i-1 (X), Q _i-1 (X), and λ _i-1 (X) is assigned to one of the units or the first unit (43A). The supplied data is processed based on the Euclidean circuit. Then, after the supply of these initial polynomials is completed, the data selection means (42) is switched to output the output data supplied via the feedback means (45) to the one reciprocal unit or the first reciprocal unit (43A). ), It is possible to perform a process based on the Euclidean algorithm a desired number of times.

Therefore, compared with the desired number of times, the exchange unit (43
The number of A) to (43H) can be reduced to, for example, a fraction of an integer. Therefore, the overall circuit scale can be significantly reduced.

In addition, even under the condition that the data delay time in each of the mutual units (43A) to (43H) is restricted due to the requirement that the number of times of repeated use is increased as much as possible, the presence of the delay means causes a series of mutual units ( 43A) to (43H), the time per clock pulse required to perform one (one round) processing is longer than the time required to supply the initial polynomial and its coefficients (2t + 1 set). it can. Can be

Further, the number of mutual units (43A) to (43H) can be reduced to one at a minimum.

Description of mutual division unit used in the G Example G ₁ an embodiment (FIG. 14-FIG. 18) conventional improved mutual division units used in the derivation circuit of the error locator polynomial as shown in FIG. 12 (11A ) ~ (11D)
Has the following two disadvantages.

If deg R _i-1 (X) <deg Q _i-1 (X) is satisfied and the input coefficients are crossed, and the coefficient of the highest order of the R _i-1 (X) becomes 0, the divider ( A calculation error occurs because division in 19A) to (19D) cannot be performed. This is because the mutual exchange units (11A) to (11D) in FIG. 12 can always reduce the order only by one order.

Even when the highest-order coefficient of the syndrome polynomial S (X), which is the initial value Q ₀ (X) of Q _i-1 (X), is 0, the division by the divider (19A) fails, and a calculation error occurs. Occur.

In this embodiment, the exchange unit (11A) of FIG.
Since a reciprocal unit that eliminates the inconvenience of (11D) is used, the reciprocal unit used in this embodiment will be described first.

FIG. 14 shows the configuration of the mutual exchange unit (25) of this embodiment. In FIG. 14, (26) to (28) are replacement registers, respectively. These replacement registers (26), (27), (28) ) Are the start flag signal SF, the coefficient of the polynomial Q _i-1 (X),
Supply the coefficient of μ _i-1 (X). The output signal of the register (26) is a start flag signal SFO to a subsequent circuit.
(29) to (31) show switch circuits for transmitting the supplied coefficients in parallel or crosswise, respectively. Variables dR _i- indicating the degree of the polynomial to two input ports of the switch circuit (29), respectively. ₁ and d Q _i-1 are supplied to a variable appearing at one output port of the switch circuit (29) by -1 by an adder (32).
The adds generate variable d R _i, and supplies the variable d Q _i appearing at the other output port of the variable d R _i and the switching circuit (29) to a subsequent circuit.

Further, the coefficient of the polynomial R _i-1 (X) and the coefficient output from the register (27) are supplied to one and the other input ports of the switch circuit (30), respectively, and the one output port of the switch circuit (30) is supplied. Is supplied to the dividend input port of the divider (33) and one input port of the adder (34), and the coefficient appearing at the other input port of the switch circuit (30) is input to the divisor input of the divider (33). Ports and dividers (37)
To one of the input ports. A polynomial λ _{i-1 is connected to} one and the other input ports of the switch circuit (31), respectively.
The coefficient of (X) and the coefficient output from the register (28) are supplied, and the coefficients appearing at one and the other output ports of the switch circuit (31) are respectively input to one input port of the adder (35) and the multiplier ( 38) is supplied to one input port and the quotient output from the divider (33) is held in the register (36).
The held quotient is supplied to the other input port of each of the multipliers (37) and (38), and the output data of the multipliers (37) and (38) is supplied to the other of the adders (34) and (35), respectively. Supply to the input port of The output port of the adder (34), the other output port of the switch circuit (30), the output port of the adder (35), and the other output port of the switch circuit (31) are polynomials R _i (X) and Q _{i, respectively.} (X), λ _i (X) and μ
The coefficients of _i (X) are provided to subsequent circuits.

FIG. 15 shows an example in which 2t mutual exchange units (25A) to (25Z) having the same configuration as the mutual exchange unit (25) in FIG. 14 are cascaded. In FIG. 15, the first-stage mutual exchange unit (25
A) is supplied with each variable and the initial value of the polynomial (including the syndrome polynomial S (X), ^X2t, etc.), and the error locator polynomial σ (X) (= λ
_2t (X)) and the error evaluation polynomial ω (X) (= R
_2t (X)).

Referring to steps (115) to (125) of FIG. 16, an improved algorithm based on the Euclidean algorithm applied to the algorithm unit of FIG. 14 will be described. And Also, this algorithm is basically a polynomial R _i (X), γ _i (X), λ that satisfies Expression (16) in the i-th iterative procedure.
_i (X) is calculated in order, and γ _i (X)
The processing for is omitted.

Step (115) R ₀ (X), Q ₀ (X), λ ₀ (X), μ
₀ (X), dR ₀ and dQ _{0 respectively represent the} syndrome polynomial S
(X), sets the X ^2t, 1,0,2t-1 and 2T. Compared with the algorithm of FIG. 13, the initial values of R ₀ (X) and Q ₀ (X) are exchanged, and the initial values of λ ₀ (X) and μ ₀ (X) are also exchanged. According to this, since the coefficient of the highest order of X ^2t , which is the initial value Q ₀ (X) of Q _i (X), becomes 1 and the divisor can be divided by 0, the above-described conventional mutual exchange unit (11A) can be avoided. ) To (11D) can be solved.

Step (116) The number of steps i is set to one.

Step (117) The difference l _i-1 between dR _i-1 and dQ _i-1 is obtained, and dR _{i-1 of} R _i-1 (X) is obtained.
The next coefficient and dQ _{i-1 of} Q _i-1 (X) are referred to as a _i-1 and b _i-1 , respectively. In this case, since the highest order coefficient of the syndrome polynomial S (X) which is R ₀ (X) can be 0,
The value of the coefficient a _i-1 may be 0.

Step (118) Depending on the sign of the degree difference l _i−1 , if l _i−1 ≧ 0, the process proceeds to step (123) via step (119), and if l _i−1 <0, step (120) Proceed to.

Step (119) (Normal mode) This is the operation when l _i−1 ≧ 0, that is, when dR _i−1 is equal to or more than dQ _i−1 ,
R _i (X) and λ _i (X) are calculated by the following equations.

R _i (X) = R _i-1 (X) + (a _i-1 / b _i-1 ) · X · Q
_i-1 (X) ‥‥ (23A) λ _i (X) = λ _i-1 (X) + (a _i-1 / b _i-1 ) · X · μ _i-1
(X) ‥‥ (23B) Also, Q _i (X) = Q _i-1 (X), μ _i (X) = μ
_i−1 (X), dR _i = dR _i−1 −1, dQ _i = dQ _i−1 . This is obtained by replacing the division R _i-1 (X) / Q _i-1 (X) with the division a _i-1 / b _i-1 of the virtual highest-order coefficients. Equation (23A),
The reason why (a _i-1 / b _i-1 ) is multiplied by X in (23B) is that in this example, l _i-1 = dR _i-1 -dQ _i-1 is normally ± 1. This is because it is controlled.

Step (120) If a _{i-1 which} is the coefficient of order dR _{i-1 of} R _i-1 (X) is 0, the process proceeds from step (121) to step (123), where a _i-1 is 0.
If not, the process proceeds from step (122) to step (123).

Step (122) (Cross mode) This operation is performed when the order of Q _i-1 (X) is larger than the coefficient of R _i-1 (X) and the coefficient a _i-1 is not 0. By exchanging R _i-1 (X) and Q _i-1 (X) for the case, R _i (X) and λ _i (X) are
Is calculated.

R _i (X) = Q _i-1 (X) + (b _i-1 / a _i-1 ) · X · R
_i-1 (X) ‥‥ (24A) λ _i (X) = μ _i-1 (X) + (b _i-1 / a _i-1 ) · X · λ _i-1
(X) ‥‥ (24B) Q _i (X) = R _i-1 (X), μ _i (X) = λ
_i−1 (X), dR _i = dQ _i−1 −1, dQ _i = dR _{i−1 and the} process proceeds to step (123).

Step (121) (shift mode) The coefficient a _i-1 of the dR _i-1 order (highest order) of R _i (X) is 0, and the actual order of this R _i-1 (X) is (dR _{i -1} -1) Operation in the following cases. In this case, R _i-1 (X) is multiplied by X so that division by R _i-1 (X) becomes possible.
_i-1 (X) is shifted to the higher order side. That is, the following equation is established.

R _i (X) = X · R _i-1 (X) ‥‥ (25A) λ _i (X) = X · λ _i-1 (X) ‥‥ (25A) Also, Q _i (X) = Q _{i −1} (X), μ _i (X) = μ
_i−1 (X), dR _i = dR _i−1 −1, dR _i = dQ _{i−1 and the} process proceeds to step (123). In this case, since dR _i has decreased by 1, dR _i coincides with deg (R _i (X)) when the coefficient of the highest order (dR _i order) of R _i (X) becomes a value other than 0. At this time, the processing in the cross mode is performed in step (122) for the first time. As a result, the disadvantages of the mutual exchange units (11A) to (11D) in FIG. 12 are eliminated.

Step (123) It is checked whether or not the number i of steps has reached 2t. If the number of steps i has not reached 2t, the process proceeds to step (124). If the number of steps i has reached 2t, the process proceeds to step (125) as the final process.

Therefore, even when the number of error symbols is only ν (ν <t), the operation of steps (117) to (123) in FIG. 16 is always repeated 2t times as a whole in the circuit for deriving the error locator polynomial. Will be. However, one mutual unit executes steps (117) to (123) only once each. In this case, the operations of steps (117) to (123)
In the solution obtained after 2t repetitions, dR _2t represents the number obtained by subtracting 1 from the order ν of the error correction polynomial σ (X). On the other hand, the polynomial R _2t (X) is shifted to the higher order side (t−1−ν) by the operation of the shift mode in step (121).
In order to obtain σ (X) and ω (X), λ _2t (X) and R _2t (X) are respectively shifted to the lower order using a shift polynomial P (X) described later. Need to shift.

Step (124) The number of steps i is incremented by 1 and the process returns to step (117).

Step (125) As final processing, the number ν of error symbols and the shift polynomial P
(X) is calculated from the following equation.

ν = dR _2t +1 P (X) = X ^t−1 Then, using this shift polynomial P (X), an error locator polynomial σ (X) and an error evaluation polynomial ω (X) are calculated from the following equations.

σ (X) = λ _2t (X) / P (X) ‥‥ (26) ω (X) = R _2t (X) / P (X) ‥‥ (27) Mutual exchange unit (25) in FIG. 14 To explain a specific application example, as shown in FIG. 17, four mutual units (25A) to (25A) to (25A) having the same configuration as the mutual unit (25) are used.
D) is cascaded to form a circuit for deriving an error locator polynomial. In addition, each symbol is represented by each element of the finite field GF (2 ⁴ ), and the code length n is set to 11 and the number of correctable symbols t is set to 2 as in the example of FIG. f and the transmission error vector e are expressed by equations (20) and (21), respectively.

In this case, the syndrome polynomial S (X) is expressed by equation (22), and the initial values of each variable and each polynomial in step (115) in FIG. 16 are as follows.

R ₀ (X) = S (X), Q ₀ (X) = X ⁴ λ ₀ (X) = 1, μ ₀ (X) = 0, dR ₀ = 3, dQ ₀ = 4 And in FIG. As shown, the coefficients R ₀ (X) to μ ₀ (X) are supplied to the mutual exchange unit (25A) in order from the higher-order coefficient, and the values of dR ₀ and dQ ₀ are supplied to the mutual exchange unit (25A). Start flag signal synchronized with the highest order coefficient
Raise SF to high level “1”.

In the alternating unit (25A), the order difference l ₀ = dR ₀ −
dQ ₀ = 3-4 = −1 <0, and a ₀ = α ⁸ , b ₀ = 1
Therefore, the operation shifts to step (122) (cross mode) in FIG. 16, and the switch circuits (29A) to (31A) transmit the supplied variables or coefficients in an intersecting manner.
Further, b ₀ / a ₀ = 1 / α ⁸ = α ⁷ is set in the register (36A), and R ₁ (X) and λ ₁ (X) are as follows.

R ₁ (X) = X ⁴ + α ⁷ · X · (α ⁸ X ³ + α ¹⁰ X ² + α ⁵ X +
α ¹² ) = α ² X ³ + α ¹² X ² + α ⁴ Xλ ₁ (X) = 0 + α ⁷ · X = α ⁷ X Further, Q ₁ (X) = R ₀ (X) = S (X), μ ₁ (X) =
λ ₀ (X) = 1, but these results are the same as those of FIG. 12 except that the order is shifted.
Is the same as the processing result in.

Similarly, the processing results in the exchange units (25B) to (25D) in the example of FIG. 17 are respectively obtained by the exchange units (11B) to (1B) in FIG.
1D), the error locator polynomial σ (X) (= λ ₄ (X)) and the error evaluation polynomial ω (X) (= R ₄ (X)) are finally obtained. In addition,
In the example of FIG. 17, since the number t of correctable symbols and the number ν of actual erroneous symbols are both 2, the shift polynomial P (X) in step (125) in FIG. 61 is 1.

Next, the code length n is 150.
In this case, it is necessary to repeat the operations of steps (117) to (123) in FIG. 16 32 times (2t times). Therefore, simply by cascade-connecting the mutual exchange units as in the conventional example, the mutual exchange unit (25) shown in FIG.
Are required. The received code word is a clock pulse
As that is transmitted by one symbol in synchronism with CK, when one period of the clock pulse CT and 1T _c, as shown in Figure 18 A, a received codeword I of the code length of each is 0.99, II, II
I and ‥‥ are transmitted at a period of 150 _Tc . When t = 16, the highest degree of the syndrome polynomial S (X) is 31
(= 2t-1), and the number 33 of coefficients of the polynomial X ^2t (= 2t
+1). Therefore, when 32 cascade connection units (25) in FIG. 14 are simply connected in cascade as in the conventional example,
18 as shown in FIG. B, the received code word I, II, III, period of 33T _c reception completion word ‥‥ (39A), (39B) , (39C), the head of the circuits respectively the cascaded ‥‥ Are supplied with 33 pairs of coefficients of the syndrome polynomial S (X) and the polynomial X ^2t .

Assuming that one reciprocal unit requires four clock pulses (4T _c ) to process a pair of coefficients of S (X) and X ^2t , one pair of logarithms is equivalent to 32 reciprocal units each. Since 32 × 4T _c = 128T _c , the period (40A), (40B), (40C) after 128T _{c has} elapsed from the end of reception of the reception codewords I, II, III, ‥‥, respectively, ), ‥‥, the coefficients of the error locator polynomial σ (X) corresponding to the received codewords are sequentially output from the rear end mutual division unit. And 150T
_In the period IT excluding the period of 33Tc from the period of _c , no input is made to the head mutual unit, so that period IT can be considered as a kind of idle time. Therefore, in general, when the number t of symbols that can be error-corrected with respect to the code length N satisfies the relationship of N 一般 2t, simply cascading the mutual units as in the conventional example requires a large circuit scale. In addition to this, there is a disadvantage that the idle time IT becomes longer.

Description of derivation circuit of the error one polynomial G ₂ an embodiment (FIG. 1-
FIG. 4) An embodiment of the Euclidean mutual elimination circuit according to the present invention will be described below with reference to FIGS. 1 and 2. FIG. In this example, the code length n in the Reed-Solpmon code decoder is 150
The present invention is applied to a circuit (corresponding to (2) in FIG. 9) for deriving an error locator polynomial in which the number of symbols t that can be corrected by 16 is 16. Further, in this example, eight reciprocal units having the same configuration as in the example of FIG. 14 are used, and the data delay time in each reciprocal unit is equivalent to four clock pulses (4 clock pulses).
T _c ). The algorithm used in each mutual unit in this example is the same as the algorithm based on the improved Euclidean algorithm shown in FIG.

FIG. 1 shows a circuit for deriving an error locator polynomial of the present embodiment. In FIG. 1, reference numeral (41) denotes a data bus, and (42) denotes a data selector, and the syndrome polynomial S via this data bus (41). (X) and the coefficients of the polynomial X ^2t are supplied to one input port of the data selector (42). (43
A) ~ (43H) are each 14 view of mutual division unit (25) and mutual division unit of the same structure, (44) represents the delay register one clock pulse of the delay time (1T _c), the data selector (42 ) Are cascade-connected between the output ports of (3) and the input ports of the delay register (44). (45) indicates a data bus.
The output port of the delay register (44) is connected to the other input port of the data selector (42) via 5), and an error position finally obtained from a part (45a) of this data bus (45) The coefficients of the polynomial σ (X) and the error evaluation polynomial ω (X) are taken into a circuit not shown.

The operation of the example of FIG. 1 will be described with reference to FIG.
Also in this example, as shown in FIG. 2A, received codewords I, II, III, の having a code length n of 150 are transmitted at a period of 150 _Tc . In addition, since the number t of symbols for which error correction is possible is 16, the order of the syndrome polynomial S (X) is 31 (= 2t−
1) Next, S (X) and polynomial X ^2t as initial values
33 (= 2t + 1) sets of coefficients are supplied. The polynomial λ ₀ (X), μ in step (115) of FIG.
₀ (X) and variables dR ₀ , dQ ₀ are also supplied.
Therefore, until the coefficients of the initial value S (X) and X ^2t like come supplied all require 33T _c, but the delay time in each 4T _c in mutual division unit in this example (43A) ~ (43H) Since the delay time in the delay register (44) is 1 _Tc , the mutual elimination unit (43A) sends the delay register (4
The total delay time up to 4) is 33 (= 4.8 + 1) _Tc ,
The time is set equal to the time required until all the coefficients are supplied.

Therefore, in this example, as shown in FIG.
11, III, period 33T _c after the end of reception of ‥‥ (46A), (46
B), (46C), supplies 33 sets of initial data comprising such factor S (X) and X ^2t by the data selector (42) to ‥‥ the beginning of mutual division unit (43A). As a result, these three units are stored in the delay register (44) from the mutual unit (43A).
Intermediate processing data of three sets of data is stored.

Next, the data selector (42) is switched so that the data output from the delay register (44) is supplied to the head mutual exchange unit (43A). Fig. 2
C, as shown in D and E, a period of 33T _c following the period (46A) (47A), is held between the (48A) and mutual division unit (49A) (43A) and a delay register (44) The 33 sets of intermediate processing data are processed by moving one loop at a time by a loop formed by the mutual units (43A) to (43H), the delay register (44), the data bus (45), and the data selector (42). Is done. Then, as shown in FIG.
Error position polynomial from the output port of the period of 33T _c followed by A) (50A) to the data bus (45) a portion of (45a) via a delay register (44) sigma (X) and error evaluation polynomial omega (X )
Is taken out. Similarly, periods (46B), (46C),
Also in each period following ‥‥, the intermediate processing data circulates in the loop.

According to this example, the data is supplied via the data bus (41).
Each of the 33 sets of initial data goes around the loop four times, and in this loop there are eight mutual units (43A) to
Since (43H) is included, these 33 sets of initial data are equivalent to a total of 32 sets of mutual units, respectively, and the coefficients of the error locator polynomial can be accurately obtained. In this case, the conventional example requires 32 mutual units, whereas in the present example, only 1/8 of the mutual units (43A) to (43H) need to be used. There is an advantage that the size can be significantly reduced.

Further, in this example, as shown in FIG.
The coefficients of the error locator polynomial σ (X) are obtained with a delay time of 132 (= 32 × 4) _Tc after completion of reception of II, III, and 終了, respectively. it is substantially equal to the delay time than the delay time 128T _c in the case of using the method. Therefore, according to this example, there is an advantage that the delay time hardly changes even if the circuit size is reduced to 1/4. Moreover, idle time IT in this example is the time obtained by subtracting the 132T _c from 150T _c as shown in FIG. 2, it is greatly reduced as compared with the first 18 illustrated example.

The example of FIG. 1 is generalized to consider the number of mutual units required when the code length is n and the number of correctable symbols is t. In this case, the syndrome polynomial S
Since there are (2t + 1) sets of coefficients of (X) and the polynomial X ^2t , the maximum value R _{M of the} number of times a series of mutual units can be used repeatedly is R _M = int (n / ( 2t + 1)) ‥‥ (28). int (A) means an integer not exceeding A. Further, when a series of mutual units is used repeatedly R times, the number G of the exemplary units is G = int ((2t−1) / R) +129 (29). the upper limit T _U time T _CK of the clock pulse units required to perform processing once the unit (one turn) is _{T U = int ((n-} 1) / R) +1 ‥‥ (30). Furthermore, since (2t + 1) sets of initial coefficients and the like must be supplied, the lower limit T _D of the time T _CK is T _D = 2t + 1 ‥‥ (31). Therefore, the number of times R is repeatedly used from equation (29)
Is increased, the number G of the exemplary units can be reduced to one at a minimum. In this case, the delay time T _{CK is set} to T _D ≦ T _CK ≦
Forms as provided delay register for accommodating the range of T _U.

Incidentally, when n = 150 and t = 16 as shown in FIG.
R = int (150/33) = 4, G = int (31/4) + 1 = 8, T _U = i
nt (149/4) + 1 = 38, T _D = 33, and these conditions are satisfied.

The error locator polynomial or the like may be finally extracted from the connection between the mutual units (in the example of FIG. 1, for example, between the mutual units (43E) and (43F)).

More description of the specific structure of G ₃ mutual division unit (Figure 3, Figure 4) the delay time of the data in Figure 1 example 4 clock (4T _c)
(43A) to (43H) are used,
FIG. 3 shows a specific synchronous configuration example of the mutual elimination unit having a delay time of 4 _Tc , and FIG.
Portions and signals corresponding to those in the drawings are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 3, (51) to (68) denote delay registers each composed of a D-type flip-flop, and (69) to (74) denote two-input data selectors, respectively, and a pair of data selectors (69) and (69). 70), pair (71), (72) and pair (73),
(74) corresponds to the switch circuits (29), (30) and (31) in FIG. 14, respectively. (75) indicates a comparison circuit. The comparison circuit (75) has a low level “0” when dR _i −dQ _i ≧ 0 and a high level “1” when dR _i −dQ _i <0. signal
REV is generated, and the comparison signal REV is supplied to one input terminal of the AND gate (77). (76) denotes a zero detection circuit, and this zero detection circuit (76) generates a zero detection signal RZ which becomes a high level "1" only when the coefficient of the polynomial R _i-1 (X) becomes 0, This signal RZ is supplied to the other negative logic input terminal of the AND gate (77), and the output signal of the AND gate (77) is held in a register (58) to be a signal CRS. The switching of (69) to (74) is controlled.

A register (5) is connected to the input side of the data selector (71).
4) is provided, and registers (59) and (63) are provided on the output side of the data selector (71).
2) Registers are also provided before and after (74). Then, the start flag signal SF is stored in the registers (26), (51), and (52).
And the flag signals SF1, SF2, SF3 and SFO via (53)
And the register (58) is controlled by the flag signal SF1,
The registers (36), (67) and (68) are controlled by the flag signal SF3, and the other registers are controlled by the clock pulse CK. In this case, the intermediate signals are indicated by the codes shown in FIG. 3, respectively, and the variables dR _i−1 , dQ _i−1 and the polynomials R _i−1 (X) to μ _i−1
Assuming that (X) is a variable dR ₀ dQ ₀ and a polynomial R ₀ (X) to μ ₀ (X) supplied to the reciprocation unit (25A) in FIG. 17 (that is, Q _i−1 (X) = Q ₀ (X) = X ⁴ ), and each signal in FIG. 3 changes as shown in FIG. 4 in synchronization with the clock pulse CK. The frequency of this clock pulse CK is 20
MHz is assumed.

In FIG. 4, the coefficients of the polynomials R _i (X) to μ _i (X) are 4 times the coefficients of the polynomials R _i-1 (X) to μ _i-1 (X).
_Tc has been generated late. Therefore, it can be seen the delay time of FIG. 3 example is 4T _c. Note that the timing chart of FIG. 4 is a divider that divides the original between the finite field is completed within 1T _c in (33) and a multiplier (37) and an adder (34) and the finite field elements by multiplication and addition of each other are assumed to be completed within 1T _c.

G ₄ Description of another example of the mutual division unit (FIG. 5-FIG. 8) Another example of mutual division units per Referring to Figure 5 will be described. This example is a configuration example consumes 2T _c to the division of the original between the finite field, in Figure 5 where the same reference numerals are assigned to portions corresponding to the FIG. 3, first, after the register (53) Further, a delay register (88) is provided, and the registers (36) and (67) are provided by the flag signal SF4 output from the register (53).
And (68).

Further, the output port of the data selector (71) is connected to the divider (33) via the register (78), and the output port is further connected to the adder (33) via the registers (79), (80) and (59). 34), the output port of the data selector (72) is connected to the divider (33) via the register (81), and the output port is further connected to the divider (82), (83) and (60). To the multiplier (37). In this case, the registers (78) and (81) are controlled by the flag signal SF2. Similarly, a data selector (73) and an adder (35)
And registers (84), (85), and (61) between them, and registers (86), (87), and (62) at the outputs of the data selector (74) and the multiplier (38). . FIG. 6 shows a timing chart under the same conditions as those in FIG. 3 of the example of FIG. Since it takes only 1T _c to the division according to the number present embodiment, it can be seen that the delay time of the whole is 5T _c.

FIG. 7 shows a main part of an example obtained by modifying the example of FIG. 5,
In FIG. 7, pipeline processing is performed between the register (59) and the adder (34), between the register (60) and the output port, and between the multiplier (37) and the adder (34). Registers (89), (90) and (91) are provided. According to the example of FIG. 7, after the quotient is determined in the register (36),
The multiplication and the addition are reliably executed in each one clock cycle.

FIG. 8 shows a main part of an example obtained by modifying the example of FIG.
In FIG. 8, a register (94) is provided between a register (89) and an adder (34), and an original expression of a finite field is provided between the register (36) and the multiplier (37) by a vector. A matrix conversion circuit (92) and a register (9
Connect 3) and add register (95) between registers (60) and (90). The example shown in FIG.
By applying a multiplication method and a pipeline method using a finite field matrix expression disclosed in
The multiplication speed is increased.

Although the divider (33) is used in the above-described embodiment, the number of multipliers may be increased without using the divider to form the mutual division unit.

As described above, the present invention is not limited to the above-described embodiment, and may adopt various configurations without departing from the spirit of the present invention.

H Advantageous Effects of the Invention According to the present invention, since the reciprocation units can be used repeatedly, there is an advantage that the number of reciprocation units can be reduced and the entire circuit scale can be significantly reduced.

Further, even under the condition that the data delay time in each mutual unit is restricted due to the demand to increase the number of times of repeated use as much as possible, the processing is performed once by a series of mutual units due to the presence of the delay means. Can be made longer than the time required to supply all of the initial polynomial and its coefficients.

In particular, when the code length is n and the number of error-correctable symbols is t, the present invention is effective when n≫t and t is a relatively large value.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit for deriving an error locator polynomial in one embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment in FIG. 1, and FIG. 4, FIG. 4 is a timing chart for explaining the operation of the example of FIG. 3, FIG. 5 is a structural diagram showing another example of the mutual exchange unit, and FIG. 6 is an explanation of the operation of the example of FIG. FIG. 7 is a block diagram showing a main part of a modification of the example of FIG. 5, FIG. 8 is a block diagram showing a modification of the example of FIG. 7, and FIG. 9 is a decoder of an error correction code. FIG. 10 is a block diagram showing a conventional error locator polynomial derivation circuit, FIG. 11 is a flowchart showing an algorithm based on a conventional Euclidean algorithm, and FIG. 12 is an improved conventional circuit. Configuration diagram showing a derivation circuit of the error locator polynomial,
FIG. 13 is a flowchart showing an algorithm according to a conventional improved Euclidean algorithm, FIG. 14 is a block diagram showing an algorithm unit used in one embodiment of the present invention, and FIG. 15 is an example of FIG. FIG. 16 is a block diagram showing a connection example of a conventional system, FIG. 16 is a flowchart showing an algorithm of an improved Euclidean algorithm used in an embodiment of the present invention, and FIG.
FIG. 17 is a block diagram showing a circuit for deriving an error locator polynomial constructed by connecting the example of FIG. 14 by a conventional method, and FIG. 18 is a timing chart for explaining the operation of the conventional method. (33) is a divider, (34) and (35) are adders, (3
7) and (38) are multipliers, (42) is a data selector,
(43A) to (43H) are mutual units, (44) is a delay register, (45) is a data bus for data feedback, (6)
9) to (74) are data selectors, (75) is a comparison circuit, and (76) is a zero detection circuit.

Continuation of front page (56) References JP-A-63-316525 (JP, A) JP-A-3-195217 (JP, A) JP-A-63-164629 (JP, A) JP-A-63-164627 (JP) , A) JP-A-63-164625 (JP, A) IEEE Trans. on Com p. , Oct. 1989, Vol. 38, No. 10, p. 1473-1478 (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 13/00-13/22

Claims (1)

(57) [Claims] 1. A quotient and a remainder R _i (X) when a polynomial including a _first input polynomial R _i-1 (X) as a factor is divided by a second input polynomial Q _i-1 (X) are obtained. And the total quotient λ _i (X) from the above quotient and the third input polynomial λ _i-1 (X).
, The remainder R _i (X), the first input polynomial R _i-1
(X) or one that forms the second input polynomial Q _i-1 (X) and the entire quotient λ _i (X) as a first output polynomial, a second output polynomial, and a third output polynomial, respectively. A plurality of cascade connected units, and one of the input ports having the first, second, and third input polynomials R _i-1 (X), Q _i-1 (X), and λ _i-1 (X ), Data output means for supplying each initial polynomial and supplying output data to the one decryption unit or the first decryption unit among the plurality, and output data of the one decryption unit or the plurality of data. Feedback means for supplying the output data of the rear end mutual unit to the other input port of the data selecting means; and one or more cascade-connected mutual units.
And delay means for making the number of correctable symbols t equal to or more than 2t + 1, the time in clock pulse units required for performing the processing one or more times. A Euclidean mutual exchange circuit characterized by using a plurality of times each.