JP3157741B2 - Binary-decimal conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a binary-decimal conversion circuit in an information processing apparatus, and more particularly to a binary-decimal conversion circuit having an improved conversion speed.

[0002]

2. Description of the Related Art In a conventional binary-decimal conversion circuit,
For example, conversion is performed by checking each bit of binary data bit by bit as in the technique described in Japanese Patent Application Laid-Open No. 59-168543.

FIG. 7 is a block diagram showing this conventional technique. Referring to FIG. 7, this binary-decimal conversion circuit includes a binary data selector 11 and a binary data register 1.
2, decimal adder 13 and decimal data register 14
It is composed of

The binary data 000 to be converted and the data 300 obtained by shifting the binary data register 12 to the left by one bit are input to the binary data selector 11, and the output 100 of the binary data selector 11 is input to the binary data register 12. type in,
The output 500 of the decimal data register 14 is input to both inputs of the decimal adder 13, the most significant bit 200 of the binary data register 12 is input to the carry input of the decimal adder 13, and the decimal adder 13 is input to the decimal data register 14.

[0005] First, binary data 000 to be converted is transferred to a binary data register 12 via a binary data selector 11.
And reset the decimal data register 14 at the same time.

Next, the most significant bit 200 of the binary data register 12 and the data 500 of the decimal data register 14
Is added by the decimal adder 13 to add the multiple of the value 500 of the decimal data register 14 and the most significant bit 200 of the binary data register 12. Also,
The output 400 of the decimal adder 13 is stored in the decimal data register 14, and at the same time, the data 300 obtained by shifting the data of the binary data register 12 to the left by one bit is transferred via the binary data selector 11 to the binary data register 12. To be stored.

This operation is repeated by the number of bits of binary data, thereby performing binary-decimal conversion.

[0008]

SUMMARY OF THE INVENTION The above-described conventional binary 1
In the zero-ary conversion circuit, assuming that the binary data has n (positive integer) bits, the arithmetic circuit is required to perform an addition operation n times. For this reason, there is a disadvantage that the execution time required for the binary-decimal conversion is increased, which causes a reduction in the operation speed and an increase in the processing time.

An object of the present invention is to improve the problems of the prior art by utilizing the characteristics of the decimal data and adding a few circuits to the conventional binary / decimal conversion circuit. It is to provide a base conversion circuit.

[0010]

SUMMARY OF THE INVENTION A first binary 10 according to the present invention.
The decimal conversion circuit has a decimal adder having two data inputs for adding decimal data and a carry input, and a decimal double generation circuit for generating double data of the decimal data. The output of the binary doubling generation circuit is input to the upper part of the two data inputs of the decimal adder, and the upper bit of the two bits of the binary data to be converted is converted to the 10th bit.
The lower input of the two data inputs of the decimal adder, the lower bit of the two bits of the binary data to be converted is input to the carry input of the decimal adder, and the binary data to be converted is It is converted into a decimal number every two bits.

A second binary-decimal conversion circuit according to the present invention comprises:
(A) a binary data register for holding binary data;
(B) a binary data selection circuit for selecting either binary data to be converted or data obtained by shifting the output of the binary data register to the left by 2 bits, and outputting the selected data to the binary data register; A decimal data register for storing decimal data converted from the binary data to be converted into decimal data; and (d) a decimal double number for generating data of a double of the output of the decimal data register. A generation circuit, and (e) inputting the output of the decimal double generation circuit to the upper part of two data inputs, and inputting the upper bit of the upper two bits of the binary data register to the lower part of the two data inputs Inputting the lower bit of the upper two bits to the carry input of the decimal adder;
By performing a decimal addition of a quadruple number of the output of the binary data register and the upper 2 bits of the binary data register,
The conversion target binary data is converted into the decimal data every two bits and output to the decimal data register.
And a binary adder.

A third binary-decimal conversion circuit according to the present invention is the second binary-decimal conversion circuit, wherein the binary data register, the binary data selection circuit, and the decimal data A register, the decimal double number generation circuit,
It is composed of one chip including a zero-base adder.

[Operation] Since the binary-to-decimal conversion is performed every two bits using a double data generation circuit for decimal data and a decimal adder, if the binary data is n (positive integer) bits, Conversion to decimal data can be performed by n / 2 addition operations. For this reason, the execution time is reduced to one half of that of the conventional art, and it is possible to easily realize an increase in the operation speed and a reduction in the processing time.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG.
The binary-decimal conversion circuit according to the present invention includes a binary data selector 1
1 and binary data register 12 and decimal adder 13
, A decimal data register 14 and a decimal double number generation circuit 15. Also, conversion target binary data 0
00 and data 300 obtained by shifting the data of the binary data register 12 to the left by 2 bits are input to the binary data selector 11. Also, the output 100 of the binary data selector 11
Is input to the binary data register 12, the output 500 of the decimal data register 14 is input to the decimal double generation circuit 15, and the output 600 of the decimal double generation circuit 15 (the least significant bit 0 of the double is Excluding data) is input to bits other than the least significant 1 bit of both inputs of the decimal adder 13, and the most significant 1 bit 200 of the binary data register 12 is input.
Is input to the least significant bit of both inputs of the decimal adder 13, the next bit 201 of the most significant 1 bit of the binary data register 12 is input to the carry input of the decimal adder 13, and The output 400 of the adder 13 is input to the decimal data register 14. FIG. 2 is a block diagram of the decimal double generation circuit 15 of FIG. Referring to FIG.
The 0-ary double generation circuit 15 generates j-digit (j is a positive integer) decimal data d0 (0), d0 (1), d0 (2), d0 (3),.
-Di-1 (0), di-1 (1), di-1 (2),
di-1 (3), di (0), di (1), di
(2), di (3), di + 1 (0), di + 1
(1), di + 1 (2), di + 1 (3),..., D
j-1 (0), dj-1 (1), dj-1 (2), dj
-1 (3) from the decimal double data D-1 (3), D0 (0), D0 (1), D0 (2),
D0 (3) ... Di-1 (0), Di-1 (1), D
i-1 (2), Di-1 (3), Di (0), Di
(1), Di (2), Di (3), Di + 1 (0), D
i + 1 (1), Di + 1 (2), Di + 1 (3),.
·, Dj-1 (0), Dj-1 (1), Dj-1
(2), so as to generate Dj-1 (3)
24 (they all have the same configuration). FIG. 3 is a circuit diagram of the one-digit decimal double generation circuit 20 shown in FIG.
24 to 24 are detailed circuit diagrams. FIG. 4 is a conversion table of the one-digit decimal double number generation circuits 20 to 24. As shown in FIG. 4, since one digit of the decimal data is from "0" to "9", its double number is from "0" to "18", and the conversion digit of the decimal double number generation result. Least significant bit D of
(3) is always "0". FIG. 5 is a conversion table in units of one digit of the decimal double generation circuit 15 of FIG.
In the generation of a decimal double number of a plurality of decimal numbers, one bit is generated from the lower digit, but as described with reference to FIG. 4, the least significant bit of each digit is doubled to “0”. Therefore, one bit of carry from the lower digit can be directly input.

Therefore, any one digit di (0), di (1), di (2), di (3) of a j-digit (j is a positive integer) decimal number is converted to a decimal double Di-1 ( 3), Di (0), Di (1), Di
(2), when converting to Di (3) (i is a positive integer from 0 to j-1), Di-1 (3) = di (0) + di (1) * (di
(2) + di (3)) Di (0) = di (0) * di (3) + di (1) * d
i (2) '* di (3)' Di (1) = di (0) * di (3) '+ di (1)'
* Di (2) + di (2) * di (3) Di (2) = di (0) '* di (1)' * di (3)
+ Di (1) * di (2) * di (3) ′ + di (0)
* Di (3) ′ (where “*” is a logical product,
“+” Indicates a logical sum, and “′” indicates an inversion (complement).

Thus, by connecting the decimal double-number generating circuit 20 of FIG. 3 in parallel with the decimal single-digit generating circuit 20 as shown in FIG.
A decimal doubling of a decimal number can be generated.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a state transition table showing the operation of converting binary data “1110010000110110” into decimal data, showing the output value of each component circuit for each operation cycle. First, the binary data 000 to be converted is loaded into the binary data register 12 via the binary data selector 11, and at the same time,
The binary data register 14 is reset.

Next, from the data 500 of the decimal data register 14, a decimal double number generating circuit 15 generates decimal double number data 600 (data excluding the least significant bit). Most significant 1 bit 20 of binary data register 12
0, the next bit 201 of the most significant bit of the binary data register 12 (that is, the most significant two bits of the binary data register 12), and the output 6 of the decimal double generation circuit 15
00 and the decimal adder 13 add 10
A quadruple generation of the value of the binary data register 14 and addition of the two most significant bits of the binary data register 12 are performed.

The output 400 of the decimal adder 13 is 1
At the same time as the data 300 is stored in the binary data register 14, the data 300 obtained by shifting the data of the binary data register 12 to the left by 2 bits is stored in the binary data register 12.

By repeating this operation for half the number of bits of the binary data, binary data 0 to be converted is obtained.
00 is converted to decimal data 900 in a binary-decimal manner. Thus, according to the present invention, the binary data "11100"
10000111010 ”to decimal data“ 5842 ”
The operation of converting to 2 "can be realized with half the number of cycles of the bit number of the binary data to be converted.

[0021]

As described above, according to the present invention, by converting n-bit binary data into decimal data in units of 2 bits, the number of operations required in the past becomes n / 2 times. This has the effect that the calculation speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a decimal double generation circuit of FIG. 1;

FIG. 3 is a circuit diagram of a single-digit decimal double generation circuit.

FIG. 4 is a conversion table of a one-digit decimal double number generation circuit.

FIG. 5 is a conversion table of a multiple-digit decimal double generation circuit.

FIG. 6 is a state transition table of conversion in a decimal double number generation circuit.

FIG. 7 is a block diagram showing a conventional binary-decimal conversion circuit.

[Explanation of symbols]

 11 Binary data selector 12 Binary data register 13 Decimal adder 14 Decimal data register 15 Decimal doubling number generation circuit 20 to 24 1 digit decimal doubling number generation circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-61333 (JP, A) JP-A-53-78133 (JP, A) JP-A-59-139443 (JP, A) JP-A-59-139443 177645 (JP, A) JP-A-60-169229 (JP, A) JP-A-61-251331 (JP, A) JP-A-3-13011 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 7/12

Claims (3)

(57) [Claims] A decimal adder having two data inputs for adding decimal data and a carry input; and a decimal double generation circuit for generating data of a double of the decimal data. The output of the binary doubling generation circuit is input to the upper part of the two data inputs of the decimal adder, and the upper bit of the two bits of the binary data to be converted is converted to the 10th bit.
The lower input of the two data inputs of the decimal adder, the lower bit of the two bits of the binary data to be converted is input to the carry input of the decimal adder, and the binary data to be converted is A binary-to-decimal conversion circuit for converting into a decimal number every two bits. 2. Select one of (a) a binary data register for holding binary data, and (b) binary data to be converted and data obtained by shifting the output of the binary data register to the left by 2 bits. Output to the binary data register
(C) storing decimal data converted from the binary data to be converted into decimal data;
A zero-decimal data register, (d) a decimal double-number generating circuit for generating data of a decimal double of the output of the decimal data register, and (e) an output of the decimal double-number generating circuit as two data. Input to the upper part of the input; input the upper bit of the upper two bits of the binary data register to the lower part of the two data inputs; and input the lower bit of the upper two bits to the carry of the decimal adder. Input to the input, a quadruple of the output of the decimal data register and the 2
A decimal adder for converting the binary data to be converted into the decimal data every two bits by performing a decimal addition with the upper two bits of the decimal data register, and outputting the converted data to the decimal data register; 2 characterized by having
Decimal-decimal conversion circuit. 3. The binary data register, the binary data selection circuit, the decimal data register,
1 including a zero-ary double generation circuit and the decimal adder
3. The device according to claim 2, wherein the device comprises a chip.
Decimal-decimal conversion circuit.