JP3361654B2 - Data transmission equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device having a transmission device and a plurality of reception devices and having a function of transmitting data from the transmission device to a specific reception device.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a transmission frame exchanged in a conventional data transmission device, which is referred to as a reference "Digital type protective relay and protective relay (power standard B-40.
2) (The Federation of Electric Power Companies of Japan) ”is a configuration diagram showing an outline of the transmission frame. In FIG. 6, F is a frame synchronization signal indicating the start of the transmission frame 61, D is a data part indicating message information, and CRC is an error detection for confirming whether the data part D is correctly sent to the other party. It is an error check code indicating a code.

FIG. 7 is a block diagram showing the configuration of a conventional data transmission device. In FIG. 7, reference numeral 1 is a transmitter for transmitting data to a specific partner, and reference numerals 2 and 3 are receivers for receiving a transmission frame 61 from the transmitter 1. Transmitter 1
11 is a frame synchronization generation unit for generating the frame synchronization signal F, 12 is a data unit generation unit for generating the data unit D of arbitrary bits, and 13 is the error check code CR.
An error verification code generation unit for generating C, a parallel / input 14 for inputting the frame synchronization signal F, the data section D, and the error verification code CRC in a parallel format, and outputting after serial conversion.
It is a serial conversion unit. In the receiving device 2, 21 is a frame synchronization determination unit that determines whether or not the frame synchronization signal F has a desired bit pattern, 22 is a data unit reception unit that receives the data unit D, and 23 is a transmission error of the data unit D. An error detection unit for detecting 24 is a serial / parallel conversion unit for converting the serial transmission frame 61 into a parallel format. Although the above configuration has been described for the receiving device 2, the other receiving devices 3 and the like have the same configuration.

Next, the operation will be described. In the transmitter 1 of FIG. 7, the frame synchronization generation unit 11 generates
The output frame synchronization signal F, the data part D of an arbitrary bit generated and output by the data part generator 12, and the error generated and output from the data part D by the error test code generator 13 using a generator polynomial or the like. Verification code CRC
Is input to the parallel / serial conversion unit 14 in parallel format. Next, the parallel / serial conversion unit 14 converts this parallel format data into a serial format and transmits the transmission frame 61 shown in FIG. 6 to the receiving device 2. Next, in the serial / parallel converter 24 in the receiving device 2 which has received the transmission frame 61, the serial transmission frame 61 is converted into the parallel format, and the frame synchronization signal F is sent to the frame synchronization determination unit 21 and the data unit. D is output to the data unit reception unit 22 and the error check code CRC is output to the error detection unit 23. Next, the frame synchronization determination unit 21 confirms that the frame synchronization signal F has a desired bit pattern. If the frame sync signal F does not have a desired bit pattern, the hunting for frame sync is performed again. Next, the error detector 2
In 3, the error check code CRC, the data part D, the generator polynomial, etc. are used to check whether the transmitted data part D has an error. At this time, if there is no error in the sent data part D, the input data part D is processed as valid data, but if an error is detected, the input data part D is made invalid data. Although the above operation has been described for the transmission to the receiving device 2, the same operation is performed for the transmission to the other receiving device 3 and the like.

[0005]

The transmission frame of the conventional data transmission apparatus as described above is configured as shown in FIG. 6, but in FIG. 7, the transmission frame is transmitted from the transmission apparatus 1 to the reception apparatus 2. When the receiving device 3 erroneously receives the transmission frame due to the incorrect connection of the transmission path or the like, the error detecting unit 23 cannot confirm that the transmission frame is the transmission frame for the receiving device 2 for this transmission frame. However, there is a problem that the receiving device 3 operates as if it were the receiving device 2. Therefore, like the conventional data transmission apparatus shown in FIG. 8, the transmitting apparatus 1 is provided with an address setting section 19 for setting the address section of the transmission partner, and the receiving apparatus 2 and 3 are provided with the address section transmitted from the transmitting apparatus 1. Is provided and an address determination unit 29 for determining whether or not this address is a self address is provided, and as shown in FIG. 9, the number of bits of the transmission frame 91 is increased to indicate the address of the receiving device of the transmission destination. There is also a method of inserting the address portion A into the transmission frame 91, but there is a problem that it is necessary to reduce the number of bits of the transmission frame as much as possible because the transmission delay time becomes longer as the number of bits of the transmission frame increases. .

The present invention has been made to solve the above problems, and for example, the transmission frame 9 shown in FIG.
By deleting the address part A in 1, the data transmission device capable of reducing the number of bits and shortening the transmission delay time of the transmission frame (increasing the transmission efficiency) compared to the transmission frame 91 of FIG. 9 is provided. The purpose is to do.

[0007]

According to a first aspect of the present invention, a transmitting side address recognition code setting switch 15 for setting an address recognition code corresponding to an address of a receiving destination receiving apparatus 2 in a transmitting apparatus 1 and this transmitting side. An exclusive OR circuit 16 that inputs the address recognition code set by the address recognition code setting switch 15 and the data section generated by the data section generation section 12 and performs an exclusive OR is provided, and the frame synchronization generation section 11 is provided. From the frame sync signal from the exclusive OR circuit 16
Output signal and the error check code from the error check code generator 13 are input to the parallel / serial converter 14, and the address recognition code corresponding to the address of the receiver 2 is set in the receiver 2. An exclusive OR for inputting the receiving side address recognition code setting switch 25 and the address recognition code set by the receiving side address recognition code setting switch 25 and the data section from the serial / parallel conversion section 24 to obtain an exclusive OR. An OR circuit 26 is provided, and the output signal of the exclusive OR circuit 26 is input to the data section receiving section 22 and the error detecting section 23.

A second aspect of the present invention is to set a transmission side address recognition code setting switch 15 for setting an address recognition code corresponding to an address of a receiving destination receiving apparatus 2 in the transmission device 1, and this transmission side address recognition code setting switch 15 An exclusive OR circuit 16 that inputs the address recognition code and the error check code generated by the error check code generator 13 set in step 3 and performs an exclusive OR is provided, and the frame synchronization from the frame synchronization generator 11 is provided. The signal and the data part from the data part generation part 12 and the output signal of the exclusive OR circuit 16 are parallel /
The receiving side address recognition code setting switch 25 for setting the address recognition code corresponding to the address of the receiving device 2 in the receiving device 2 and the receiving side address recognition code setting switch Address recognition code and serial / set in 25
An exclusive OR circuit 26 for taking an exclusive OR by inputting the error test code from the parallel conversion section 24 is provided, and an output signal of the exclusive OR circuit 26 and a data section from the serial / parallel conversion section 24. Is input to the error detection unit 23.

A third aspect of the present invention is a transmission side address recognition code setting switch 15 for setting an address recognition code corresponding to the address of the reception destination device 2 of the transmission destination in the transmission apparatus 1, and this transmission side address recognition code setting switch 15 An exclusive OR circuit 16 for inputting the address recognition code set in 1. and the frame synchronization signal generated by the frame synchronization generation unit 11 and performing an exclusive OR is provided, and an output signal of the exclusive OR circuit 16 is provided. And the data part from the data generator 12 and the error setting code from the error check code generator 13 are input to the parallel / serial converter 14,
A receiving side address recognition code setting switch 25 for setting an address recognition code corresponding to the address of the receiving apparatus 2 in the receiving apparatus 2, and an address recognition code and serial / parallel set by the receiving side address recognition code setting switch 25. And an exclusive OR circuit 26 that inputs the frame synchronization signal from the conversion unit 24 and takes an exclusive OR.
The output signal of the exclusive OR circuit 26 is input to the frame synchronization determination unit 21.

The fourth invention is characterized in that the transmitting side address recognition code setting means and the receiving side address recognition code setting means are respectively constituted by mechanical switches 15 and 25.

In a fifth aspect of the invention, the transmitting side address recognition code setting means and the receiving side address recognition code setting means are storage elements 17 such as a ROM storing the address recognition code,
27 and an address setting unit 1 for setting an address for reading the address recognition code from the storage elements 17, 27.
It is characterized in that it is configured by including 8 and 28, respectively.

[0012]

In the first aspect of the present invention, in the transmitter 1, the address recognition code set by the transmission side address recognition code setting switch 15 and the data section generated by the data section generation section 12 are exclusive by the exclusive OR circuit 16. The logical sum is calculated and input to the parallel / serial conversion unit 14. The frame synchronization signal from the frame synchronization generation unit 11, the output signal of the exclusive OR circuit 16 and the error verification code from the error verification code generation unit 13 are converted into serial signals by the parallel / serial conversion unit 14 and transmitted. . The reception device 2 receives the transmission signal from the transmission device 1, and the serial / parallel conversion unit 24 converts the transmission signal into a parallel signal. The frame synchronization signal from the serial / parallel conversion unit 24 is input to the frame synchronization determination unit 21 and it is determined whether or not it has a desired bit pattern. Further, the data section from the serial / parallel conversion section 24 and the address recognition code from the reception side address recognition code setting switch 25 are exclusive ORed by the exclusive OR circuit 26 and received by the data section reception section 22. It In addition, the serial / parallel converter 2
The error check code from 4 and the data section from the exclusive OR circuit 16 are input to the error detection section 23, and it is determined whether or not the transmitted data section is correct.

In the second aspect of the invention, in the transmitter 1, the address recognition code set by the transmission side address recognition code setting switch 15 and the error verification code generated by the error verification code generation unit 13 are processed by the exclusive OR circuit 16. The exclusive OR is calculated and input to the parallel / serial conversion unit 14. The frame synchronization signal from the frame synchronization generation unit 11, the data unit from the data unit generation unit 12, and the output signal of the exclusive OR circuit 16 are converted into serial signals by the parallel / serial conversion unit 14 and transmitted. The reception device 2 receives the transmission signal from the transmission device 1, and the serial / parallel conversion unit 24 converts the transmission signal into a parallel signal.
The frame synchronization signal from the serial / parallel conversion unit 24 is input to the frame synchronization determination unit 21 and it is determined whether or not it has a desired bit pattern. The data section from the serial / parallel conversion section 24 is the data section reception section 22.
And is input to the error detection unit 23. Also, serial /
The error check code from the parallel conversion section 24 and the address recognition code set by the receiving side address recognition code setting switch 25 are exclusive ORed by the exclusive OR circuit 26, input to the error detection section 23, and transmitted. It is determined whether or not the received data section is correct.

In the third invention, in the transmitter 1, the address recognition code set by the transmission side address recognition code setting switch 15 and the frame synchronization signal generated by the frame synchronization generator 11 are exclusive by the exclusive OR circuit 16. The logical OR is calculated and input to the parallel / serial conversion unit 14. The output signal of the exclusive OR circuit 16, the data part from the data part generator 12, and the error check code from the error check code generator 13 are converted into serial signals by the parallel / serial converter 14 and transmitted. The reception device 2 receives the transmission signal from the transmission device 1, and the serial / parallel conversion unit 24 converts the transmission signal into a parallel signal. The frame synchronization signal from the serial / parallel conversion unit 24 and the address recognition code set by the receiving side address recognition code setting switch 25 are exclusive ORed by the exclusive OR circuit 26 and input to the frame synchronization determination unit 21. Is
It is determined whether the frame synchronization signal has a desired bit pattern. In addition, the serial / parallel converter 24
The data section from is input to the data section receiving section 22 and the error detecting section 23. In addition, the serial / parallel converter 2
The error check code from 4 is input to the error detection unit 23, and it is determined whether the transmitted data part is correct.

In the fourth invention, by operating the switch 15, the transmission side address recognition code is set,
By operating the switch 25, the receiving side address recognition code is set.

In the fifth invention, the address setting section 18
When the address is set by, the transmission side address recognition code corresponding to the address is read from the storage element 17. When the address is set by the address setting unit 28, the receiving side address recognition code corresponding to the address is read from the storage element 27.

[0017]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data transmission device according to an embodiment of the present invention. In FIG.
The same reference numerals are given to those corresponding to the components shown in
The description is omitted. In the first embodiment, the transmission side address recognition code setting switch 15 as the transmission side address recognition code setting means for setting the transmission side address recognition code corresponding to the addresses of the reception destination devices 2 and 3 in the transmission device 1.
And exclusive-OR gates 16a to 16c for taking an exclusive-OR by inputting the address recognition code set by the transmission side address recognition code setting switch 15 and the data part generated by the data part generation part 12. An exclusive OR circuit 16 is provided, and the frame synchronization signal from the frame synchronization generation unit 11, the output signal of the exclusive OR circuit 16 and the error verification code from the error verification code generation unit 13 are parallel / serial conversion unit 14. And a receiving side address recognition code setting switch 25 as receiving side address recognition code setting means for setting an address recognition code corresponding to the address of the receiving apparatus 2 in the receiving device 2.
Exclusive logic having exclusive OR gates 26a to 26c for inputting the address recognition code set by the receiving side address recognition code setting switch 25 and the data section from the serial / parallel conversion section 24 and taking an exclusive OR And an output circuit of the exclusive OR circuit 26 is input to the data section reception section 22 and the error detection section 23. The other receiving devices 3 and the like have the same configuration as the receiving device 2.

FIG. 2 is a block diagram showing an outline of a transmission frame transmitted by the data transmission apparatus of the first embodiment.
In FIG. 2, F is a frame synchronization signal indicating the start of the transmission frame 31, and is generated by the frame synchronization generation unit 11. D is a data part indicating message information, which is generated by the data part generation unit 12. The CRC is an error detecting code indicating an error detecting code for confirming whether or not the data part D is correctly sent to the other party, and is generated by the error detecting code generating section 13.

Next, the operation of the first embodiment will be described.
In FIG. 1, the operations of the frame synchronization generation unit 11, the data unit generation unit 12, the parallel / serial conversion unit 14, the frame synchronization determination unit 21, the data reception unit 22, and the serial / parallel conversion unit 24 are shown in FIG. Since it has been described above, detailed description will be omitted here. First, the transmitter 1
Then, the error check code generating section 13 generates an error check code which is a code for error detection from the input data part D. As a method of generating this error test code, when a generator polynomial is used as an example, the data part D is represented by a predetermined number, for example, “11001” in binary notation.
Divide by. At this time, the remainder generated by the division is the error check code. However, the division referred to here is not division by normal arithmetic but division of XOR with no carry. Sender address recognition code setting switch 15
In step 1, an address recognition code suitable for being inserted into the transmission frame corresponding to the address of the receiving device 2 which is the transmission destination is set. For example, if this address is displayed in binary, "1
If it is "0", the address recognition code corresponding to this address is displayed as "000000000000" in binary.
11 (most left bit is most significant bit, 0 = 1ow, 1 = h
)) ”. The specific bit of the address recognition code and the specific output signal of the data section generation unit 12 are input to each of the exclusive OR gates 16a to 16c. The combination of inputs to each of the exclusive OR gates 16a to 16c is such that the most significant bit of the address recognition code and the most significant bit of the data part generation unit 12 are input to the exclusive OR gate 16a, and the following The bit is input to the exclusive OR gate 16b, and similarly to each exclusive OR gate, and finally, the least significant bit of the address recognition code and the least significant bit of the output signal of the data section generation unit 12 are input. It is input to the exclusive OR gate 16c. Therefore, in the above example, the lower 2 bits of the output signal of the data part generation part 12 are determined, and this is output to the parallel / serial conversion part 14 as the data part D.

In the receiver 2, the receiving side address recognition code setting switch 25 sets the same address recognition code as the address recognition code set by the transmitting side address recognition code setting switch 15. The specific bit of the address recognition code and the specific bit of the data section D from the serial / parallel conversion section 24 are exclusive OR gates 26a ...
26c. This exclusive OR gate 26a-2
The combination of inputs to each of 6c is such that the most significant bit of the address recognition code and the most significant bit of the data section D are inputted to the exclusive OR gate 26a, and the next upper bits are inputted to the exclusive OR gate 26b. Then, the same is input to each exclusive OR gate, and finally, the least significant bit of the address recognition code and the least significant bit of the data part D are input to the exclusive OR gate 26c. Therefore, in the above example, the lower 2 bits of the data part D from the serial / parallel converter 24 are re-inverted. Accordingly, the exclusive OR gates 26a to 26c are connected to the error detection unit 23.
The signals inputted to the exclusive OR gates 16a to 16
It becomes the same bit string as the signal before being inverted in c.
The error detector 23, which receives this bit string, detects a transmission error from the input bit string and the error detection code CRC in FIG. As a method of detecting this transmission error, taking a case where a generator polynomial is used as an example, a bit string "1100" in which a bit string in which the data part D and the error detection code CRC are connected is used in the error check code generation part 13 is used.
Divide by the same bit example as "1". At this time, if the remainder generated by division is 0, there is no transmission error, and if the remainder is not 0, there is a transmission error. However, the division referred to here is not division by normal arithmetic but division of XOR with no carry. As a condition that the remainder becomes 0, the output signal from the data part generation part 12 and the bit string input from the exclusive OR gates 26a to 26c to the error detection part 23 must be the same. Therefore, if the address recognition code set by the transmission side address recognition code setting switch 15 and the address recognition code set by the reception side address recognition code setting switch 25 are different,
Since the bit positions to be inverted are different between the exclusive OR gates 16a to 16c and the exclusive OR gates 26a to 26c, the remainder in the error detection unit 23 is not necessarily 0, and the transmission error is detected. For example, if the receiving device 3 is not the transmission destination of the transmitting device 1, a transmission error is detected and the received data portion D is set as invalid data.

By thus inserting the address of the transmission destination into the data section D, the transmission destination can be discriminated without using the address section for determining to which receiving apparatus the transmission is performed. The number of bits corresponding to the address portion of the frame can be reduced, and the reduction in the number of bits can reduce the transmission delay time of the transmission frame (increase the transmission efficiency).

The operation of the first embodiment has been described for the transmission to the receiving device 2, but the same operation is performed for the transmission to the other receiving device 3 and the like. Further, in the first embodiment, the specific 2 bits are inverted in the data part D, but the same effect can be obtained even if all the bits other than the specific 2 bits are inverted in the data part D. Also,
This specific number of bits does not have to be 2 bits, and can be set to the number of bits according to the error detection level (inter-code distance). Further, in the first embodiment, the transmission frame of FIG. 2 has been described, but the same effect can be obtained even with a transmission frame including an address part.

Example 2. 3 is a block diagram showing the configuration of a data transmission device according to a second embodiment of the present invention. In the first embodiment described above, the case where the address of the transmission destination is inserted into the data section D to reduce the number of bits of the transmission frame has been described, but in the second embodiment, as shown in FIG. In order to insert the address of the transmission destination (see FIG. 2), in the transmission device 1, one input of each of the exclusive OR gates 16a to 16c is connected to the error check code generation unit 13.
The output of each of the exclusive ORs is input to the parallel / serial converter 14 as the error check code CRC, and the output from the data part generator 12 as the data part D. Is configured. Further, in the receiving device 2, each exclusive OR gate 26
One of the inputs a to 26c is connected to the serial / parallel converter 2
4, the error check code CRC is output, the output of each exclusive OR is input to the error check unit 23, and the data section D output from the serial / parallel converter 24 is directly input to the data section receiver 22. Is configured to.
Although the above configuration has been described for the receiving device 2, the other receiving devices 3 and the like have the same configuration.

Next, the operation of the second embodiment will be described.
In FIG. 3, in the transmitter 1, the address recognition code setting switch 15 on the transmitter side is set to the receiver 2 which is the destination.
The address recognition code corresponding to the address of is set. For example, if this address is “10” in binary notation, the address recognition code corresponding to this address is 2
Set in decimal notation as “00000000000011 (leftmost bit is most significant bit, 0 = 1ow, 1 = high)”. The specific bit of the address recognition code and the specific bit of the error verification code which is the code for error detection output from the error verification code generation unit 13 are input to the exclusive OR gates 16a to 16c. The combination of inputs to each of the exclusive OR gates 16a to 16c is such that the most significant bit of the address recognition code and the most significant bit of the error detection code are input to the exclusive OR gate 16a and the next upper bit comrades are excluded. Input to the exclusive OR gate 16b, and similarly to each exclusive OR gate, and finally the least significant bit of the address recognition code and the least significant bit of the error test code are input to the exclusive OR gate 16c. To do. Therefore, in the above example, the lower 2 bits of the error check code are inverted, and the error check code C as shown in FIG.
It is output to the parallel / serial conversion unit 14 as RC.

In the receiving device 2, the receiving side address recognition code setting switch 25 sets the same address recognition code as the address recognition code set by the transmitting side address recognition code setting switch 15. The specific bit of the address recognition code and the specific bit of the error check code CRC are input to the exclusive OR gates 26a to 26c. The combination of inputs to each of the exclusive OR gates 26a to 26c is the exclusive OR gate 26a in which the most significant bit of the address recognition code and the most significant bit of the error check code CRC are combined.
And input the next high-order bit comrade to exclusive OR gate 2
6b, and then the same operation to each exclusive OR gate, and finally the least significant bit of the address recognition code and the least significant bit of the error check code CRC are input to the exclusive OR gate 26c. Therefore, in the above example, the error test code C
The lower 2 bits of RC will be re-inverted. As a result, the signals input from the exclusive OR gates 26a to 26c to the error detection unit 23 are the exclusive OR gate 1
In 6a to 16c, the bit string is the same as the error detection code (error check code) before being inverted. The error detection unit 23 that receives this bit string detects a transmission error (remainder = 0) from the input bit string and the data portion D in FIG. The condition for the remainder to be 0 is that the error check code generated by the error check code generation unit 13 and the bit string input from the exclusive OR gates 26a to 26c to the error detection unit 23 must be the same. Therefore, if the address recognition code set by the transmission side address recognition code setting switch 15 is different from the address recognition code set by the reception side address recognition code setting switch 25, the exclusive OR gates 16a to 16c and the exclusive OR gate 26a. 26c, since the bit positions to be inverted are different, the remainder in the error detection unit 23 is not necessarily 0, and a transmission error is detected. For example, if the receiving device 3 is not the transmission destination of the transmitting device 1, a transmission error is detected and the received data section D is set as invalid data.

In this way, by inserting the address of the transmission destination into the error check code CRC, the same effect as that of the first embodiment can be obtained, and, in addition, the transmission which should not be originally received due to some trouble. When the frame is received by the receiving device, it is possible to prevent a secondary failure caused by intentionally inverting the bit of the data part D that most affects other devices in the transmission frame.

The operation of the second embodiment has been described for the transmission to the receiving device 2, but the same operation is performed for the transmission to the other receiving device 3 and the like. Further, in the second embodiment, the specific 2 bits are inverted in the error check code CRC, but the same effect can be obtained even if all the bits other than the specific 2 bits are inverted in the error check code CRC. . The specific number of bits does not have to be 2 bits, and can be set to the number of bits according to the error detection level (inter-code distance). In addition, the second embodiment
Then, although the transmission frame in FIG. 2 has been described, the same effect can be obtained even in the transmission frame including the address part.

Example 3. 4 is a block diagram showing the configuration of a data transmission device according to a third embodiment of the present invention. In the second embodiment, the address of the transmission destination is the error check code CRC.
In the third embodiment, the number of bits of the transmission frame is reduced. However, in the third embodiment, as shown in FIG. 4, in the transmitter 1, the destination address is inserted in the frame synchronization signal F. , Each exclusive OR gate 16a
16c is a specific output signal (frame synchronization signal) from the frame synchronization generation unit 12, the output of each exclusive OR is a frame synchronization signal F, and the output from the error check code generation unit 13 is The error check code CRC is input to the parallel / serial conversion unit 14. In addition, in the receiving device 2, the exclusive OR gates 26a to 26 are provided.
One input of c is set as the frame synchronization signal F output from the serial / parallel conversion unit 24, the output of each exclusive OR is input to the frame synchronization determination unit 21, and output from the serial / parallel conversion unit 24. Error test code CR
C is input to the error detection unit 23. Although the above-described configuration has been described with respect to the receiving device 2, another receiving device 3
Etc. have the same configuration.

Next, the operation of the third embodiment will be described.
In FIG. 4, in the transmission device 1, the transmission side address recognition code setting switch 15 is set to the reception device 2 which is the transmission destination
The address recognition code which is a code corresponding to the address of is set. For example, if this address is displayed in binary, "1
If it is “0”, the code (address recognition code) corresponding to this address is displayed in binary number “0000001”.
1 (most left bit is most significant bit, 0 = 1ow, 1 = hi
gh)) ”. The specific bit of the address recognition code and the specific output signal (frame synchronization signal) from the frame synchronization generator 11 are input to the exclusive OR gates 16a to 16c. The combination of inputs to each of the exclusive OR gates 16a to 16c is the most significant bit of the address recognition code and the frame synchronization generation unit 11.
Exclusive-OR gate 1 of the most significant bit of the output signal from
6a, the next higher-order bit is input to the exclusive-OR gate 16b, and the same is input to each exclusive-OR gate in the same manner. Finally, the least significant bit of the address recognition code and the frame synchronization generator 11 are input. And the least significant bit of the output signal from is input to the exclusive OR gate 16c. Therefore, in the above example, the lower 2 bits of the normal frame sync signal output from the frame sync generator 11 are inverted, and the inverted frame sync signal is output to the parallel / serial converter 14.

In the receiving device 2, the receiving side address recognition code setting switch 25 sets the same address recognition code as the address recognition code set by the transmitting side address recognition code setting switch 15. The specific bit of the address recognition code and the specific bit of the frame synchronization signal F are input to the exclusive OR gates 26a to 26c. The combination of inputs to each of the exclusive OR gates 26a to 26c is the exclusive OR gate 26a of the most significant bit of the address recognition code and the most significant bit of the frame synchronization signal F.
And input the next high-order bit comrade to exclusive OR gate 2
6b, and similarly to the exclusive OR gates, and finally, the least significant bit of the address recognition code and the least significant bit of the frame synchronization signal F are input to the exclusive OR gate 26c. Therefore, in the above example, the lower 2 bits of the frame synchronization signal F will be inverted again. As a result, the signals output from the exclusive OR gates 26a to 26c have the same bit pattern as the normal frame synchronization signal. In the frame synchronization determination unit 21 which has input the same bit pattern as this normal frame synchronization signal,
When it is confirmed that this pattern is a desired bit pattern, the data unit D and the error check code CRC received by the receiving device 2 are processed as valid data. If the frame synchronization signal F is not the desired bit pattern, The data section D and the error check code CRC are invalidated. Therefore, if the address recognition code set by the transmission side address recognition code setting switch 15 is different from the address recognition code set by the reception side address recognition code setting switch 25, the exclusive OR gates 16a to 16c and the exclusive OR gate 26a. 26c, since the bit positions to be inverted are different, the frame synchronization signal F input to the frame synchronization determination unit 21 is not necessarily a normal frame synchronization signal, and the data portion D and the error check code CRC are invalid data. Treated For example, if the receiving device 3 is not the destination of the transmitting device 1, the received data portion D and the error check code CR are received.
Let C be invalid data.

In this way, by inserting the address of the transmission destination in the frame synchronization signal F, the same effect as that of the first embodiment can be obtained, and besides, the data to be received promptly is determined, and unnecessary error is detected. An effect that processing such as detection can be prevented can be obtained.

The operation of the third embodiment has been described with respect to the transmission to the receiving device 2, but the same operation is performed for the transmission to the other receiving device 3 and the like. Further, in the third embodiment, the specific 2 bits are inverted in the frame synchronization signal F, but the same effect can be obtained even if all the bits other than the specific 2 bits are inverted in the frame synchronization F. The specific number of bits does not have to be 2 bits, and can be set to the number of bits according to the error detection level (inter-code distance). Further, although the third embodiment has been described with reference to the transmission frame of FIG. 2, the same effect can be obtained even with a transmission frame including an address part.

Example 4. FIG. 5 is a block diagram showing the configuration of the data transmission device according to the fourth embodiment of the present invention. In the first to third embodiments described above, the case where the address recognition code is set by mechanical setting such as a switch has been described.
Then, as shown in FIG. 5, in order to simplify the setting of the address recognition code, the transmitter 1 reads the address recognition code from the storage element 17 such as a ROM in which the address recognition code is stored in advance. A transmitting side address setting unit 18 such as a switch for setting a memory address for setting is provided, and in the receiving devices 2 and 3, a storage element 27 such as a ROM in which an address recognition code is stored in advance, and an address from this storage element 27. A receiving side address setting unit 28 such as a switch for setting a memory address for reading the recognition code is provided, and the address recognition code is set by the transmitting side address setting unit 18 or the receiving side address setting 28, respectively.

In the first to third embodiments, the address recognition code setting switch 15 on the transmitting side and the address recognition code setting switch 25 on the receiving side are used to manually set the address of the receiving device as the transmission destination by one bit for the address recognition code. It was cumbersome because it had to be converted and set by. Therefore, in the fourth embodiment shown in FIG. 5, the storage element is set by setting the address of the destination receiving apparatus by the transmitting side address setting unit 18 and the address of the destination receiving apparatus by the receiving side address setting unit 28. 17
Alternatively, the address recognition code is read from the storage element 27, and a specific bit on the transmission frame is inverted by this read data.

As described above, by setting only the address of the destination receiving device and simplifying the setting of the address recognition code, the number of setting switches is reduced, and the conversion error from the address of the destination receiving device to the address recognition code is incorrect. , And the setting error of the address recognition code can be prevented. Further, in FIG. 5, the output signals of the storage element 17 and the storage element 27 are input to the exclusive OR gates 16a to 16c and the exclusive OR gates 26a to 26c, respectively, so that specific bits in parallel format data can be specified. Although the example of inverting is shown, a new function for counting the bit position of serial format data is newly provided, so that a specific bit in serial format data can be determined based on the output values of the storage elements 17 and 27. The same effect can be obtained when inverted. Also, this particular number of bits is
It does not have to be 2 bits, and can be set to the number of bits according to the error detection level (inter-code distance). Also,
Although the fourth embodiment has been described with reference to the transmission frame in FIG. 2, the same effect can be obtained even in the transmission frame including the address part.

[0036]

As described above, according to the first aspect of the invention, the transmitting side address recognition code setting means for setting the address recognition code corresponding to the address of the receiving destination device in the transmitting device, and the transmitting side address. An exclusive OR circuit that inputs the address recognition code set by the recognition code setting means and the data section generated by the data section generation section to obtain an exclusive OR is provided, and the address of the receiving apparatus is provided to the receiving apparatus. The address recognition code setting means for setting the address recognition code corresponding to the address recognition code and the address recognition code set by the address recognition code setting means for the reception side and the data section from the serial / parallel conversion section are inputted and exclusive logic is inputted. Since the exclusive OR circuit for summing is provided, the destination address can be inserted in the data section. Since the destination can be determined without using the address part for determining whether to send to the device, it is possible to reduce the number of bits corresponding to the address part of the transmission frame, and thus the transmission delay of the transmission frame. The effect that the time can be shortened (the transmission efficiency can be increased) is obtained.

According to the second aspect of the invention, the transmission side address recognition code setting means for setting the address recognition code corresponding to the address of the reception destination apparatus of the transmission destination and the transmission side address recognition code setting means for the transmission apparatus. The address recognition code and the error check code generated by the error check code generator are input, and an exclusive OR circuit that takes an exclusive OR is provided, and the receiving device is provided with an address corresponding to the address of the receiving device. An exclusive OR is taken by inputting the receiving side address recognition code setting means for setting the recognition code and the address recognition code set by the receiving side address recognition code setting means and the error verification code from the serial / parallel conversion section. Since the exclusive OR circuit is provided and configured, the destination address can be inserted into the error check code.
Unlike the conventional case, the destination can be determined without using the address part for determining to which receiving device the transmission is performed, so that the number of bits corresponding to the address part of the transmission frame can be reduced. Therefore, the effect that the transmission delay time of the transmission frame can be shortened is obtained. Also, by inserting the address of the transmission destination into the error check code, when the receiving device receives a transmission frame that should not be received due to some trouble, the data part of the transmission frame that most affects other devices is transmitted. There is also an effect that it is possible to prevent a secondary failure caused by intentionally inverting the bit.

According to the third aspect of the invention, the sender side address recognition code setting means for setting the address recognition code corresponding to the address of the destination receiver apparatus in the transmitter and the sender side address recognition code setting means. An exclusive OR circuit that inputs the generated address recognition code and the frame synchronization signal generated by the frame synchronization generation unit and performs an exclusive OR is provided, and the receiving device recognizes the address corresponding to the address of the receiving device. Exclusive to take an exclusive OR by inputting a receiving side address recognition code setting means for setting a code and the address recognition code set by the receiving side address recognition code setting means and the frame synchronization signal from the serial / parallel conversion section Since it is configured by providing a logical OR circuit, the destination address can be inserted in the frame synchronization signal,
As a result, the destination can be determined without using the address part for determining which receiving device is to be transmitted as in the conventional case, so that the number of bits corresponding to the address part of the transmission frame is reduced. Therefore, it is possible to obtain the effect that the transmission delay time of the transmission frame can be shortened. Further, by inserting the address of the transmission destination in the frame synchronization signal, it is possible to quickly determine the data to be received and prevent unnecessary processing such as error detection.

According to the fourth aspect of the invention, since the transmitting side address recognition code setting means and the receiving side address recognition code setting means are respectively constituted by mechanical switches, the address recognition code setting means is realized with a simple circuit configuration. The effect of being able to do is obtained.

According to the fifth aspect of the invention, the transmitting side address recognition code setting means and the receiving side address recognition code setting means are a storage element such as a ROM storing the address recognition code, and the address recognition code from this storage element. Since it is configured with an address setting unit for setting an address for reading out, if only the destination address is set,
The address recognition code can be read out, which reduces the number of setting switches, and can prevent an erroneous conversion from an address to an address recognition code and an erroneous setting of the address recognition code.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission device according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a transmission frame in each embodiment.

FIG. 3 is a block diagram showing a configuration of a data transmission device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a data transmission device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a data transmission device according to a fourth embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of a transmission frame in a conventional data transmission device.

FIG. 7 is a block diagram showing a configuration of a conventional data transmission device.

FIG. 8 is a block diagram showing a configuration of another conventional data transmission device showing an example in which an address setting unit / determination unit is added to the conventional data transmission device.

FIG. 9 is a schematic configuration diagram of a transmission frame showing an example in which a transmission frame “address A” is inserted in a conventional data transmission device.

[Explanation of symbols]

1 transmitter, 2 and 3 receiver, 11 frame synchronization generator, 12 data generator, 13 error verification code generator, 14 parallel / serial converter, 15 transmitter address recognition code setting switch (transmitter address recognition code Setting means), 16, 26 exclusive OR circuit, 16a
16c, 26a to 26c Exclusive OR gate, 1
7, 27 storage element, 18 transmission side address setting section, 2
1 frame synchronization determination unit, 22 data unit reception unit, 23
Error detection unit, 24 Serial / parallel conversion unit, 25
Receiving side address recognition code setting switch (receiving side address recognition code setting means), 28 receiving side address setting section, 3
1,61,91 Transmission frame.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 12/00

Claims (5)

(57) [Claims] 1. A frame synchronization generation unit for generating a frame synchronization signal indicating the start of a transmission frame, a data unit generation unit for generating a data unit indicating message information, and inputting the data unit so that the data unit is accurate. An error test code generation unit for generating an error test code indicating a code for error detection for confirming whether or not the data has been sent to the transmission partner, the frame synchronization signal, the data unit, and the error test code are input in parallel / A transmission device including a parallel / serial conversion unit that performs serial conversion and outputs a serial transmission signal, a serial / parallel conversion unit that receives a serial transmission signal from the transmission device, and performs serial / parallel conversion, and the serial / parallel conversion unit. Input a frame synchronization signal from the parallel conversion unit and determine whether the frame synchronization signal has a desired bit pattern A frame synchronization determination unit, a data unit receiving unit that receives the data unit from the serial / parallel conversion unit, and a data unit and an error test code from the serial / parallel conversion unit are input to determine whether the data unit is correct. In a data transmission device including a receiving device having an error detection unit for detecting an error, a transmitting side address recognition code setting for setting an address recognition code corresponding to an address of a receiving destination device in the transmitting device Means and
An exclusive OR circuit for inputting the address recognition code set by the transmission side address recognition code setting means and the data section generated by the data section generation section to obtain an exclusive OR is provided, and the data section generation is performed. The data section from the section is not directly input to the parallel / serial conversion section, but the frame synchronization signal from the frame synchronization generation section, the output signal of the exclusive OR circuit, and the error verification code from the error verification code generation section. And a receiving side address recognition code setting means for setting an address recognition code corresponding to the address of the receiving device in the receiving device, and the receiving side address recognition code. The address recognition code set by the setting means and the data section from the serial / parallel conversion section are input and an exclusive OR operation is performed. A logical OR circuit is provided, and the output signal of the exclusive OR circuit is input to the data section receiving section and the error detecting section without directly inputting the data section from the serial / parallel conversion section. A data transmission device characterized by the above. 2. A frame synchronization generation unit for generating a frame synchronization signal indicating the start of a transmission frame, a data unit generation unit for generating a data unit indicating message information, and inputting the data unit so that the data unit is accurate. An error test code generation unit for generating an error test code indicating a code for error detection for confirming whether or not the data has been sent to the transmission partner, the frame synchronization signal, the data unit, and the error test code are input in parallel / A transmission device including a parallel / serial conversion unit that performs serial conversion and outputs a serial transmission signal, a serial / parallel conversion unit that receives a serial transmission signal from the transmission device, and performs serial / parallel conversion, and the serial / parallel conversion unit. Input a frame synchronization signal from the parallel conversion unit and determine whether the frame synchronization signal has a desired bit pattern A frame synchronization determination unit, a data unit receiving unit that receives the data unit from the serial / parallel conversion unit, and a data unit and an error test code from the serial / parallel conversion unit are input to determine whether the data unit is correct. In a data transmission device including a receiving device having an error detection unit for detecting an error, a transmitting side address recognition code setting for setting an address recognition code corresponding to an address of a receiving destination device in the transmitting device Means and
An exclusive OR circuit for inputting the address recognition code set by the transmitting side address recognition code setting means and the error verification code generated by the error verification code generation section to take an exclusive OR is provided, and the error The error verification code from the verification code generation unit is not directly input to the parallel / serial conversion unit, but the frame synchronization signal from the frame synchronization generation unit, the data unit from the data unit generation unit, and the output of the exclusive OR circuit. And a signal input to the parallel / serial conversion unit, and a receiving side address recognition code setting means for setting an address recognition code corresponding to the address of the receiving apparatus in the receiving apparatus, and the receiving side address recognition The address recognition code set by the code setting means and the error verification code from the serial / parallel conversion unit are input to perform an exclusive OR. An exclusive OR circuit is provided, and the error check code from the serial / parallel conversion section is not directly input, but the output signal of the exclusive OR circuit and the data section from the serial / parallel conversion section have the above error. A data transmission device characterized in that the data is input to a detection unit. 3. A frame synchronization generation unit for generating a frame synchronization signal indicating the start of a transmission frame, a data unit generation unit for generating a data unit indicating message information, and inputting the data unit so that the data unit is accurate. An error test code generation unit for generating an error test code indicating a code for error detection for confirming whether or not the data has been sent to the transmission partner, the frame synchronization signal, the data unit, and the error test code are input in parallel / A transmission device including a parallel / serial conversion unit that performs serial conversion and outputs a serial transmission signal, a serial / parallel conversion unit that receives a serial transmission signal from the transmission device, and performs serial / parallel conversion, and the serial / parallel conversion unit. Input a frame synchronization signal from the parallel conversion unit and determine whether the frame synchronization signal has a desired bit pattern A frame synchronization determination unit, a data unit receiving unit that receives the data unit from the serial / parallel conversion unit, and a data unit and an error test code from the serial / parallel conversion unit are input to determine whether the data unit is correct. In a data transmission device including a receiving device having an error detection unit for detecting an error, a transmitting side address recognition code setting for setting an address recognition code corresponding to an address of a receiving destination device in the transmitting device Means and
An exclusive OR circuit for inputting the address recognition code set by the transmission side address recognition code setting means and the frame synchronization signal generated by the frame synchronization generation unit to take an exclusive OR is provided, and the frame synchronization is performed. The frame synchronization signal from the generation section is not directly input to the parallel / serial conversion section, but the output signal of the exclusive OR circuit, the data section from the data generation section, and the error verification code from the error verification code generation section. And a receiving side address recognition code setting means for setting an address recognition code corresponding to the address of the receiving device in the receiving device, and the receiving side address recognition code. The address recognition code set by the setting means and the frame synchronization signal from the serial / parallel converter are input and removed. And an exclusive OR circuit for taking a logical OR, and the output signal of the exclusive OR circuit is input to the frame synchronization determination section without directly inputting the frame synchronization signal from the serial / parallel conversion section. A data transmission device characterized in that 4. The data transmission apparatus according to claim 1, wherein the transmitting side address recognition code setting means and the receiving side address recognition code setting means are each constituted by a mechanical switch. 5. The transmitting side address recognition code setting means and the receiving side address recognition code setting means, a storage element such as a ROM storing the address recognition code, and an address for reading the address recognition code from the storage element. 4. The data transmission apparatus according to claim 1, wherein the data transmission apparatus comprises an address setting unit for setting the above.