KR19980074516A - An error correction method and an apparatus therefor for reproducing a digital signal - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data error correction in digital signal reproduction, and more particularly, to an error correction method for correcting errors in data using a Reed-Solomon code and an apparatus applied thereto. This is an error correction method for correcting an error of data using a Reed-Solomon code in the reproduction of a digital signal, comprising: calculating a syndrome from a received signal (step 400); Determining a number of errors using the error number discriminant by the syndrome calculated in the syndrome calculation step (operation 400); Performing error correction according to the number of errors determined in the error count determination step (operation 404); A state searching step (step 406) of performing a state search of the system after the number of errors determined in the error number determination step (step 402) is '0' or after performing the error correction step (step 404); And a plug setting step of determining whether the state searched in the state searching step (step 406) is good or not and whether the number of errors determined in the error number determination step (step 402) is greater than or equal to 3 and setting the plug to 0 or 1 (Step 408), and a syndrome calculation step 500 for calculating a syndrome from a received signal. An error number discrimination step (step 502) of discriminating an error number using an error number discrimination formula by the syndrome calculated in the syndrome calculation step (step 500); If it is determined that the number of errors identified in the error count determination step 502 is '2', it is determined whether the current error position coincides with the position of the error set in the plug setting step (step 408) of the C1 decoding process Determining whether the plug is matched (step 504); If the number of errors determined in the error count determination step 502 is '1' through the error number determination step 502 and / or the plug matching determination step 504, a '1' error correction is performed An error correction step (step 506) of performing '2' error correction if the determination of the plug match determination step (step 504) matches the position of the error currently detected and the error position set in the C1 decoding process; Determining whether or not the laser is corrected if the number of errors detected in step 502 is greater than '2' (step 508); A first number of plugs (step 510) for determining the number of plugs if the determination of step 508 is 'ON'; If the number of plugs determined in the first number of plugs determination step 510 is '3' or '4', '3' / '4' performing laser correction of '3' / '4' (Step 512); In the laser correction step '3' or '4', after the laser correction of '3' or '4' is performed in the laser correction step 512, a check is performed to check whether the laser correction is performed correctly (Step 514); The determination of the plug matching determination step (step 504) through the plug matching determination step (step 504) and / or the laser correction determination step (step 508) A second number of plugs (step 516) for determining the number of plugs if the position of the set error does not coincide or the determination of the laser correcting step 508 is 'OFF'; And a C 2 decoding process having a plug setting step 518 of setting a plug after the syndrome calculation step 500 to the plug number second determination step 516 is performed.

Description

An error correction method and an apparatus therefor for reproducing a digital signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data error correction in digital signal reproduction, and more particularly, to an error correction method for correcting errors in data using a Reed-Solomon code and an apparatus applied thereto.

In general, when transmitting or recording a digital signal, errors may occur in data due to noise on the transmission system. In order to prevent such an error as much as possible, a check word is added when data is transmitted or recorded to correct the error data.

The code used for error correction in a compact disc player is typically a Reed-Solomon code that is a class of non-binary BCH codes. The ability of the Reed-Solomon code can correct not only the random error but also the burst error. The disadvantage of using this Reed-Solomon code is that since the Reed-Solomon code is a block sequence code having a symbol of an element of the finite field GF (2 ^M ), unlike the binary BCH code, (error value) must be obtained. Therefore, the decoding process is very complicated. In particular, the complexity of the system is greatly influenced by the error correction capability, the size of the finite field, and the type and number of finite field operations, and the time required for decoding also increases in proportion to the complexity of the system.

FIG. 1A is a diagram showing a C1 decoding algorithm according to a flag processing method in error correction of the conventional art.

Syndrome is calculated (step 100).

It is determined whether the number of errors is 0 for the syndrome calculated in step 100. In step 102,

If the determination in step 102 is that the number of errors is 0, the flag is set to 0 and the process is terminated (step 104)

If it is determined in step 102 that the number of errors is not 0, it is determined whether the number of errors is 1. In step 106,

If the number of errors is 1 in step 106, error correction is performed in step 108. In step 108,

After one error correction is performed in step 108, the flag is set to 0 and the process is terminated (step 104)

If it is determined in step 106 that the number of errors is not 1, it is determined whether the number of errors is 2. In step 110,

If the number of errors is 2 in step 110, error correction is performed in step 112. In step 112,

If it is determined in step 110 that the number of errors is not 2 or if the error is corrected in step 112, the flag is set to 1 and the process is terminated (step 114)

FIG. 1B is a diagram illustrating a C2 decoding algorithm according to a flag processing method in error correction of the conventional art.

Syndrome is calculated (step 150).

It is determined whether the number of errors is 0 for the syndrome calculated in step 150. In step 152,

If the determination in step 152 is 0, the flag is set to 0 and the process is terminated (step 154)

If it is determined in step 152 that the number of errors is not 0, it is determined whether the number of errors is 1. In step 156,

If it is determined in step 156 that the number of errors is 1, one error correction is performed (step 158)

After one error correction is performed in step 158, the flag is set to 0 and the process is terminated (step 154)

If it is determined in step 156 that the number of errors is not 1, it is determined whether the number of errors is 2. In step 160,

If it is determined in step 160 that the number of errors is 2, the plug is checked (step 162)

If the checked result in step 162 is good, then two error corrections are performed (step 164)

After performing two error corrections in step 164, the flag is set to 0 and the process is terminated (step 154)

If the checked result in step 162 is bad, it is determined whether the number of plugs is greater than 2. In step 166,

If it is determined in step 166 that the number of plugs is greater than 2, the plug is copied and terminated (step 168)

If it is determined in step 166 that the number of plugs is not greater than 2, the plug is set to 1 and the process is terminated (step 170)

In the Reed-Solomon error correction device used in a compact disc player, only two errors are corrected in the C1 code, and in the case of the C2 code, four errors can be corrected. 2 Error Correction If 8 or more burst errors occur in the number of codewords, it is not possible to perform error correction. However, if 4 laser corrections are performed, even if errors occur consecutively up to 16 codewords, There is an advantage to be able to do. However, when the maximum error correction is performed, the probability that the 8/14 modulation data is incorrect or the player operation state is unstable becomes very large.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an error correction method having a decoding algorithm for performing decoding with a simpler structure while exhibiting an error correction capability as much as possible,

Another object of the present invention is to provide an error correction apparatus applied to the above-described error correction method.

FIG. 1A is a diagram showing a C1 decoding algorithm according to a flag processing method in error correction of the conventional art.

FIG. 1B is a diagram illustrating a C2 decoding algorithm according to a flag processing method in error correction of the conventional art.

2 is a block diagram of an apparatus for generating a syndrome of a general Reed-Solomon code according to the present invention.

FIG. 3A shows a syndrome generator of a general Reed-Solomon code to which the present invention is applied, Fig.

FIG. 3B shows an apparatus for generating a syndrome of a general Reed-Solomon code to which the present invention is applied, Fig.

FIG. 3C shows a syndrome generator of a general Reed-Solomon code to which the present invention is applied, Fig.

FIG. 3D shows a syndrome generator of a general Reed-Solomon code to which the present invention is applied, Fig.

4 is a flowchart of a C1 decoding algorithm as an error correction method according to the present invention.

5 is a flowchart of a C2 decoding algorithm as an error correction method according to the present invention.

6A to 6B are block diagrams of an error correction apparatus according to the present invention.

According to an aspect of the present invention, there is provided an error correction method for correcting errors in data using a Reed-Solomon code in digital signal reproduction, (Step 400); Determining a number of errors using the error number discriminant by the syndrome calculated in the syndrome calculation step (operation 400); Performing error correction according to the number of errors determined in the error count determination step (operation 404); A state searching step (step 406) of performing a state search of the system after the number of errors determined in the error number determination step (step 402) is '0' or after performing the error correction step (step 404); And a plug setting step of determining whether the state searched in the state searching step (step 406) is good or not and whether the number of errors determined in the error number determination step (step 402) is greater than or equal to 3 and setting the plug to 0 or 1 (Step 408), and a syndrome calculation step 500 for calculating a syndrome from a received signal. An error number discrimination step (step 502) of discriminating an error number using an error number discrimination formula by the syndrome calculated in the syndrome calculation step (step 500); If it is determined that the number of errors identified in the error count determination step 502 is '2', it is determined whether the current error position coincides with the position of the error set in the plug setting step (step 408) of the C1 decoding process Determining whether the plug is matched (step 504); If the number of errors determined in the error count determination step 502 is '1' through the error number determination step 502 and / or the plug matching determination step 504, a '1' error correction is performed An error correction step (step 506) of performing '2' error correction if the determination of the plug match determination step (step 504) matches the position of the error currently detected and the error position set in the C1 decoding process; Determining whether or not the laser is corrected if the number of errors detected in step 502 is greater than '2' (step 508); A first number of plugs (step 510) for determining the number of plugs if the determination of step 508 is 'ON'; If the number of plugs determined in the first number of plugs determination step 510 is '3' or '4', '3' / '4' performing laser correction of '3' / '4' (Step 512); In the laser correction step '3' or '4', after the laser correction of '3' or '4' is performed in the laser correction step 512, a check is performed to check whether the laser correction is performed correctly (Step 514); The determination of the plug matching determination step (step 504) through the plug matching determination step (step 504) and / or the laser correction determination step (step 508) A second number of plugs (step 516) for determining the number of plugs if the position of the set error does not coincide or the determination of the laser correcting step 508 is 'OFF'; And a C 2 decoding process having a plug setting step 518 of setting a plug after the syndrome calculation step 500 to the plug number second determination step 516 is performed.

The syndrome when a single symbol error occurs in the syndrome calculation step 400

, And the syndrome when a double symbol error occurs

, And the syndrome when a triple symbol error occurs

, And the syndrome when a quadruple symbol error occurs

.

The error number determination step (step 402)

And,

a) If there is no error

b) When a single symbol error occurs

c) When a double symbol error occurs

d) If an error of more than triple symbol occurs

In cases other than the above a), b), and c)

The number of errors is determined.

The error number determination step 402 may include determining whether the number of errors is '0' (step 402-1); Determining whether the number of errors is '1' (step 402-2); And determining whether the number of errors is '2' (step 402-3).

If the number of errors identified in the error number determination step is '0', the error correction is not performed. If the number of errors is '1', the error correction step (step 404) Error correction is performed in step 404-1. If the number of errors is '2', error correction in step 2 is performed in step 404-2. In step 404-1, The performance of

X1 = ==== Error location

Y1 = ==== Error value

, And the '2' error correction (step 404-2) is performed by using an error locator polynomial having error locus X1 and X2 in the vicinity of a double symbol error , The polynomial equation , The polynomial can be expressed by Equation (14) below,

&Quot; (14) "

(here, ego, ) Also, Trace of To Wow If you write an expression to distinguish it,

, And the finite field GF , M = 8, and therefore, Wow Can be expressed by Equations 15 and 16, respectively,

&Quot; (15) "

&Quot; (16) "

From equations (15) and (16) ego, , ≪ EMI ID = 14.0 > Throb and Can be expressed as the following Equation (17)

&Quot; (17) "

But or The following equation (18) can be obtained,

&Quot; (18) "

Here, y is Is an element in GF (2 ^B ) When you say , The two roots expressed by the above-mentioned equation (18) are determined. and , The error positions X1 and X2 are expressed by the following Equation (19), and the error values Y1 and Y2 are expressed by the following Equation (20)

&Quot; (19) "

&Quot; (20) "

If the number of errors determined in the error correction step 404 is other than '0', '1', or '2', error correction is not performed.

The state searching step (step 406) is a step of searching system characteristics, data and player status. The state searching step (step 406) The step for variably adding the next plug (Flag)

STATUS FLAG C1 FLAG Set / Reset Whether frame sync is detected Player operating status No Error One Error Two Error reset (OK) reset (OK) reset reset reset / set reset (OK) set (NG) reset reset / set set set (NG) reset (OK) reset reset / set set set (NG) set (NG) reset / set set set

.

The plug setting step 408 sets the plug to '0' if the state searched in the state searching step 406 is good, sets the plug to '1' if the searched state is not good, If it is determined that the number of errors identified in the determination step 402 is greater than or equal to 3, the plug is directly set to '1' without going through the error correction step 404 and the state searching step 406 .

The plug setting step (step 408) includes setting (step 408-1) a plug to '0' if the state searched in the state searching step (step 406) is good. And if the number of errors identified in the error number determination step 402 is greater than or equal to 3, the error correction step 404 and / And directly setting the plug to '1' without going through the state searching step (step 406) (step 408-2).

The syndrome when a single symbol error occurs in the syndrome calculation step 500

, And the syndrome when a double symbol error occurs

, And the syndrome when a triple symbol error occurs

, And the syndrome when a quadruple symbol error occurs

.

The error number determination step (step 502)

And,

a) If there is no error

b) When a single symbol error occurs

c) When a double symbol error occurs

d) If an error of more than triple symbol occurs

In cases other than the above a), b), and c)

The number of errors is determined.

The error number determination step 502 may include determining whether the number of errors is '0' (step 502-1); Determining whether the number of errors is '1' (step 502-2); And determining whether the number of errors is '2' (step 502-3).

The error correction step 506 is divided into a '1' error correction step (step 506-1) and a '2' error correction step (step 506-2). The '1' error correction step 506-1 The performance of the step

X1 = s ₁ / s ₀ ==== error position

Y1 = s ₀ ==== error value

And, the "2" if the error occurs in performing the symbol of the second error correction step (step 506-2), the error position X1, the error locator polynomial having the near-X2 z (x) = x ² ₊ z ₁ + x When defined as z _2, when replaced with x = z ₁ ^x, from the polynomials, the polynomials can be represented as in the following equation (14), the

&Quot; (14) "

(here, And z ₁ = D ₂ / D ₁ z ₂ = D ₃ / D ₁ ) Further, Of to distinguish T _r (k) of the trace (trace) in T ₂ (k) and T ₄ (k) write the formula,

, And the finite field GF , M = 8, and therefore, Wow Can be expressed by Equations 15 and 16, respectively,

&Quot; (15) "

&Quot; (16) "

From equations (15) and (16) ego, , ≪ EMI ID = 14.0 > Throb and Can be expressed as the following Equation (17)

&Quot; (17) "

But or The following equation (18) can be obtained,

&Quot; (18) "

Here, y is GF Is an element within When you say , The two roots expressed by the above-mentioned equation (18) are determined. and The error positions X1 and X2 are expressed by the following Equation (19), and the error values Y1 and Y2 are expressed by the following Equation (20).

&Quot; (19) "

&Quot; (20) "

The determination of the laser correction determination step (step 508) is as follows.

[table]

STATUS FLAG MICOM DATA Whether this laser is corrected Whether frame sync is detected Player operating status forced Erasure OFF reser (OK) reset (OK) reset ON reset (OK) set (NG) reset ON / OFF set (NG) reset (OK) reset ON / OFF set (NG) set (NG) reset ON / OFF do not care do not care set OFF

In the laser correction step (step 512) of '3' / '4', laser correction of '3' Is expressed by the following equation (21)

&Quot; (21) "

Also, the error location polynomial is given by the following equation (22)

&Quot; (22) "

In Equation 22, the coefficient of each degree Can be expressed as the following Equation (23)

&Quot; (23) "

Equation (22) becomes '0' if a triple symbol error occurs. Error location , The error values Y1, Y2, and Y3 are obtained by the following Equation (24), and the error values Y1, Y2, and Y3 are obtained by solving the three-way linear simultaneous equations of Equation (21)

&Quot; (24) "

'4' This laser correction is a syndrome element Is expressed by the following equation (25)

&Quot; (25) "

Also, the error location polynomial is as shown in the following Equation 26,

&Quot; (26) "

In Equation (26), the coefficient of each order is expressed by Equation (27) below,

&Quot; (27) "

Equation (26) becomes '0' if a quad-symbol error occurs, And the error values Y1, Y2, Y3, and Y4 are as shown in the following Equation (28) by solving the 4-element linear simultaneous equations of Equation (25).

&Quot; (28) "

The plug setting step 518 may include a plug setting step 518-1, a plug setting step 518-2, a plug setting step 518-3, (Step 502-1) of determining whether the number of errors in the number-of-errors determination step 502 is '0' is determined in the plug-0 setting step 518-1 (step 518-1) 1 'or' 2 'error is corrected in the' 1 '/' 2 'error correcting step (step 506), or when the result of checking in the checking step 514 is good, The plug number setting step 518-2 sets the number of plugs determined in the plug number first determination step 510 as '0', '1', '2' Or if the result of the checking in the checking step 514 is not good or if the number of the plugs determined in the second number of plug determination step 516 is '1' or '2' To (Step 518-3), the number of plugs determined in the plug number first determination step 510 is' 5 'or the plug number second determination step 516 is' When the number of plugs determined in step " 2 " exceeds " 2 ".

According to another aspect of the present invention,

An error correction apparatus for correcting an error of data by using a Reed-Solomon code in the reproduction of a digital signal, the error correction apparatus comprising: a program ROM in which an error correction decoding algorithm is coded and embedded; A program register for storing an instruction output from the program ROM; A program decoder for outputting a control signal according to a predetermined coding format to an instruction stored in the program register; A signal output from the program decoder and a signal output from the error correction operation unit are used as an input signal to hold a specific step or instruction at the time of error correction for a predetermined period, A jumping control unit A program address counter for counting an address by a signal output from the program register, a signal output from the program decoder, and a control signal output from the jump control unit; And an operation control unit for generating an input / output control signal for code data necessary for error correction according to a signal output from the program decoder, and a data bus for interfacing signals between the respective components; An address generator for generating code data necessary for error correction and an address for use in reading / writing a plug; And is connected to the data bus, Any element on To an integer value ( ) To convert converter; Connected to the data bus and having an integer value ( ) To a finite field GF Any element on To convert converter; A C1 plug counter connected to the data bus for reading the C2 code data at the time of correcting the C2 code error and then reading the C1 plug at the time of counting the number of C1 plugs; A zero counter connected to the data bus for detecting zero data and measuring the number and outputting the number of measurements; An input / output register connected to the data bus for inputting / outputting code data and plugs; An output signal from one side output from the address generator, An error location storage register for storing a location of an error generated during an error correction operation as an integer value and storing the location of the erasure output from the address generator as an integer value using an output signal of one side output from the converter as an input signal; A first signal selector for selectively outputting a signal output from the address generator and output from the error location storage register; And is connected to the data bus, Any element on To or Inverted output to convert to expression; And is connected to the data bus and used for error correction of the double symbol, A trace transformer for obtaining a root of the trapezoid; A second signal selector connected to the data bus for selectively outputting data on the 8-bit internal data bus or data output from the inverted data bus; A third signal selector connected to the data bus for selectively outputting data on an 8-bit internal data bus or data passed through the trace converter; An MA register for temporarily storing the signal output from the second signal selector; An MB register for temporarily storing data output from the third signal selector; An AB register connected to the data bus for temporarily storing data; A TEMP register connected to the data bus for temporarily storing temporary data generated during operation; Connected to the data bus and generating syndrome elements A syndrome generator for obtaining a syndrome; A C1 / C2 plug generator connected to the data bus and adding plug information or copying plug information to each code data after error correction processing; A RAM connected to the data bus for storing important coefficient data or various roots generated during an error correction operation; The signal output from the MA register and the signal output from the MB register are used as input signals, A multiplier for multiplying the elements on; And a signal output from the multiplier and a signal output from the AB register as input signals, And an adder for adding elements on the input signal.

And the inverse encoder is used when performing a division operation during an error correction operation.

And the adder is comprised of an exclusive-OR gate.

Hereinafter, a preferred embodiment of the present invention will be described in detail.

In general, the decoding process of the Reed-Solomon code is summarized in the following five steps.

1) Calculate the syndrome from the received code.

2) Compute the error locator polynomial.

3) Calculate the error location number.

4) Calculate the error value.

5) Perform error correction.

If an error e (x) occurs during transmission when the transmission code c (x) is transmitted, the reception code r (x) can be expressed as Equation (1).

[Equation 1]

r (x) = c (x) + e (x)

a as a finite field GF ( ) Is a premix element (X) of the generator polynomial g (x), and substituting the neighboring polynomial g (x) into the equation (1), the following equation (2) and equation (3) can be obtained.

&Quot; (2) "

&Quot; (3) "

The syndrome element I can be expressed by Equation 4 below.

&Quot; (4) "

In practice, a syndrome generator of double error correction (32, 28), (28, 24) Reed-Solomon code applied on a compact disc player is as shown in FIG.

2 is a block diagram of an apparatus for generating a syndrome of a general Reed-Solomon code according to the present invention.

2, a received signal 200 (x) and a signal output from the multiplier 202 are input to an adder 204, and a signal output from the adder 204 is input to a flip-flop. Flop 206 and the signal output from the flip-flop 206 is input to the multiplier 202. The multiplier 202 multiplies the signal output from the flip-flop 206 and the output signal of the generator polynomial root 208 And outputs it to the adder 204. [

For example, Any element on

1, a, , Is expressed by the following Equation (5). &Quot; (5) "

&Quot; (5) "

The apparatus according to Equation (5) is configured as shown in FIGS. 3A to 3D.

FIG. 3A shows a syndrome generator of a general Reed-Solomon code to which the present invention is applied, Fig.

FIG. 3B shows an apparatus for generating a syndrome of a general Reed-Solomon code to which the present invention is applied, Fig.

FIG. 3C shows a syndrome generator of a general Reed-Solomon code to which the present invention is applied, Fig.

FIG. 3D shows a syndrome generator of a general Reed-Solomon code to which the present invention is applied, Fig.

An error occurring during transmission is expressed by Equation (6) below.

&Quot; (6) "

Also, (6) can be expressed as the following Equation (7). &Quot; (7) "

&Quot; (7) "

The syndrome element < RTI ID = 0.0 > Is a polynomial of the generator polynomial ( ), And each syndrome element is expressed by the following Equation (8).

&Quot; (8) "

In Equation (8) To And the error location number To (9) " (9) "

&Quot; (9) "

From Equation (9) Wow And decoding the error e (x) expressed by Equation (7) using a Reed-Solomon code.

Then, an error is calculated from the received signal, and then the error syndrome discrimination described below is performed.

Double error [ ], The syndrome element can be obtained from Equation (8) as follows.

&Quot; (10) "

Using Equation 10 above,

A quadratic equation as shown in the following equation (11) can be obtained.

&Quot; (11) "

The respective coefficients of Equation (11) are replaced with Equation (12).

&Quot; (12) "

If Equation (12) is substituted, Equation (11) is expressed as follows.

And can be used as an error count discrimination formula.

1) When there is no error

2) When a single symbol error occurs

3) When a double symbol error occurs

4) In case of error more than triple symbol

In cases other than 1), 2) and 3)

After determining the number of errors in 1), 2), 3) and 4), the error position and error value for the corresponding error should be determined.

* When a single symbol error occurs

When a single error occurs, the syndrome , And the error position and the error value are obtained by the following Equation (13).

&Quot; (13) "

X1 = ==== Error location

Y1 = ==== Error value

* When a 2-symbol error occurs

In case of 2-symbol error, the error location polynomial with error locus X1, X2 . From the polynomial equation , It can be expressed by the following Equation (14).

&Quot; (14) "

here, ego, to be. And Trace of To Wow The following is an example.

Finite element GF If m = 8, Wow Can be expressed by Equations (15) and (16), respectively.

&Quot; (15) "

&Quot; (16) "

From equations (15) and (16) ego, , ≪ EMI ID = 14.0 > Throb and Can be expressed by the following Equation (17).

&Quot; (17) "

But or The following equation (18) can be obtained.

&Quot; (18) "

Here, y is GF Is an element within When you say The two roots expressed by the above-mentioned equation (18) are determined.

In addition to the method of calculating two roots by this calculation Using And then Value into an address input of a read-only memory (ROM) to determine one of the two pre- Can be obtained directly from the output of the ROM. The following table 1 shows the case of (32,28) Reed-Solomon codes Here is an example of a value:

Table 1 below is a trace conversion table for obtaining the root of Equation (14).

[Table 1]

k x 10 11101001 10000111 10000101 11001001 10001110 10001111 10101001 110 11 11000000 1110100 10010100 1010100 100110 100110 11010010 1110010 11011110 10110100 11000010 10011101 1011110 11100101 10001001 10101010 11110 11000000 11011111 1100010 11000111 10100000 11011010 1011110 1001111 11011101 10000100 10111011 10101 11010011 1001001 11011111 10010010 1010110 11010101 10100111 11011011 10001001 1000001 11110011 11001000 1011001 11011101 10001010 1010011 11110100 1001 11111010 11001011 1100111 10110 11101100

Table 1 For Is described in detail in the Korean Patent Application No. 90-21950 (filed by Samsung Electronics), the description thereof is omitted.

If the value is outside the range shown in Table 1, it is regarded that three or more errors have occurred. The and The error positions X1 and X2 can be expressed by the following equation (19).

&Quot; (19) "

The error values Y1 and Y2 can be expressed by the following Equation (20).

&Quot; (20) "

* When a triple symbol error occurs

If a triple symbol error occurs, the syndrome element Is expressed by the following equation (21).

&Quot; (21) "

Further, the error location polynomial is expressed by the following equation (22).

&Quot; (22) "

In Equation 22, the coefficient of each degree Can be expressed by the following equation (23).

&Quot; (23) "

Equation (22) becomes '0' if a triple symbol error occurs. Error location , The error values Y1, Y2, and Y3 are obtained by the following Equation (24). ≪ EMI ID = 24.0 >

&Quot; (24) "

* When a 4-symbol error occurs

If a quad-symbol error occurs, the syndrome element Is expressed by the following equation (25).

&Quot; (25) "

Also, the error location polynomial is given by the following equation (26).

&Quot; (26) "

In Equation (26), the coefficient of each order is expressed by Equation (27).

&Quot; (27) "

Equation (26) becomes '0' if a quad-symbol error occurs.

Error location The error values Y1, Y2, Y3, and Y4 are obtained by the following equation (28). ≪ EMI ID = 28.0 >

&Quot; (28) "

The Reed-Solomon code can be decoded according to the error correction method described so far, and the error correction code used in the actual digital device is composed of two types of codes C1 and C2 as CIRC (Cross Interleaved Reed-Solomon Code) . That is, the error correction decoding process is divided into two steps.

Assuming that the minimum distance of C1 and C2 codes is 5, in case of error correction, 2t + 1 5, and in the case of erasure correction, t + 1 Error correction up to 5 is possible. Where t is the error correction capability.

In the decoding procedure used in the algorithm of the present invention, the C1 error correction is performed using the C1 code, and then the C2 error / the laser correction is performed using the C2 code and the C1 plug (Flag) information. This will be described with reference to the drawings.

4 is a flowchart of a C1 decoding algorithm as an error correction method according to the present invention.

First, a syndrome is calculated from a received signal (step 400)

The number of errors is determined by using the error number discrimination formula based on the syndrome calculated in operation 400. In operation 402,

The syndrome when a single symbol error occurs

to be.

The syndrome at the time of occurrence of the double symbol error is expressed by Equation (10). The syndrome at the time of occurrence of the triple symbol error is expressed by Equation (21). The syndrome at the occurrence of the quadruple symbol error is as shown in Equation 25 above.

An example of determining the number of errors in the above Equations 10 to 12 has been described above.

The description of the discriminant that discriminates whether a single error has occurred, a double error has occurred, or a triple or more error has occurred is as described above.

That is, it is determined whether or not the number of errors is '0' (step 402-1), whether or not the number of errors is '1' (step 402-2) Step 402-3) is determined by the discriminant.

Error correction is performed according to the number of errors identified in step 402. In step 404,

If the number of errors identified in step 402 is '0', error correction is not performed. If the number of the identified errors is '1', error correction is performed. (Step 404-1) In addition, if the number of identified errors is '2', error correction of '2' step)

The '1' error correction (step 404-1) is the same as already explained in the above equation (13). In addition, the '2' error correction (step 404-2) is the same as already described in the above Equations (14) to (20). If the number of errors identified in step 404 is other than '0', '1', or '2', error correction is not performed.

In step 406, the number of errors determined in the error count determination step 402 is '0' or the state search is performed after the error correction step 404 is performed.

The state searching step (step 406) is a step for searching system characteristics, data, and player situation. That is, it is a step for variably adding a plug after confirming whether there is an EFM (Eight / Fourteen Modulation) data abnormality, a player operation state, a frame sync detection or not.

A description of EFM data abnormality is as follows.

14-bit channel data input from the disc is demodulated into 8 bits, = 16384 kinds of channel data = Only 256 channel data are converted. The remaining 16384-256 = 16128 pieces of data are unnecessary data. If such unnecessary data is input from the disc, it can not be demodulated into the normal 8-bit data. At this time, set EFM data error status plug. Similarly, if the frame sync data indicating the start or end of one frame can not be detected every 7.35 KHz (= 136 microseconds), it is highly likely that the data of the corresponding frame is abnormal, so that the frame sync detection presence / absence plug is set . The player operation state is classified into a normal operation and an abnormal operation. The player state flag is set when the player abnormally operates. The steady state means a normal play state, and the abnormal state means states such as fast forward, review, and search. The state (STATUS) used in C1 decoding and the C1 plug added at that time are shown in Table 2 below.

[Table 2]

STATUS FLAG C1 FLAG Set / Reset Whether frame sync is detected Player operating status No Error One Error Two Error reset (OK) reset (OK) reset reset reset / set reset (OK) set (NG) reset reset / set set set (NG) reset (OK) reset reset / set set set (NG) set (NG) reset / set set set

In the case of reset / set in Table 2, setting two conditions at the same time means that it can be changed depending on the characteristics of the system and various application circuits.

It is determined whether the searched state is good in the state searching step 406 and whether the number of errors determined in the error number determination step 402 is greater than or equal to 3 and the plug is set to 0 or 1. In operation 408, )

If the retrieved state is good in the state searching step 406, the plug is set to '0'. (Step 408-1) On the other hand, if the retrieved state in the state searching step 406 is not good, If it is determined that the number of errors identified in the number determination step 402 is greater than or equal to 3, the plug is directly set to '1' without going through the error correction step 404 and the state searching step 406 (Step 408-2)

5 is a flowchart of a C2 decoding algorithm as an error correction method according to the present invention.

First, a syndrome is calculated from a received signal (step 500)

The number of errors is determined using the number-of-errors discrimination formula by the syndrome calculated in the syndrome calculation step 500. In step 502,

As shown in FIG. 4, the syndrome when a single symbol error occurs

to be.

The syndrome at the time of occurrence of the double symbol error is expressed by Equation (10). The syndrome at the time of occurrence of the triple symbol error is expressed by Equation (21). The syndrome at the occurrence of the quadruple symbol error is as shown in Equation 25 above.

An example of determining the number of errors in the above Equations 10 to 12 has been described above.

The description of the discriminant that discriminates whether a single error has occurred, a double error has occurred, or a triple or more error has occurred is as described above.

That is, it is determined whether the number of errors is '0' (step 502-1), whether the number of errors is '1' (step 502-2), whether the number of errors is '2' Step 502-3) is determined by the above discrimination formula.

If it is determined in step 502 that the number of errors is '2' (step 502-3), if the number of errors is '2', the current error position is determined to be a value set in the plug set in the C1 decoding algorithm (Step 504)

If the number of errors determined in the error count determination step 502 is '1' through the error number determination step 502 and / or the plug matching determination step 504, a '1' error correction is performed And performs '2' error correction if the determination of the plug match determination step (step 504) matches the position of the currently detected error and the error location set in the C1 decoding algorithm (step 506).

The '1' / '2' error correction step (step 506) is divided into a '1' error correction step (step 506-1) and a '2' error correction step (step 506-2). The '1' error correction step (step 506-1) is performed as described in Equation (13). Further, the '2' error correction step (step 506-2) is performed as described in Equations (14) to (20).

If it is determined in step 502-3 that the number of errors is '2' in the error number determination step 502, if the number of currently detected errors is not '2', it is determined whether or not the laser is corrected. Step 508)

The determination of the laser correction determination step (step 508) will be described in detail in Table 3 below.

[Table 3]

STATUS FLAG MICOM DATA Whether this laser is corrected Whether frame sync is detected Player operating status forced Erasure OFF reser (OK) reset (OK) reset ON reset (OK) set (NG) reset ON / OFF set (NG) reset (OK) reset ON / OFF set (NG) set (NG) reset ON / OFF do not care do not care set OFF

As shown in Table 2, in Table 3, selectively setting ON / OFF states is different depending on the characteristics of the system and various application circuits.

If the determination of the laser correcting status determination step 508 is 'ON' according to Table 3, the number of the plugs is determined (step 510)

If the number of plugs determined in the first number of plugs determination step 510 is '3' or '4', '3' / '4'

In the laser correction step (step 512) of '3' / '4', '3' laser correction is performed as described in the above Equations (21) to (24). Further, '4' laser correction is performed as described in the above Equations (25) to (28).

After the '3' or '4' laser correction is performed in the laser correction step 512, '3' or '4' is performed to check whether the laser correction is performed correctly. Step 514)

The determination of the plug matching determination step (step 504) through the plug matching determination step (step 504) and / or the laser correction determination step (step 508) If the positions of the set errors do not coincide with each other, or if the determination of the laser correction determination step 508 is 'OFF' based on Table 3, the number of the plugs is determined (Step 516)

After the syndrome calculation step 500 to the plug number second determination step 516 are performed, a plug is set. In step 518,

The plug setting step 518 may include a plug setting step 518-1, a plug setting step 518-2, a plug setting step 518-3, Respectively.

If it is determined in step 502-1 that the number of errors in the error count determination step 502 is '0' (step 502-1), there is no error currently detected, If the '1' or '2' error is corrected in the '1' / '2' error correction step (step 506), or if the result of the checking in step 514 is good, Setting.

The plug 1 setting step 518-2 may be performed when the number of plugs determined in the plug number first determination step 510 is '0', '1', '2' Or when the number of plugs determined in the second number of plug determination step 516 is '1' or '2', the plug is set to '1'.

The plug 'copy' setting step 518-3 may be performed when the number of plugs determined in the plug number first determination step 510 is '5' or the plug number is determined in the plug number second determination step 516 Set the plug to 'copy' when the number of plugs exceeds '2'.

An error correction apparatus for achieving another object of the present invention will now be described.

6A to 6B are block diagrams of an error correction apparatus according to the present invention.

Particularly, FIG. 6A is a block diagram of an error correction control unit of an error correction apparatus according to the present invention, and FIG. 6B is a block diagram of an error correction calculation unit.

6A includes a program ROM 600, a program register 602 having an output signal of the program ROM 600 as an input signal, an output signal of the program register 602 as an input signal, A jump control unit 606 that receives the output signal of one side of the program decoder 604 and the output signal of the error correction operation unit as shown in FIG. 6B as an input signal, the jump control unit 606, A program address counter 608 for taking the output signal of the program decoder 602 as an input signal and the output signal of the program decoder 602 and the other output signal of the program decoder 604 as an input signal, And outputs it to an error correction calculation unit (Fig. 6B).

On the other hand, the error correction arithmetic operation unit shown in FIG. 6B includes an address generator 650, The converter 652, A first counter 654, a C1 plug counter 656, a zero counter 658, an i / o register 660, an error location storage register 662, a first signal selector 664, A trace converter 668, a second signal selector 670, a third signal selector 672, an MA register 674, an MB register 676, an AB register 678, a TEMP register 680, A syndrome generator 682, a C1 / C2 plug generator 684, a RAM 686, a multiplier 688, an adder 690, and a data bus.

Then, the operation of the error correction control unit and the components constituting the error correction operation unit shown in FIGS. 6A and 6B will be described.

The error correction control unit as shown in Fig. 6A generates the control signal so that the error correction function is performed according to the flow of the algorithm as described in Figs. 4 and 5 above. The program ROM 600 is coded and embedded with an error correction decoding algorithm. That is, the C1 and C2 decoding algorithms described with reference to FIGS. 4 and 5 are coded and embedded. The program register 602 stores an instruction output from the program ROM 600. The program decoder 604 outputs a control signal to the instruction stored in the program register 602 according to a predetermined coding format. The jump control unit 606 uses a signal output from the program decoder 604 and a signal output from the error correction operation unit shown in FIG. 6B as input signals to maintain a specific step or instruction for a predetermined period Or a case of branching to another step, and generates a control signal suitable for the situation at that time. The program address counter 608 counts an address by a signal output from the program register 602, a signal output from the program decoder 604, and a control signal output from the jump control unit 606 counting). The operation control unit 610 generates an input / output adjustment signal of code data required for error correction by the signal output from the program decoder 604. [

On the other hand, the error correction arithmetic unit as shown in Fig. 6B generates arithmetic processing for error correction and addresses necessary for read / write of code data and C1 / C2 plugs. The address generator 650 generates code data necessary for error correction and an address used for reading / writing the plug. The code data refers to C1 data and C2 data. The plug also refers to a C1 plug and a C2 plug. The converter 652 is connected to the data bus 692, and the finite field GF Any element on To an integer value ( ). remind The converted constants in the converter 652 are output to the error location storage register 662. [ The converter 654 is connected to the data bus 692 and has an integer value ( ) To a finite field GF Any element on . These arbitrary elements are used for error correction operations. The C1 plug counter 656 is connected to the data bus 692, reads the C2 code data at the time of correcting the C2 code error, reads the C1 plug, and at this time, counts the number of C1 plugs. The zero counter 658 is connected to the data bus 692, detects zero data, measures the number, and outputs the number of measurements. The input / output register 660 is an interface circuit connected to the data bus 692 and used for inputting / outputting code data and plugs and the like. The error location storage register 662 stores the output signal of one side output from the address generator 650, The position of the error generated during the error correction operation is stored as an integer value or the position of the error output from the address generator 650 is stored as an integer value using the output signal of one side outputted from the converter 652 as an input signal. The first signal selector 664 selectively outputs the signal output from the address generator 650 and the signal output from the error location storage register 662. Inverse inverter 666 is connected to data bus 692, and finite field GF Any element on To or Convert output to expression. The inverse transformer 666 is used when performing a division operation during an error correction operation. Trace converter 668 is connected to data bus 692 and is used for dual symbol error correction, . The conversion table for this is performed as already described in Table 1 above. The second signal selector 670 is connected to the data bus 692 to selectively output data on the 8-bit internal data bus or data output from the inverse transformer 666. The third signal selector 672 is connected to the data bus 692 to selectively output data on the 8-bit internal data bus or data passed through the trace converter 668. The MA register 674 temporarily stores the signal output from the second signal selector 670. The MB register 676 temporarily stores the data output from the third signal selector 672. The AB register 678 is connected to the data bus 692 to temporarily store data. The TEMP register 680 is connected to the data bus 692 and temporarily stores the temporary data generated during the operation. The syndrome generator 682 is connected to the data bus 692 to generate syndrome elements ≪ / RTI > To 3A and 3B show the embodiment of the present invention. The C1 / C2 plug generator 684 is connected to the data bus 692, adds the plug information to each code data after the error correction processing, or copies the plug information. The RAM 686 is connected to the data bus 692 to store important coefficient data or various roots generated during error correction operations. The multiplier 688 multiplies the signal output from the MA register 674 and the signal output from the MB register 676 as an input signal, . The adder 690 receives the signal output from the multiplier 688 and the signal output from the AB register 678 as an input signal, Add the elements above. The adder 690 is composed of an exclusive-OR gate.

According to the present invention as described above, the following effects are obtained.

In the Reed-Solomon error correction apparatus used in a conventional digital A / V (Audio / Video) apparatus, two errors are corrected in the C1 code and four in the C2 code. 2 Error Correction If 8 or more burst errors occur as the number of code words, error correction can not be performed. However, if 4 laser correction is performed as in the present invention, It is possible to perform an error correction even if an error occurs.

Claims (18)

An error correction method for correcting an error of data using a Reed-Solomon code in the reproduction of a digital signal, Calculating a syndrome from a received signal (step 400); Determining a number of errors using the error number discriminant by the syndrome calculated in the syndrome calculation step (operation 400); Performing error correction according to the number of errors determined in the error count determination step (operation 404); A state searching step (step 406) of performing a state search of the system after the number of errors determined in the error number determination step (step 402) is '0' or after performing the error correction step (step 404); And A plug setting step of determining whether the searched state is good in the state searching step (step 406) and whether the number of errors determined in the error number determination step (step 402) is greater than or equal to 3 and setting the plug to 0 or 1 Step 408) And, A syndrome calculation step 500 for calculating a syndrome from a received signal; An error number discrimination step (step 502) of discriminating an error number using an error number discrimination formula by the syndrome calculated in the syndrome calculation step (step 500); If it is determined that the number of errors identified in the error count determination step 502 is '2', it is determined whether the current error position coincides with the position of the error set in the plug setting step (step 408) of the C1 decoding process Determining whether the plug is matched (step 504); If the number of errors determined in the error count determination step 502 is '1' through the error number determination step 502 and / or the plug matching determination step 504, a '1' error correction is performed An error correction step (step 506) of performing '2' error correction if the determination of the plug match determination step (step 504) matches the position of the error currently detected and the error position set in the C1 decoding process; Determining whether or not the laser is corrected if the number of errors detected in step 502 is greater than '2' (step 508); A first number of plugs (step 510) for determining the number of plugs if the determination of step 508 is 'ON'; If the number of plugs determined in the first number of plugs determination step 510 is '3' or '4', '3' / '4' performing laser correction of '3' / '4' (Step 512); In the laser correction step '3' or '4', after the laser correction of '3' or '4' is performed in the laser correction step 512, a check is performed to check whether the laser correction is performed correctly (Step 514); The determination of the plug matching determination step (step 504) through the plug matching determination step (step 504) and / or the laser correction determination step (step 508) A second number of plugs (step 516) for determining the number of plugs if the position of the set error does not coincide or the determination of the laser correcting step 508 is 'OFF'; And a C2 setting step of setting a plug after the syndrome calculation step (500) to the plug number second determination step (516) is performed (518). 2. The method of claim 1, wherein in the syndrome calculation step (400) The syndrome when a single symbol error occurs , And the syndrome when a double symbol error occurs , And the syndrome when a triple symbol error occurs , And the syndrome when a quadruple symbol error occurs The error correcting method. The method of claim 1, wherein the error number determination step (402) And, a) If there is no error b) When a single symbol error occurs c) When a double symbol error occurs d) If an error of more than triple symbol occurs In cases other than the above a), b), and c) And the number of errors is determined as the number of errors. 4. The method of claim 1 or 3, wherein the error number determination step (402) Determining whether the number of errors is '0' (step 402-1); Determining whether the number of errors is '1' (step 402-2); And And determining whether the number of errors is '2' (step 402-3). 2. The method of claim 1, wherein the error correction step (404) If the number of errors identified in step 402 is '0', error correction is not performed. If the number of errors is '1', error correction is performed in step 1 (step 404-1) And if the number of the identified errors is '2', '2' error correction is performed (step 404-2) The performance of the '1' error correction (step 404-1) X1 = ==== Error location Y1 = ==== Error value , And the execution of the '2' error correction (step 404-2) In case of 2-symbol error, the error location polynomial with error locus X1, X2 , The polynomial equation , The polynomial can be expressed by Equation (14) below, &Quot; (14) " (here, ego, ) Also, Trace of To Wow If you write an expression to distinguish it, , And the finite field GF , M = 8, and therefore, Wow Can be expressed by Equations 15 and 16, respectively, &Quot; (15) " &Quot; (16) " From equations (15) and (16) ego, , ≪ EMI ID = 14.0 > Throb and Can be expressed as the following Equation (17) &Quot; (17) " But or The following equation (18) can be obtained, &Quot; (18) " Here, y is GF Is an element within When you say The two roots represented by the above-mentioned equation (18) are determined, The and , The error positions X1 and X2 are expressed by the following Equation (19), and the error values Y1 and Y2 are expressed by the following Equation (20) &Quot; (19) " &Quot; (20) " Wherein error correction is not performed if the number of errors determined in the error correction step (404) is a number other than '0', '1', or '2'. The method as claimed in claim 1, wherein the state searching step (406) (Eight / Fourteen Modulation) data, a player operation state, a frame sync detection, and the like are detected as a step of searching for system characteristics, data, In this case, STATUS FLAG C1 FLAG Set / Reset Whether frame sync is detected Player operating status No Error One Error Two Error reset (OK) reset (OK) reset reset reset / set reset (OK) set (NG) reset reset / set set set (NG) reset (OK) reset reset / set set set (NG) set (NG) reset / set set set The error correcting method. 2. The method of claim 1, wherein the plug setting step (408) If the retrieved state is good in step 406, the plug is set to '0'. If the retrieved state is not good, the plug is set to '1' And if it is determined that the number of errors is equal to or greater than 3, the plug is directly set to '1' without going through the error correction step (404) and the state searching step (406). 2. The method of claim 1, wherein the plug setting step (408) If the retrieved state is good in the state searching step 406, setting the plug to '0' (step 408-1); And If it is determined that the retrieved state is not good in the state searching step 406 or if the number of errors determined in the error number determination step 402 is greater than or equal to '3', the error correction step 404 and the state And setting the plug directly to '1' without going through the search step (step 406). 2. The method of claim 1, wherein in the syndrome calculation step (500) The syndrome when a single symbol error occurs , And the syndrome when a double symbol error occurs , And the syndrome when a triple symbol error occurs , And the syndrome when a quadruple symbol error occurs The error correcting method. The method of claim 1, wherein the error number determination step (502) And, a) If there is no error b) When a single symbol error occurs c) When a double symbol error occurs d) If an error of more than triple symbol occurs In cases other than the above a), b), and c) And the number of errors is determined as the number of errors. 11. The method of claim 1 or 10, wherein the error number determination step (502) Determining whether the number of errors is '0' (step 502-1); Determining whether the number of errors is '1' (step 502-2); And And determining whether the number of errors is '2' (step 502-3). The method of claim 1, wherein the error correction step (506) is divided into a '1' error correction step (506-1) and a '2' error correction step (506-2) The execution of the '1' error correction step (step 506-1) X1 = ==== Error location Y1 = ==== Error value , And the execution of the '2' error correction step (step 506-2) In case of 2-symbol error, the error location polynomial with error locus X1, X2 , The polynomial equation , The polynomial can be expressed by Equation (14) below, &Quot; (14) " (here, ego, ) Also, Trace of To Wow If you write an expression to distinguish it, , And the finite field GF , M = 8, and therefore, Wow Can be expressed by Equations 15 and 16, respectively, &Quot; (15) " &Quot; (16) " From equations (15) and (16) ego, , ≪ EMI ID = 14.0 > Throb and Can be expressed as the following Equation (17) &Quot; (17) " But or The following equation (18) can be obtained, &Quot; (18) " Here, y is GF Is an element within When you say , The two roots expressed by the above-mentioned equation (18) are determined. and The error positions X1 and X2 are expressed by the following Equation (19), and the error values Y1 and Y2 are expressed by the following Equation (20). &Quot; (19) " &Quot; (20) " The method of claim 1, wherein the determination of the step of determining whether the laser is to be corrected (step 508) is as shown in the following table. [table] STATUS FLAG MICOM DATA Whether this laser is corrected Whether frame sync is detected Player operating status forced Erasure OFF reser (OK) reset (OK) reset ON reset (OK) set (NG) reset ON / OFF set (NG) reset (OK) reset ON / OFF set (NG) set (NG) reset ON / OFF do not care do not care set OFF 2. The method of claim 1, wherein the laser correction is performed in a laser correction step of '3' / '4' Is expressed by the following equation (21) &Quot; (21) " Also, the error location polynomial is given by the following equation (22) &Quot; (22) " In Equation 22, the coefficient of each degree Can be expressed as the following Equation (23) &Quot; (23) " Equation (22) becomes '0' if a triple symbol error occurs. Error location , The error values Y1, Y2, and Y3 are obtained by the following Equation (24), and the error values Y1, Y2, and Y3 are obtained by solving the three-way linear simultaneous equations of Equation (21) &Quot; (24) " '4' This laser correction is a syndrome element Is expressed by the following equation (25) &Quot; (25) " Also, the error location polynomial is as shown in the following Equation 26, &Quot; (26) " In Equation (26), the coefficient of each order is expressed by Equation (27) below, &Quot; (27) " Equation (26) becomes '0' if a quad-symbol error occurs, And the error values Y1, Y2, Y3, and Y4 are as shown in the following Equation (28) when the 4-element linear simultaneous equations of Equation (25) are solved. &Quot; (28) " The method of claim 1, wherein the plug setting step (518) A plug '0' setting step (step 518-1), a plug '1' setting step (step 518-2) and a plug 'copy' setting step (step 518-3) If it is determined in step 502-1 that the number of errors in the error count determination step 502 is '0' (step 502-1), there is no error currently detected, If the '1' or '2' error is corrected in the '1' / '2' error correction step (step 506), or if the result of the checking in step 514 is good, Setting, The plug 1 setting step 518-2 may be performed when the number of plugs determined in the plug number first determination step 510 is '0', '1', '2' Or when the number of plugs determined in the second number of plug determination step 516 is '1' or '2', the plug is set to '1' The plug 'copy' setting step 518-3 may be performed when the number of plugs determined in the plug number first determination step 510 is '5' or the plug number is determined in the plug number second determination step 516 And sets the plug to 'copy' when the number of plugs exceeds '2'. An error correction apparatus for correcting errors in data using a Reed-Solomon code in the reproduction of a digital signal, the apparatus comprising: An embedded program ROM in which an error correction decoding algorithm is coded; A program register for storing an instruction output from the program ROM; A program decoder for outputting a control signal according to a predetermined coding format to an instruction stored in the program register; A signal output from the program decoder and a signal output from the error correction operation unit are used as an input signal to hold a specific step or instruction at the time of error correction for a predetermined period, A jumping control unit A program address counter for counting an address by a signal output from the program register, a signal output from the program decoder, and a control signal output from the jump control unit; And And an arithmetic control unit for generating an input / output adjustment signal of code data necessary for error correction according to the signal outputted from the program decoder, And, A data bus for interfacing signals between each component; An address generator for generating code data necessary for error correction and an address for use in reading / writing a plug; And is connected to the data bus, Any element on To an integer value ( ) To convert converter; Connected to the data bus and having an integer value ( ) To a finite field GF Any element on To convert converter; A C1 plug counter connected to the data bus for reading the C2 code data at the time of correcting the C2 code error and then reading the C1 plug at the time of counting the number of C1 plugs; A zero counter connected to the data bus for detecting zero data and measuring the number and outputting the number of measurements; An input / output register connected to the data bus for inputting / outputting code data and plugs; An output signal from one side output from the address generator, An error location storage register for storing a location of an error generated during an error correction operation as an integer value and storing the location of the erasure output from the address generator as an integer value using an output signal of one side output from the converter as an input signal; A first signal selector for selectively outputting a signal output from the address generator and output from the error location storage register; And is connected to the data bus, Any element on To or Inverted output to convert to expression; And is connected to the data bus and used for error correction of the double symbol, A trace transformer for obtaining a root of the trapezoid; A second signal selector connected to the data bus for selectively outputting data on the 8-bit internal data bus or data output from the inverted data bus; A third signal selector connected to the data bus for selectively outputting data on an 8-bit internal data bus or data passed through the trace converter; An MA register for temporarily storing the signal output from the second signal selector; An MB register for temporarily storing data output from the third signal selector; An AB register connected to the data bus for temporarily storing data; A TEMP register connected to the data bus for temporarily storing temporary data generated during operation; Connected to the data bus and generating syndrome elements A syndrome generator for obtaining a syndrome; A C1 / C2 plug generator connected to the data bus and adding plug information or copying plug information to each code data after error correction processing; A RAM connected to the data bus for storing important coefficient data or various roots generated during an error correction operation; The signal output from the MA register and the signal output from the MB register are used as input signals, A multiplier for multiplying the elements on; And And outputs the signal output from the multiplier and the signal output from the AB register as input signals to the finite field GF And an error correcting operation unit having an adder for adding elements on the error correction unit. 17. The error correction apparatus of claim 16, wherein the inverse encoder is used when performing a division operation during an error correction operation. 17. The error correction apparatus of claim 16, wherein the adder comprises an exclusive-OR gate.