JP2662457B2 - BCH code decoding circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for decoding a BCH code, which is an error correction code used in an image transmission device or the like.

2. Description of the Related Art Errors occurring on a communication channel are classified into random errors and burst errors according to their patterns. There is an error correction code as a technique for suppressing the influence of these errors and improving the reliability.

The BCH code, which is one of the error correction codes, is capable of random error correction and burst error correction.

The decoding process for random error correction of the BCH code includes the following four steps.

(1) Calculate the syndrome from the received sequence.

(2) Find the number of error positions.

(3) Find the magnitude of the error.

(4) Perform error correction.

However, the third step is omitted in the binary BCH code, and the error correction is performed by simply changing the digit in which the error has occurred from 0 to 1 or from 1 to 0.

Further, decoding processing for burst error correction can be performed by obtaining a syndrome and checking whether it is 0 or not.

When applying the error correction code to an actual communication system,
It is clarified whether an error occurring in a communication path is a random error or a burst error, and error correction is performed by a decoding process suitable for each error.

 FIG. 8 is an example of a BCH code decoding circuit.

In the figure, received data Din is supplied to a random error correction circuit 14 and a burst error correction circuit 15, and error correction of the received data Din delayed by a data delay circuit 16 is performed. The data corrected by the random error correction circuit 14 and the burst error correction circuit 15
The data supplied to the selector 17 is output as decoded data Dout.

Here, the data from the random error correction circuit 14 is selected when used in a communication path where a random error is predicted to occur, while the burst error correction circuit is used when used in a communication path where a burst error is predicted to occur. The selector 17 is preset so that the data from 15 is selected.

[Problems to be Solved by the Invention] In the example of FIG. 8, when the selector 17 selects the data from the error correction circuit 14 and the received data Din includes a burst error, Receive data Din with data from 15 selected
Contains a random error, the erroneously corrected data is output as decoded data Dout.

Therefore, the present invention is intended to prevent the output of erroneously corrected decoded data.

[Means for Solving the Problems] The present invention provides a first syndrome generation circuit that obtains a syndrome for random error correction from received data that has been BCH-encoded, and a random number from the syndrome from the first syndrome generation circuit. A random error pattern detection circuit for detecting an error pattern; a second syndrome generation circuit for obtaining a syndrome for burst error correction from the received data; and a burst error pattern from the syndrome from the second syndrome generation circuit. Burst error pattern detection circuit, the relationship between the syndrome for random error correction and the syndrome for burst error correction for all patterns of correctable random and burst errors occurring in the received data is determined in advance, random and bar A memory for storing an error type corresponding to the syndrome state of the strike error correction, and referring to the contents of the memory from the syndrome states of the first and second syndrome generation circuits and included in the received data. An error pattern determining circuit for determining whether the error is a random error or a burst error; and selecting one of the random error pattern detecting circuit and the burst error pattern detecting circuit according to the determination result of the error pattern determining circuit. And
And an error correction circuit for correcting an error of the received data based on the selected error pattern.

[Operation] By referring to the contents of the memory storing the types of errors corresponding to the states of the syndromes S1 and S3 for random error correction and the syndrome S for burst error correction obtained from the received data Din, an error can be obtained. An error pattern is determined by the pattern determination circuit 9.

When the error correction circuit 11 is performing a process for random error correction, when it is determined that the error included in the received data Din is a burst error, the process is changed to a process for burst error correction. Conversely, when the error correction circuit 11 is performing a process for burst error correction, when the error included in the received data Din is determined to be a random error, the process is changed to a process for random error correction. .

As described above, the error correction circuit adaptively performs correction processing on an error whose error pattern can be determined, so that erroneously corrected data is not output as decoded data Dout.

Embodiment An embodiment of the present invention will be described below with reference to FIG.

Here, it is a (511,493) BCH code, and the generator polynomial g (X) is g (X) = (X ₉ + X ₄ +1) × (X ₉ + X ₆ + X ₄ + X ₃ +1) (1) An example is described.

In the figure, Din is received data, which is a data sequence that has been BCH encoded.

This received data Din is supplied to a syndrome generation circuit 2 for random error correction.

As shown in FIG. 2, the syndrome generation circuit 2 performs division by X ₉ + X ₄ +1 and X ₉ + X ₆ + X ₄ + X ₃ +1 so that two sets of 9-bit shifts by 1-bit delay circuits 19 to 36 are performed. Register, exclusive OR gate 37-42, latch circuit
It is composed of 43 and 44.

In this case, the reception data Din has 493 information bits.
Every 511 of the 18 check bits are sequentially input from the first bit of the information bit and division is performed. At the end of the input of 511 bits, syndromes S1 and S3 of 9 bits are obtained and output from the latch circuits 43 and 44, respectively.

From the values of the syndromes S1 and S3, the error state of the reception data Din can be determined as follows.

When S1 = 0, S3 = 0, when no error ^{S1 ≠ 0, S3 = S1 3} , when a single error ^{S1 ≠ 0, S3 ≠ S1 3} , when the double error S1 = 0, S3 ≠ 0, Three or more errors occur. The syndromes S1 and S3 output from the syndrome generation circuit 2 are supplied to an error locator polynomial calculation circuit 3.

The error locator polynomial calculation circuit 3 includes selectors 45 and 46, a subtraction circuit 47, a squaring circuit 48, and an addition circuit 49, as shown in FIG.

A ROM 4 is connected to the error locator polynomial calculation circuit 3. The ROM 4 stores data for converting a syndrome from a vector into an exponent and from an exponent into a vector.

In the error locator polynomial calculation circuit 3, the syndrome S
1. Based on S3, coefficient σ1, of error locator polynomial σ (Z)
σ2 is determined. Error locator polynomial σ (Z), coefficient σ1,
σ2 is represented by the following equation.

σ (Z) = 1 + S1Z + (S3 / S1 + S1 ² ) Z ₂ (2) σ1 = S1 (3) σ2 = S3 / S1 + S1 ² (4) Here, S3 / S1, which is a finite field division, is ROM4. Is obtained as follows.

First, S1 and S3 given as vectors are input as addresses of the ROM 4, and are converted into exponents 1ogS1 and 1ogS3, respectively. At this time, input of S1 and S3 to ROM4 is controlled by selector 45, and output from ROM4 is controlled by selector 46, and logS1 and logS3 are obtained.

Next, in the subtraction circuit 47, 1ogS output from the selector 46 is output.
Using 1 and 1ogS3, 1ogS3-1-1ogS1 is calculated.

Next, the result of is input as the address of ROM4, and S3
/ S1 is obtained.

Σ2 is obtained this way S1 ² obtained in S3 / S1 and squaring circuit 48 obtained is added by the adding circuit 49.
Note that σ1 is the same as S1.

The coefficient σ obtained by the error locator polynomial calculation circuit 3
1 and σ2 are supplied to the random error pattern detection circuit 5. The error pattern detection circuit 5 detects a random error pattern based on the coefficients σ1 and σ2.

The detection of the random error pattern is performed by finding the root of the error locator polynomial σ (Z) by Chien's algorithm. That is, using the coefficients σ1 and σ2 as initial values,
The position where (Z) = 0 is detected.

The random error pattern detected by the error pattern detection circuit 5 is supplied to an error correction circuit 11.

The received data Din is supplied to a syndrome generation circuit 6 for burst error correction.

As shown in FIG. 4, the syndrome generating circuit 6 generates a generating polynomial X ¹⁸ + X ¹⁵ + X ¹² + X ¹⁸ + X ⁸ + X ⁷ + X ⁶ + X ³ +
1-bit delay circuits 50 to 67 for performing division by 1
18-bit shift register, exclusive OR gates 68 to 75,
It is composed of a latch circuit 76.

In this case, the reception data Din has 493 information bits.
Every 511 of the 18 check bits are sequentially input from the first bit of the information bit and division is performed. When the input of 511 bits is completed, an 18-bit syndrome S is obtained and output from the latch circuit 76.

The syndrome S output from the syndrome generation circuit 6 is supplied to the syndrome circulating circuit 7 and circulated.

As shown in FIG. 5, the syndrome circulating circuit 7 has a generator polynomial X ¹⁸ + X ¹⁵ + X ¹² + X ¹⁸ + X ⁸ + X ⁷ + X ⁶ + X ³ +
1-bit delay circuits 77 to 94 for performing division by 1
18-bit shift register, exclusive OR gate 95-10
Consists of one.

In the cyclic processing, first, the syndrome S is set as an initial value in the 18-bit shift register, and thereafter the circuit is circulated 511 times in the 18-bit shift register. The syndrome S is circulated in the 18-bit shift register by the selector 102 in FIG. 5 until a burst error pattern is detected by a burst error pattern detection circuit 8 described later.

Further, twelve low-order parts of the syndrome S circulated by the syndrome circulating circuit 7 are supplied to a burst error pattern detecting circuit 8 (shown in FIG. 5).

The error pattern detection circuit 8 detects that all 12 low-order parts are 0, and accordingly, the selector 102
Is switched to output a burst error pattern.

Returning to FIG. 1, the burst error pattern detected by the burst error pattern detection circuit 8 is supplied to the error correction circuit 11.

The detection of the random error pattern in the error pattern detection circuit 5 and the detection of the burst error pattern in the error pattern detection circuit 8 are simultaneously performed in parallel.

The syndromes S1, S3, and S output from the syndrome generation circuits 2 and 6 are supplied to an error pattern determination circuit 9.

In the error pattern determination circuit 9, the syndrome S1,
Based on S3 and S, it is determined whether the error included in the received data Din is a random error or a burst error. This determination makes use of the fact that the error position can be uniquely determined according to the state of the syndrome, and is performed as follows.

(1) The relationship between the error included in the reception data Din and the state of the syndrome S1, S3, or S is determined in advance.

Syndromes S1 * and S3 * when a 2-bit random error occurs in the received data Din are obtained, and data "0" indicating the occurrence of a random error is stored in the storage means as data corresponding to the addresses S1 * and S3 *. “1” is stored as data for an address other than S1 * and S3 *.

Similarly, a syndrome S * when a burst error of up to 6 bits occurs in the received data is obtained, and data "1" indicating the occurrence of the burst error is stored in the storage means as data for the address of S *, and S * "0" is stored as data for addresses other than.

(2) When the error correction process is performed, as described above, the syndromes output from the syndrome generation circuits 2 and 6 are used.
S1, S3, and S are supplied to the error pattern determination circuit 9, and the determination is performed as follows.

As described above, the error pattern determination circuit 9 includes S1, S
3, ROM 103 as shown in FIG. 6 and FIG. 7 as storage means for storing the relationship between the state of S and the error pattern;
104 are provided.

(A) Outputting "0" when S1 and S3 are the addresses of ROM 103 (b) Outputting "0" when S is the address of ROM 104 (a), (b) If the condition of () is satisfied, it is determined that a random error has occurred.

For example, S1, S3, and S when an error occurs at the 11th and 100th bits of the reception data Din are as follows.

^{S1 = α 7 + α 5 +} α 4 + α 3 + α 2 + α + 1 = (010111111) ... (5) S3 = α 7 + α 6 + α 2 + α = (011000110) ... (6) S = α 17 + α 16 + α 15 + α 14 + α 13 + Α ¹² + α ¹⁰ + α ⁹
+ Α ⁷ + α ² + α = (111111011010000110) (7) That is, when S1 and S3 are the addresses of the ROM 103 as shown in FIG. 6, “0” is output because of a random error. However, when S is the address of the ROM 104, "0" is output because burst error correction cannot be performed in such a syndrome. Based on these output results, a random error is determined.

When it is determined that a burst error has occurred (a) When S1 and S3 are the addresses of ROM 103, “1” is output (b) When S is the address of ROM 104, “1” is output If the condition (b) is satisfied, it is determined that a burst error has occurred.

For example, the 11th bit, 12th bit and
S1, S3, and S when an error occurs at the 14th bit are as follows.

^{S1 = α 6 + α 5 +} α 4 + α 3 + α 2 + α = (001111110) ... (8) S3 = α 7 + α 6 + α 4 + α 3 + α + 1 = (011011011) ... (9) S = α 8 + α 7 + α 5 = ( (000000000110100000) (10) That is, when S is the address of the ROM 104 as shown in FIG. 7, a burst error occurs, and thus “1” is output.
However, when S1 and S3 are the addresses of the ROM 103, "1" is output because random error correction cannot be performed in such a syndrome. Based on these output results, it is determined that a burst error has occurred.

In the case where it is impossible to determine the error In cases other than the above, it is impossible to determine whether the error is a random error or a burst error based on the states of S1, S3, and S.

The data output from the ROMs 103 and 104 of the error pattern determination circuit 9 is supplied to the error correction circuit 11.

The received data Din is supplied to the error correction circuit 11 after being delayed by a predetermined time by the data delay circuit 10 for error correction processing. The data corrected by the error correction circuit 11 is output as decoded data Dout.

When the error correction circuit 11 determines that the error included in the received data Din is a random error in the data output from the error pattern determination circuit 9, the error correction circuit 11 corrects the error based on the random error pattern output from the error pattern detection circuit 5, That is, random error correction is performed. On the other hand, when it is determined that the error is a burst error, correction based on the burst error pattern output from the error pattern detection circuit 8, that is, burst error correction is performed. If it is impossible to determine whether a random error or a burst error is present, random error correction or burst error correction that is set in advance according to the state of the communication path is performed.

As described above, in this example, the error pattern determination circuit 9
Based on the output data, the error correction circuit 11
When Din includes a random error, random error correction is performed, while when received data Din includes a burst error, burst error correction is performed.

Therefore, according to this example, depending on whether the error included in the received data Din is a random error or a burst error, the error correction circuit 11 adaptively performs random error correction,
Since the burst error correction is performed, it is possible to prevent the erroneously corrected data from being output as the decoded data Dout.

Also, the syndrome generation circuits 2 and 6 output the syndromes.
At the time when S1, S3, and S are output, it is determined whether the error is a random error or a burst error. Therefore, there is an advantage that the processing required for the determination is not delayed.

Note that, in the above-described embodiment, the description has been made by taking the (511,493) BCH code as an example, but the structure using other BCH codes can be similarly configured.

Further, without being limited to the above-described embodiment, the method of obtaining the random error pattern and the burst error pattern can be realized by another method such as a method of directly obtaining an error position from a syndrome using a ROM or the like.

[Effects of the Invention] As described above, according to the present invention, it is determined whether an error included in received data is a random error or a burst error based on a syndrome, and the error correction circuit adaptively performs random Since the error correction and the burst error correction are performed, the correction can be correctly performed even with the error pattern which has been conventionally corrected by a simple circuit configuration. Therefore, it is possible to prevent erroneously corrected data from being output as decoded data. Also, by referring to the contents of the memory that stores the type of error corresponding to the state of the syndrome, it is determined whether the error is a random error or a burst error at the time when the syndrome is determined. There is also an advantage that no processing delay occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a syndrome generation circuit for random error correction, FIG. 3 is a block diagram of an error locator polynomial calculation circuit, and FIG. FIG. 5 is a block diagram of a syndrome cycling circuit, FIG. 6 is an explanatory diagram of error pattern determination when a random error occurs, and FIG. 7 is a diagram illustrating an error pattern determination when a burst error occurs. FIG. 8 is an explanatory diagram of error pattern determination, and FIG. 8 is a configuration diagram of an example of a conventional BCH code decoding circuit. 2. Syndrome generation circuit for random error correction 3. Error position polynomial calculation circuit 4. ROM 5. Random error pattern detection circuit 6. Syndrome generation circuit for burst error correction 7. Syndrome cyclic circuit 8. Burst error pattern detection Circuit 9: Error pattern determination circuit 10: Data delay circuit 11: Error correction circuit

Claims (1)

(57) [Claims] 1. A first syndrome generation circuit for obtaining a syndrome for random error correction from received data subjected to BCH encoding, and a random error pattern for detecting a random error pattern from a syndrome from the first syndrome generation circuit A detection circuit, a second syndrome generation circuit for obtaining a syndrome for burst error correction from the received data, a burst error pattern detection circuit for detecting a burst error pattern from the syndrome from the second syndrome generation circuit, A syndrome for random error correction and a syndrome for burst error correction for all patterns of correctable random and burst errors occurring in the received data are determined in advance, and the random and burst error correction syndromes are obtained. A memory storing the type of error corresponding to the state of the first and second syndrome generation circuits, and referring to the contents of the memory from the state of the syndrome of the first and second syndrome generation circuits to determine whether the error included in the received data is a random error. An error pattern determination circuit for determining whether a burst error, and an error pattern from any of the random error pattern detection circuit and the burst error pattern detection circuit according to the determination result of the error pattern determination circuit,
A BCH code decoding circuit comprising: an error correction circuit that corrects an error in the received data based on the selected error pattern.