JPH04150624A - Bch encoding/decoding circuit - Google Patents

Abstract

PURPOSE:To prevent a data whose error is corrected from being outputted as a decoded data by applying error correction depending whether an error included in the received data is a random error or a burst error. CONSTITUTION:When an error correction circuit 11 makes processing for random error correction and an error included in a reception data Din is discriminated to be a burst error, the processing is revised into burst error correction processing. When the error correction circuit 11 makes processing for burst error correction and an error included in the reception data Din is discriminated to be a random error, the processing is revised into random error correction processing. Since an error whose error pattern is discriminated is properly subjected to correction processing in the error correction circuit 11, it is prevented that a data whose error is corrected is outputted as a decoding data Dout.

Description

DETAILED DESCRIPTION OF THE INVENTION [Fields of Application] The present invention applies to decoding circuits for BCH codes, which are error correction codes used in image transmission devices and the like.

[Prior Art] Errors occurring on a communication path are classified into random errors and burst errors depending on their patterns.

Error correction codes are a technique for suppressing the influence of these errors and improving reliability.

The 'F3CH code, which is one of these error correction codes, is capable of random error correction and burst error correction.

The decoding process for random error correction of BCH codes consists of the following four steps.

(1) Calculate the syndrome from the received sequence.

(2) Find the number of error positions.

(3) Find the magnitude of the error.

(4) Perform error correction.

However, in the binary BCH code, the third step is omitted and error correction is performed simply by changing the erroneous digit from 0 to 1 or from 1 to O.

Further, decoding processing for burst error correction can be performed by finding a syndrome and checking whether it is 0 or not.

When error correction codes are applied to actual communication systems, it is made clear whether errors occurring on a communication channel are random errors or burst errors, and error correction is performed using decoding processing appropriate for each error.

FIG. 8 is an example of a BC)I code decoding circuit.

At the same time, the received data Din is supplied to the random error correction circuit 14 and the burst error correction circuit 15, and the received data Din delayed by the data delay circuit 16 is subjected to error correction. Random error correction circuit 14
The data error-corrected by the burst error correction circuit 15 is supplied to the selector 17, and the data selected by the selector 17 is output as decoded data D out.

Here, data from the random error correction circuit 14 is selected when used in a communication path where random errors are expected to occur, whereas data from the burst error correction circuit 14 is selected when used in a communication path where burst errors are expected to occur. Selector 17 is preset so that data from 15 is selected.

[Problems to be Solved by the Invention] In the example shown in FIG.
If the received data Din contains a burst error while the data from the error correction circuit 15 is selected by the selector 17, or if the received data Din contains a random error while the selector 17 selects the data from the error correction circuit 15, the error correction is performed. The decoded data is output as decoded data D out.

Therefore, the present invention prevents erroneously corrected decoded data from being output.

[Measures Pl for Solving the Problems] The present invention includes a first syndrome generation circuit that obtains a syndrome for random error correction from BCH encoded received data, and a syndrome generation circuit that generates a syndrome from the first syndrome generation circuit. A random error pattern detection circuit detects a random error pattern, a second syndrome generation circuit calculates a syndrome for burst error correction from received data, and a burst error pattern is detected from the syndrome from the second syndrome generation circuit. a burst error pattern detection circuit; an error pattern determination circuit that determines whether an error included in received data is a random error or a burst error based on syndrome states from the first and second syndrome generation circuits; An error correction circuit that selects an error pattern from either the random error pattern detection S path or the burst error pattern detection circuit according to the determination result of the determination circuit, and performs error correction of received data based on the selected error pattern. It is something that is biased towards.

[Operation] An error pattern is determined by the error pattern determination circuit 9 based on the states of the syndromes S1 and S3 for random error correction and the syndrome S for burst error correction obtained from the received data Din.

When the error correction circuit 11 is performing processing for random error correction, when it is determined that the error included in the received data Din is a burst error, the processing is changed to burst error correction.

Conversely, when the error correction circuit 11 is performing processing for burst error correction, when it is determined that the error included in the received data Din is a random error, the processing is changed to random error correction. .

In this way, the error correction circuit adaptively performs correction processing on errors for which the error pattern can be determined.
Erroneously corrected data will no longer be output as decoded data D out.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG.

Here, the (511,493) BCH code is
The generator polynomial g(×) is expressed as g (×) = (X'+X'+l) (X'+X'+X'+
An example will be described where X''+l).

In the figure, Din is received data, which is a BCH encoded data sequence.

This received data Din is supplied to syndrome generation port B2 for random error correction.

This syndrome generation circuit 2, as shown in FIG.
x'+x'+1 and X9+X6-+-X'+X3+1
In order to perform division by , it is composed of two sets of 9-bit shift registers with 1-bit delay circuits 19-36, exclusive OR gates 37-42, and latch circuits 43 and 44.

In this case, the received data Din is sequentially input from the first bit of the information bits every 511 bits consisting of 493 information bits and 18 check bits, and division is performed. When the input of 511 bits is completed, syndromes S1 and S3 of 9 bits each are obtained and outputted from latch circuits 43 and 44.

From the values of the syndromes S1 and S3, the received data D.
The error status of in can be determined as follows.

■No error when 51=0, 53=0■S1≠0,5
When 3=S13, single error ■S1≠0, S3≠SI
When S, double error■51=O, when S3≠0, 3
In addition, the syndromes S1 and S3 output from the syndrome generation circuit 2 are supplied to the error locator polynomial formation calculation circuit B3.

As shown in FIG. 3, this error locator polynomial generation circuit B3 includes selectors 45, 46, subtractor circuits 47, 2 east circuits 48,
It is composed of an adder circuit 49.

Note that a ROM 4 is connected to this error locator polynomial calculation circuit 3. The ROM 4 stores data for converting a syndrome from a vector to an index, and from an index to a vector.

In this error position polynomial generation circuit #I3, the syndrome S
1. Based on S3, the coefficient σ of the error locator polynomial 〇(2)
1. σ2 is calculated. Error locator polynomial σ(Z), coefficient σ1. σ2 is expressed by a linear expression.

σ (Z) = 1 ÷ SIZ+ (S3/S, 1+S1 2)
Z 2σ 1 = 81
・ ・ (3) σ2=S3/S1+S12
... (4) Here, S 3 which is division of a finite field
/S 1 is obtained using ROM4 as follows.

■First, Sl and S3 given as vectors are RO
Entered as address of M4, each with index 1ogs
l,'] o g S 3. At this time, the input of Sl and S3 to the ROM 4 is controlled by the selector 45, and the output from the ROM 4 is controlled by the selector 46, and logsl and logs3 are obtained.

■Next, in the subtraction circuit 47, using logsl and logs3 output from the selector 46, 10g5:3-
13-1o is calculated.

(2) Next, the result of (2) is input as the address of ROM 4, and S3/S1 is obtained.

S 3/S 1 and 2 east circuit 48 obtained in this way
S'12 obtained by is added in the adder circuit 49 and σ
2 is required. Note that σ1 is the same as sl.

In addition, the coefficient 01 obtained by the error locator polynomial calculation circuit 3
．． σ2 is supplied to the random error pattern detection circuit 5. In this error pattern detection circuit 5, the coefficient 01. σ2
Detection of random error patterns is performed based on .

Random error patterns are detected by finding the roots of the error locator polynomial σ(Z) using Chien's algorithm. That is, the coefficient σ1. The position where σ(Z)=O is detected using σ2 as an initial value.

The random error pattern detected by the error pattern detection circuit 5 is supplied to the error correction circuit 11.

Further, the received data Din is supplied to a syndrome generation circuit 6 for burst error correction.

This syndrome generation circuit 6, as shown in FIG.
Generator polynomial X”+X” +X” 1X1@10x” 10x
It is composed of an 18-bit shift register with 1-bit delay circuits 111150-67 for performing division by f+x'+x2+1, exclusive OR gates 68-75, and a latch circuit 76.

In this case, the received data Din is sequentially input from the first bit of the information bits every 511 bits consisting of 493 information bits and 18 check bits, and division is performed. When the input of 511 bits is completed, an 18-bit syndrome S is determined and output from the 5 latch circuit 176.

Furthermore, the syndrome S output from the syndrome generation circuit 6 is supplied to the syndrome circulation circuit 7 and circulated therein.

This syndrome circuit 7, as shown in FIG.
Generator polynomial X ``10X'' +X '2 +X '1
It is composed of an 18-bit shift register with 1-bit delay circuits 77-94 for performing division by 1x+1x+1, and exclusive OR gates 95-101.

In the cyclic processing, syndrome S is first set in the 18-bit shift register as an initial value, and then the 18-bit shift register is cycled 511 times. The selector 102 in the fifth section causes the syndrome S to circulate within the 18-bit shift register until a burst error pattern is detected in a burst error pattern detection circuit 88, which will be described later.

The 12 low-order parts of the syndrome S circulated by the complex syndrome circulation circuit 7 are supplied to the burst error pattern detection circuit 8 (shown in FIG. 5).

This error pattern detection circuit 8 detects that all 12 low-order parts are 0, and as a result, the selector 10
2 is switched and a burst error pattern is output.

Returning to FIG. 1, the burst error pattern detected by the burst error pattern detection circuit 8 is supplied to the error correction circuit 11.

Note that the detection of random error patterns in the error pattern detection circuit 5 and the detection of burst error patterns in the error pattern detection circuit 88 are performed simultaneously and in parallel.

In addition, the syndromes S ly, S3, and S output from the syndrome generation circuit 2.6 are the error pattern determination diagram #
l! 9.

In this error-repattern determination circuit 9, the syndrome Sl
, S3, and S, it is determined whether the error included in the received data Din is a random error or a burst error. This determination takes advantage of the fact that the error position can be uniquely determined depending on the state of the syndrome, and is performed as follows.

(1) In advance, the relationship between the error included in the received data Din and the state of syndrome S1, S3, or S is determined.

The syndrome Si, S3* when a 2-bit random error occurs in the received data Din is obtained, and data "0" indicating the occurrence of a random error is stored in the storage means as data for addresses 81* and 83*. 1 S,
"1pa" is stored as data for addresses other than S3*.

Similarly, the syndrome S zero when a burst error of up to 6 bits occurs in the received data is obtained, and the storage means stores data ``1'' indicating the occurrence of a burst error as data for the address of S zero, and data other than Ss. 0'' is stored as data for the address.

(2) When performing error correction processing, as described above, the syndromes S1, S3, and S output from the syndrome generation port 82.6 are supplied to the error pattern determination circuit 9,
The determination is made as follows.

As mentioned above, the error pattern determination circuit 9 includes Sl, S
3. As a storage means in which the relationship between the state of S and the error pattern is stored, R as shown in FIGS. 6 and 7 is used.
OMs 103 and 104 are provided.

■When determining a random error (a) When Sl and S3 are addresses of ROM103, output “0” (b’) When s is an address of ROM104, output “0”
” is output. If the conditions (a) and (b) are satisfied, it is determined that it is a random error.

For example, the 11th bit and 100th bit of the received data Din
81, S3, and S when an error occurs in the th bit are as follows:
It will look like this:

S 1 =α'+a'10α'+cy"+a'+cr+1
= (010111111) ・ (5) S3=α
7+α6+α2,000α = (011000110) ・ (6)
S = a "tena" tena "tena "tena" tena 120a1@+α9+α7+α2+α = (1111110110300'00110)・・
・ (7) In other words, the 61st! 5l-S3 as ROM10
If the address is 3, it is a random error, so it is “0”.
" is output. However, when S is the address of the ROM 104, burst error correction cannot be performed in such a syndrome, so "O" is output. From these output results, it is determined that it is a random error. be judged.

■When it is determined that it is a burst error (a) Sl, S
When 3 is the address of ROM103, “1” is output (b) When S is the address of ROM104, “1”
If the conditions (a) and (b) are satisfied, it is determined that there is a burst error.

For example, when an error occurs in the 11th, 12th, and 14th bits of received data, S1, S3 .
S becomes as follows.

S1=α6+α5+α−+α3+α2+α=(0011
11110) ・ (8) S3=α7+α6+α
4+α3+α+1=(011011011) ・
・ (9) S = αθ 107 + α mo = (000000000110100000) 10
) That is, when S is the address of the ROM 104 as shown in FIG. 7, it is a burst error.

1" is output. However, if Sl and S3 are ROM10
When the address is set to 3, "1" is output because random error correction cannot be performed in such a syndrome. Based on these output results, it is determined that it is a burst error.

(2) Cases in which error determination is not possible In cases other than (2) and (2) above, it is not possible to determine whether the error is a random error or a burst error based on the states of Sl, S3, and S.

In this way, ROMIO3, 1 of the error pattern determination circuit 9
The data output from 04 is supplied to error correction diagram #111.

The received data Din is supplied to the error correction circuit 11 after being delayed by a predetermined time as shown in data delay diagrams 1 and 10 for error correction processing. Then, data whose error is corrected using this error correction diagram jlIll is output as decoded data Dout.

In the error correction circuit 11, when it is determined that the error included in the received data Din is a random error based on the data output from the error pattern determination circuit 9, correction is performed using a random error pattern output from the error pattern detection circuit 5; In other words, rerandom error correction is performed. i side,
When it is determined that it is a burst error, correction is performed using the burst error pattern output from the error pattern detection circuit 8, that is, burst error correction is performed. In addition,
If it is not possible to determine whether it is a random error or a burst error, random error correction or burst error correction, which is preset according to the state of the communication channel, is performed.

In this example, based on the output data of the error pattern determination circuit 9, the error correction circuit performs random error correction when the received data Din includes a random error. If errors are included, burst error correction is performed.

Therefore, according to this example, the error correction circuit 11 adaptively performs random error correction and burst error correction depending on whether the error contained in the received data Din is a random error or a burst error. It is possible to prevent corrected data from being output as decoded data Dout.

Also, from the syndrome generation circuit 2.6, the syndrome S
Since it is determined whether the error is a random error or a burst error at the time when 1, S3, and S are output, there is also the advantage that there is no delay in the processing required for determination.

In addition, in the above-mentioned example, (511493)BC
This is explained using the H code as an example, but other B
Those using CH codes can be similarly configured.

Furthermore, without being limited to the above-mentioned embodiments, methods for determining random error patterns and burst error patterns include:
Other methods can also be used, such as a method of directly determining the error position from the syndrome using a ROM or the like.

[Effects of the Invention] As explained above, according to the present invention, it is determined based on the syndrome whether an error included in received data is a random error or a burst error, and the error correction circuit adaptively performs a random error. Since error correction and burst error correction are performed, error patterns that have conventionally been incorrectly corrected can be corrected correctly. Therefore, it is possible to prevent incorrectly corrected data from being output as decoded data. Furthermore, since it is determined whether the error is a random error or a burst error at the time the syndrome is determined, there is an advantage that there is no delay in the processing required for determination.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a syndrome generation circuit for random error correction, Fig. 3 is a block diagram of an error locator polynomial calculation circuit, and Fig. 4 is a block diagram of a syndrome generation circuit for random error correction. A configuration diagram of a syndrome generation circuit for error correction, FIG. 5 is a configuration diagram of a syndrome cyclic circuit, and FIG. 6 is an explanatory diagram of error pattern determination when it is a random error.
FIG. 7 is an explanatory diagram of error pattern determination when a burst error occurs, and FIG. 8 is a configuration diagram of an example of a conventional BCH code decoding circuit. Syndrome generation circuit for random error correction Error locator polynomial calculation circuit ROM Random error pattern detection circuit Syndrome generation circuit for burst error correction Syndrome cyclic circuit Burst error pattern detection circuit Error pattern determination circuit Data delay circuit Error correction circuit

Claims (1)

[Claims] (1) A first syndrome generation circuit that calculates a syndrome for random error correction from BCH-encoded received data, and a random error pattern detection circuit that detects a random error pattern from the syndrome from the first syndrome generation circuit. a second syndrome generation circuit that calculates a syndrome for burst error correction from the received data; a burst error pattern detection circuit that detects a burst error pattern from the syndrome from the second syndrome generation circuit; and an error pattern determination circuit that determines whether the error included in the received data is a random error or a burst error based on the syndrome state from the second syndrome generation circuit; selecting an error pattern from either the random error pattern detection circuit or the burst error pattern detection circuit;
and an error correction circuit that corrects errors in the received data based on the selected error pattern.