JPH01171327A - Decoder - Google Patents

Abstract

PURPOSE:To obtain a decoder with excellent error correction capability and detection efficiency by adding a detection signal at every information symbol at the cross position based on a 2nd detection signal and a 3rd detection signal with the information decoded by a 3rd decoding means. CONSTITUTION:An error correction detection circuit 15 by a 1st code and an error correction detection circuit 16 by a 2nd code are provided to eliminate errors as much as possible. Moreover, a 3rd detection circuit 17 is given to all the 1st code decided as the occurrence of an error by the error detection circuit 17 by the 1st code, a detection deciding circuit 18 checks whether or not the 3rd detection signal and the 2nd detection signal are given respectively to the 1st code word and the 2nd code word with respect to each information symbol and the detection signal is given to the information symbol when both are given. Thus, the range of detection is limited to the presence of error surely in the unit of the 1st code to obtain high detection efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error correction code decoder used to reduce deterioration due to noise during recording and reproduction of digital information such as images and audio.

BACKGROUND ART When using digital information such as images or sounds, it is necessary to correct errors therein. On the other hand, such digital information generally has redundancy, and since the total amount of data is extremely large, the information is often compressed using high-efficiency codes. However, when high-efficiency codes are used, errors that occur propagate and have a large impact on the original information, so error correction technology becomes an even more important issue.

FIG. 4 shows code word 1 that has been encoded with error correction.

It consists of an information symbol 2, a check symbol 3 based on a first code, and a check symbol 4 based on a second code. Also, each row of code word 1 is the first code word 5, and each column is the second code word 5.
This is code word 6.

A conventional decoder corrects some of the errors in each codeword of the first code, and provides a detection signal to the codeword in which there is a high possibility of an error. Thereafter, each code word of the second code is corrected mainly for erasures, a detection code is given to the code word in which an error has been detected, and the detection of the entire information symbol is determined. In Figure 5, the first code is (N1. N1-3, 4) Ree
d -Solomon code, the second code is (N2. N2
-2, 3) This is an explanatory diagram of a specific example when a Reed-3 olomon code is used. Figure 5a is an explanatory diagram showing the occurrence of an error, and Figure 5 shows the state after single error correction using the first code. FIG. 5C is an explanatory diagram showing the state after single erasure correction using the second code. In FIG. 6, 7 is an information symbol in which an error has occurred, 8 is a first code word that has a single-corrected detection signal and is actually erroneously corrected, 9 is an erroneously corrected information symbol, and 10 is an error detection signal. 11 is the first codeword that has a single-corrected detection signal and was actually correctly corrected; 12 is the second codeword that has a detection signal; 13 is the actually corrected codeword; The information symbol 14 in which an error occurred and was detected as an error is an information symbol that is actually correct but is detected as an error. However, when high-efficiency encoding is performed, the minimum processing unit of data is usually based on the first code word, not the signal symbol, so memory is required when performing inverse transformation of high-efficiency encoding. It becomes necessary to rearrange the information symbols using

Problems to be Solved by the Invention However, the above configuration may not provide sufficient error correction ability when used in, for example, a VTR. In addition, a detection signal is added to the code words that have been correctly corrected by the first code because of the possibility of erroneous corrections, and if there is an erroneous correction at the time of correction by the second code, it becomes impossible to detect. Detection signals are added to possible code words, resulting in poor error detection efficiency.

In view of these points, it is an object of the present invention to provide a decoder with excellent error correction ability and detection efficiency.

Means for Solving the Problems The present invention performs error correction or detection for each first codeword, and applies one or more types of first detection signals to codewords with a high possibility of error correction and codewords that cannot be corrected. A first decoding means to add the information decoded by the first decoding means is subjected to error correction, erasure correction, or detection for each second code word so that the first detected code and the error position match. a second decoding means for adding one or more types of second detection signals to codewords with a high possibility of miscorrection and codewords that cannot be corrected; and information decoded by the second decoding means. The third decoding means performs error detection again for each first code word and adds the third detection signal to the third code word to the code word in which an error has been detected. and detection means for adding a detection signal to each information symbol at a position where the third detection signal intersects the third detection signal.

Function: The present invention makes it possible to detect erroneous corrections at the time of second code correction using the third decoding means, which was previously impossible. By correcting code words that were only detected out of fear,
A decoder with superior error correction ability compared to conventional decoders is constructed. On the other hand, since the third detection signal is not added to the correctly corrected first code word by the third decoding means, a decoder with higher detection efficiency than the conventional one is constructed.

Embodiment FIG. 1 shows Reed-So in the first embodiment of the present invention.
FIG. 1 is a block diagram of a decoder for a 1 omon dual code. In FIG. 1, 15 is an error correction detection circuit based on the first code, 16 is an error correction detection circuit based on the second code, 17 is an error detection circuit based on the first code, and 18 is a detection determination circuit. The operation of the decoder of this embodiment configured as described above will be described below. First, a first detection signal is applied to each code word that has only been detected by the error correction detection circuit function based on the first code. After that, the errors are corrected by the second code and their positions match the positions indicated by the first detection signal, and the correctable erasures are corrected. A second detection signal is given to each code word that is impossible and has only been detected.

Furthermore, the error detection circuit 17 based on the first code applies a third detection signal to all the first code words determined to have an error, and the detection determination circuit 18 applies a third detection signal to each information symbol including the error detection circuit 17. It is checked whether a third detection signal and a second detection signal are given for the first code word and the second code word, respectively, and if both are given, a detection signal is given to the information symbol.

As described above, according to this embodiment, as many errors as possible are removed by providing the error correction detection circuit 15 using the first code and the error correction detection circuit 16 using the second code, and furthermore, the error correction detection circuit 15 using the first code is provided. By providing the circuit 17, it is possible to almost completely prevent errors from remaining. On the other hand, the first
By providing the code-based error detection circuit 17, the detection range is limited to those in which an error definitely exists in the first code word unit, and high detection efficiency can be obtained. In addition, in order to perform inverse transformation of high-efficiency encoding using the first codeword as a reference,
Conventionally, it was necessary to rearrange the data output for each second code word at the end of decoding, but the scale of the circuit for this operation and the error detection circuit based on the first code are almost the same, so overall The scale of the decoder is the same as the conventional one.

FIG. 2 shows the first code (N
1', N1-3, 4) Reed-Solomo
Reed the n code and the second code (N2.N2-2, 3)
3 is a block diagram of a decoder for a double code using a -3olomon code. FIG. Double error and double erasure correction circuit; 21 is an error detection circuit based on the first code; 22 is a detection/judgment circuit; 23 is an information symbol in which an error has occurred; 24 is a first detection signal that is actually incorrectly corrected. a first code word, 25 is an error-corrected information symbol, 26 is an error-detected first code word with a first detection signal, 27 is a first code word with a correctly single error-corrected first detection signal; 28 is a second code word to be subjected to double erasure correction during second code correction, 29 is a second code word to be subjected to single erasure correction during second code correction, and 30 is a first detection signal during second code correction. 31 is a second code word having a second detection signal, which is to be corrected for 1M errors at the position where the second code word has a second detection signal. The operation of the decoder of the second embodiment configured as described above will be explained below. First, the single error correction double error detection circuit 19 using the first code corrects or detects each first code word, and applies the first detection to the single error corrected code word and the code word in which an error has been detected. give a signal. If an error occurs as shown in the explanatory diagram of FIG. 3A, the state shown in the explanatory diagram of FIG. 3A will be reached when the first code correction is completed.

After that, the single error and double erasure correction circuit 2o based on the second code performs single error correction, single and double erasure correction, and double erasure correction at the position that matches the first detection signal of each second code word. , a 1M error corrected code word, a double erasure corrected code word, and an error detected code word. If the first code correction results in a state as shown in the explanatory diagram of Figure 3C, then when the second code correction is completed, all errors have been correctly corrected as shown in the explanatory diagram of Figure 3C. becomes. Further, a third detection signal is applied to all the first code words determined by the first code error detection circuit 21 to have an error, and the detection determination circuit 22 applies the third detection signal to the second detection signal and the third detection signal. A detection signal is given to each information symbol for which it is determined that an error has been detected. If the state shown in the explanatory diagram of FIG. 3C is obtained by the second code correction, there is no error-detected first code word at the end of the first code detection, so the information symbol to which the detection signal is given is All information symbols can be obtained correctly without any problems.

Note that although the embodiment is an example of a Reed-Solomon double code, it is applicable to any double code. Further, the ratio of error correction and detection in each decoding means for the first code and the second code can be arbitrarily distributed.

Further, in each decoding means, the detection signals given to code words with a high possibility of error correction and code words that cannot be corrected may be assigned to two or more types, or may be combined into one type.

In addition, it is possible to improve the error correction ability and detection efficiency by using the same decoding method for codes encoded three times or more. In the above explanation, it is assumed that the second encoding is performed after the first encoding during error correction encoding, but the exact same code word can be obtained even if the first encoding is performed after the second encoding. is obvious, and shuffling of information symbols is also possible.

As described in detail, according to the present invention, it is possible to correct more errors with the same device size, and to significantly reduce residual error detection without increasing missed errors. 1 is a block diagram of a decoder according to one embodiment of the present invention, FIG. 2 is a block diagram of a decoder according to another embodiment of the present invention, and FIG. 3 is a block diagram of a decoder according to another embodiment of the present invention. 4 is an explanatory diagram of a specific example of the code word of a double code.
The figure is an explanatory diagram of a specific example of error correction by a conventional decoder.

16...Error correction detection circuit using first code, 1
6...Error correction detection circuit based on the second code, 1...Error detection circuit based on the first code, 18...Detection determination circuit.

Figure 3 Figure 4

Claims (1)

[Claims] A high-efficiency coded image or audio signal is divided into K_1 symbols each, and error correction or detection coding is performed on the first code word with a code length of N_1 symbols for each symbol, and the first code word is divided into multiple K_1 symbols. The collected information is further divided into K_2 symbols each, and each 2 symbols has a code length of N_2.
Error correction or detection coding is performed on the second code word of the symbol, and the second coded information is divided again into each first code word, and the information transmitted sequentially is corrected for each first code word. a first decoding unit that performs correction or detection and adds one or more types of first detection signals to codewords that are likely to be incorrectly corrected and codewords that cannot be corrected; error correction for each second code word,
A second method for performing erasure correction or detection and adding one or more types of second detection signals to codewords with a high possibility of error correction and codewords that cannot be corrected depending on the coincidence between the first detection signal and the error position. a third decoding means for performing error detection on the information decoded by the second decoding means again for each first code word and adding a third detection signal to the code word in which an error is detected; , a detection means for adding a detection signal to the information decoded by the third decoding means for each information symbol located at a position where the second detection signal and the third detection signal intersect, based on the second detection signal and the third detection signal. A decoder comprising: