JP2605269B2 - Error correction method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method applied to error correction of a reproduction signal of a digital audio disk (a so-called compact disk).

[Conventional technology]

The error correction code used in the compact disc is called a CIRC correction code (cross-interleaved Reed-Solomon code). In the CIRC correction code, the (28,24) Reed-Solomon code (28,24) is used for 24 symbols (one symbol is the upper 8 bits or lower 8 bits of the audio sample) of the 2-channel stereo audio data in the first arrangement state. (C2 code), and then the data array is rearranged from the first array state to the second array state by interleaving.
For symbols, the (32,28) Reed-Solomon code (C1
Sign) is encoded.

When decoding the CIRC correction code, C1 decoding is performed, then deinterleaving complementary to interleaving is performed, and further C2 decoding is performed. As a decoding method of the CIRC correction code, there are disclosed Japanese Patent Application Laid-Open No. 57-10557, Japanese Patent Application Laid-Open No. 57-10558, Japanese Patent Application Laid-Open No. 57-10559, Japanese Patent Application Laid-Open No. 57-10560,
The ones described in JP-A-57-10561 and JP-A-57-24143 are known. As a method for decoding a Reed-Solomon code, Japanese Patent Application Laid-Open Nos.
What is described in JP-A-197020 is known. In the conventional CIRC correction code decoding method, up to double error correction is performed in the first-stage C1 composite, and in the next-stage C2 decoding, C1
Double error correction is performed with reference to the pointer information obtained in the decoding.

As one of the decoding methods of the error correction code, an erasure correction in which an error location of an error symbol is indicated by known pointer information and the error symbol is corrected is known. Both the C1 code and the C2 code can correct up to a double error without erasure, and can correct up to a quadruple error if there is an erasure. Therefore, erasure correction may be performed to increase the error correction capability. In particular, erasure correction is effective for burst errors. On the other hand, to perform erasure correction, it is necessary to know the error location from the pointer information in advance, and it is necessary that the pointer information be highly reliable.

In the conventional CIRC correction code coding method, in the C1 decoder,
Since double error correction is performed and a triple error may occur at that time, the C1 pointer is sent to the next-stage C2 decoder, and the C2 decoder performs error correction using the C1 pointer. By performing erasure correction with this C2 decoder, it is conceivable to increase the error correction capability.

[Problems to be solved by the invention]

In the conventional CIRC correction code, as shown in FIG. 6, a C1 code sequence (C1 sequence) is formed by 32 symbols alternately included in two adjacent frames (1 frame: 32 symbols), and C2 The code sequence (C2 sequence) is formed by 28 symbols included in a predetermined frame in 108 frames. Since the interleave length of the C1 sequence is shorter than that of the C2 sequence, a problem occurs when a frame is lost and the continuity of the frame is lost when fast-forward playback (cue, review) is performed. That is, ± 1 before and after the discontinuity point
In the frame, the C1 pointer indicates that there is an error, but otherwise, the C1 pointer indicates that there is no error. On the other hand, since the C2 sequence has an interleave length of 108 frames, 108 frames including discontinuous points are:
It is not a correct C2 series. If erasure correction is performed on the incorrect C2 sequence using the C1 pointer, the error correction will be erroneous.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an error correction method capable of obtaining maximum correction capability by erasure correction and preventing erroneous correction when performing error correction of a CIRC correction code. .

[Means for solving the problem]

According to the present invention, a plurality of symbols in a first arrangement state are encoded with a first error correction code (C2 code) capable of m-level error correction and erasure correction of n-level errors, and a plurality of symbols are encoded. The arrangement of the symbols and the first check symbols of the first error correction code is rearranged into the second arrangement state, and the k symbols are arranged for the plurality of symbols and the first check symbols in the second arrangement state. In the error correction method, although the second error correction code (C1 code) capable of error correction has been coded, a plurality of symbols in the second arrangement state may have a C1 code.
A first code for performing error correction of a predetermined number of error symbols equal to or less than k and setting an error pointer for at least a predetermined number of error symbols;
And a second step of converting the second arrangement state to the first arrangement state; and C2 for a plurality of symbols in the first arrangement state.
A third step of performing erasure correction of up to n error symbols indicated by the error pointer set in the first step by using a code; and a fourth step of converting the first arrangement state to the second arrangement state. C1 for the plurality of symbols in the second arrangement state
The code corrects an error of a predetermined number of error symbols equal to or less than k, and sets an error pointer for at least a predetermined number of error symbols.
And a sixth step of converting the second arrangement state to the first arrangement state; and C1 for a plurality of symbols in the first arrangement state.
And a seventh step of performing error correction of a predetermined number of error symbols equal to or less than m by referring to the error pointer set in the fifth step by using a code.

[Action]

In the case of (k = n = 2) (m = 4), up to quadruple errors are corrected by erasure correction in C2 decoding after C1 decoding, so that error correction capability is improved. Since there is a possibility of erroneous correction in erasure correction, next, C1 decoding is performed, the correction result is verified, and erroneous correction can be prevented.

〔Example〕

Hereinafter, embodiments of the present invention will be described. This description is made according to the following items.

a. Basic method of decoding b. Erasure correction method of Reed-Solomon code c. Decoder of Reed-Solomon code d. Modification a. Basic method of decoding One embodiment of the present invention will be described with reference to the drawings. . This embodiment is a method for decoding a CIRC correction code employed in a compact disc. FIG. 1 is a block diagram showing the order of decoding.

The reproduction signal from the compact disk is EFM demodulated, and 32 symbols in one frame are supplied to the delay processing stage 1, only even symbols are delayed by one frame, and the delay given by the delay circuit on the encoder side is canceled. You. 32 symbols from the delay processing stage 1 are supplied to the C1 decoder 2,
The (32,28) Reed-Solomon code is decoded by the C1 decoder 2. The C1 decoder 2 corrects up to two error symbols in the C1 sequence. When three or more errors are detected in the C1 decoder 2, a C1 pointer with an error is set for all symbols in the C1 sequence.

The data corrected by the C1 decoder 2 and the error pointer are processed in a deinterleave processing stage 3. The deinterleave processing stage 3 performs a process of restoring the interleaving performed on the encoder side, and the output of the deinterleave processing stage 3 is supplied to the C2 decoder 4. The C1 pointer of each symbol generated by the C1 decoder 2 undergoes the same deinterleaving processing as the data in the deinterleaving processing stage 3. The delay processing and the deinterleaving can be performed by address control when data is read from the RAM. The C1 pointer is written into a part of the memory area of the RAM, and receives the same address control as that of the data. The C2 decoder 4 performs erasure correction up to a quadruple error using the C1 pointer. In the C2 encoder 4, when the erasure correction is completed, the C1 pointer is cleared, and the second time
No pointer information is transmitted to C1 decoding. Thus, 1
By not transmitting the C2 pointer for the second C2 decoding, RA
The memory area for storing the C2 pointer for the first time of M becomes unnecessary, and the memory capacity is saved.

Data from the C2 decoder 4 is supplied to an interleave processing stage 5. The interleave processing stage 5 returns the data arrangement to the same arrangement as at the time of reproduction. The output data of the interleave processing stage 5 is supplied to the delay processing stage 6, from which one frame (32 symbols) of data is obtained. Actually, since the data corrected by the C1 decoding processing stage 2 and the C2 decoding processing stage 4 are stored in the RAM, by controlling the read address of this data, the interleaving processing stage 5 and the delay processing stage 6 are controlled. Processing can be performed.

The 32-symbol data from the delay processing stage 6 is the C1 decoder 7
Supplied to The C1 decoder 7 decodes the (32,28) Reed-Solomon code and corrects up to a double error. The C1 decoder 7 sets the C1 pointer not only when there are three or more errors but also when a double error is corrected.

Output data from the C1 decoder 7 is supplied to a deinterleave processing stage 8 where the data is deinterleaved. The data of 28 symbols from the deinterleave processing stage 8 is
The data is supplied to the C2 decoder 9 and the (28, 24) Reed-Solomon code is decoded. The C2 decoder 9 corrects up to a double error with reference to the number and state of the C1 pointer. The output data from the C2 decoder 9 is supplied to a descramble processing stage 10, and the reverse of the scramble processing performed on the encoder side is performed. The decoding operation performed by the C1 decoder 7 and the C2 decoder 9 is the same as that of the CIRC correction code decoder provided in the reproduction circuit of the compact disc.

As described above, the quadruple erasure correction is performed in the C2 encoder 4 using the C1 pointer generated in the C1 encoder 2, so that the number of error symbols that can be corrected increases, and the error correction capability can be improved. it can. Erroneous correction in the case of performing erasure correction is eliminated by performing C1 decoding and C2 decoding again, and the risk of erroneous correction can be reduced. FIG. 2 is a graph for comparing the error correction capability of a conventional CIRC correction code decoder employed in a current compact disc with this embodiment.

The horizontal axis in FIG. 2 is the symbol error probability Ps before correction, and the vertical axis is the word error probability Pw before correction. In this embodiment, when uncorrection occurs, the correction capability is improved as shown by 11A, as can be seen from comparison with 11B which indicates that the conventional CIRC correction code decoder becomes uncorrectable. I have. Further, when an erroneous correction occurs in this embodiment, it is indicated by 12A, which is almost the same or slightly improved as compared with 12B when the conventional decoder becomes uncorrectable.

b. Erasure correction method for Reed-Solomon code In the case of Reed-Solomon code, erasure correction is generally performed by solving the following equation.

Where ν = 0 to d−2 n: number of erasures X _j : j-th error location Sν: syndrome Y _j : j-th error vector d: Hamming distance of code In this embodiment, the C2 decoder 4 , Erasure correction is performed, and the Hamming distance of the C2 code is (d = 5). For example, when four error symbols are included, the syndrome is as follows.

The code length of the C2 code is 28 and the received symbol
Respect ₀ to _27, if an error vector of Y ₁ to _n, Becomes That is, if there is one error in _n , (X ₁
= Α ⁿ ), then S ₀ = Y ₁ S ₁ = α ⁿ Y ₁ S ₂ = α ²ⁿ Y ₁ S ₃ = α ³ⁿ Y ₁ . The _{j of} X _j and Y _j merely ranks the errors in the received data.

For example, among the 28 symbols ₀ to ₂₇ received,
_{0, 5, 10, 18} 4 When there is an error in the _symbols, and _{0 = W 0 + Y 1 5} = W 1 + Y 2 10 = W 10 + Y 3 18 = W 18 + Y 4. (X ₁ = α ⁰ , X ₂ = α ⁵ , X ₃ = α ¹⁰ , X ₄ = α ¹⁸ ). Therefore, if the error is present in the four _{symbols, S 0 = Y 1 + Y} 2 + Y 3 + Y 4 S 1 = α 0 Y 1 + α 5 Y 2 + α 10 Y 3 + α 18 Y 4 S 2 = α 0 Y ^{_{1 + α 10 Y 2 + α}} 20 Y 3 + α 36 Y 4 S 3 = α 0 Y 1 + α 15 Y 2 + α 30 Y 3 + α 54 Y 4 is a syndrome resulting.

The error location X ₁ to X ₄ is C1 pointer, because it is known, as described below, the error vector Y ₁ to Y ₄ are obtained.

Becomes

The erasure correction method described above uses the error vectors Y _{1 to} Y ₄
As the number of calculations required to obtain, (addition: 40 times, multiplication: 40 times, division: 4 times), a total of 84 times are required. An improved erasure correction that can reduce the number of calculations will be described below.

The syndrome Sν (ν = 0 to n−1) and the error location X _j (j = 1 to n) are sequentially multiplied by the following rule, and the i-th answer is Sν _{, i} . _{That, Sν, i = Sν, i} -1 X i + Sν + i, i-1 (1 ≦ i ≦ n-1) where a _(Sν, 0 = Sν).

Thus, when S _{0, n−1} is obtained, Gives Y _n .

As described above, a decoding method for erasure correction of four error symbols (that is, n = 4) will be described. At first, S _0,3 = S _0,2 X ₃ + S _1,2 By, Y ₄ is obtained. Using this error vector,
Correct the original syndrome to the syndrome at the time of triple error. That is, S ₀ + Y ₄ → S ₀ S ₁ + X ₄ Y ₄ → S ₁ S ₂ + X ₄ ² Y ₄ → S ₂ The following calculation is performed on the syndrome after this correction, and the error vector Y ₃ is obtained.

S _0,2 = S _0,1 X ₂ + S _1,1 Y ₃ = S _0,2 / (X ₃ + X ₁ ) (X ₃ + X ₂ ) Hereinafter, similarly, the syndromes are corrected and Y ₂ and Y ₁ are corrected. Ask for.

S ₀ + Y ₃ → S ₀ S ₁ + X ₃ Y ₃ → S ₁ S _0,1 = S ₀ X ₁ + S ₁ Y ₂ = S _0,1 / (X ₂ + X ₁ ) S ₀ + Y ₂ → S ₀ Y ₁ = S ₀ A description of the following theorem for obtaining the above-described error vector Y _n will be given below. That is, Substituting ν = 0, i = n-1 into the equation of "Theorem 1" And Y _n was found.

c. Decoder for Reed-Solomon Code The decoder for the Reed-Solomon code has, for example, the configuration shown in FIG. In FIG. 3, an external RAM 22 is connected to an internal data bus 21 via a write register 23 and a read register 24. The internal data bus 21 is connected to an arithmetic logic (ALU), a syndrome register 26, and a working RAM. External R
The AM 22 stores data to be decoded, such as data reproduced from a compact disc.

The decoder shown in FIG. 3 has a microprogram system configuration, in which microinstructions are stored in a microprogram ROM 28.
Is read from. The micro instruction gives a control signal to each control unit via the register 29. Micro program RO
A program counter 30 is provided in association with M28. The internal state of each part is supplied to the judgment circuit 31, and the judgment circuit 31
A jump destination address generating circuit 32 is provided which generates a jump destination address in accordance with the output signal of 31 and supplies the jump destination address to the program counter 30.

In the decoder shown in FIG. 3, the syndrome is calculated by the ALU 25 from the data read from the external RAM 22,
This syndrome is stored in the syndrome register 26. The ALU 25 is configured to perform not only a syndrome operation but also a product-sum operation. Also working RAM27
Stores the error location obtained by the ALU 25 and the intermediate calculation results (Sν, _i, etc.).

FIG. 4 shows an example of the configuration of an ALU provided in the ALU 25 for performing erasure correction. Since the erasure correction process is performed by a product-sum operation, the ALU shown in FIG. 4 has a configuration in which a multiplication unit and an addition unit are cascaded.

In FIG. 4, logR connected to the internal data bus 21
The OM 41 is a ROM that outputs an exponent i (8 bits) when the element α ⁱ (8-bit data) on the Galois field is supplied as an address input. The output of the log ROM 41 is supplied to the adder 42, The output of the register 42 is supplied to a register 43, and the output of the register 43 is supplied to an inverse log ROM 44.
Will be returned to The adder 42 performs addition of exponents, that is, multiplication by α.

When the index i is supplied as an address input, the inverse logROM 44 outputs α ^i, and the output of the inverse logROM 44 is
Stored in 47. The output of register 47 is exclusive
It is supplied to the OR circuit (mod.2 adder). The output of the exclusive OR circuit 48 is supplied to the register 49,
The output of 49 is fed back to the exclusive OR circuit 48 and supplied to the internal data bus 21. Exclusive
The OR circuit 48 performs addition on the Galois field.

FIG. 5 shows a configuration of an ALU which can be used for both erasure correction and error correction. As in FIG. 4, the logROM 41, the adder 42, the register 43, the inverse logROM 44, the register 47, the exclusive OR circuit 48, and the register 49 constitute a product-sum operation circuit. In the double error correction of the Reed-Solomon code, a transform PLA 45 is required to solve the error location equation. Therefore, register 43
Is connected to an inverse log ROM 44 and a conversion PLA 45, and the outputs of both are supplied to a selector 46. The selector 46 selects the output of the inverse logROM 44 when performing a product-sum operation such as erasure correction, and selects the output of the conversion PLA 45 in a predetermined step when obtaining an error location during error correction.

〔The invention's effect〕

According to the present invention, by performing erasure correction, the error correction capability can be improved. Also,
In the erasure correction, even if an erroneous correction occurs, the erroneous correction can be detected by decoding in the next stage.

[Brief description of the drawings]

FIG. 1 is a block diagram according to the order of correction processing according to one embodiment of the present invention, FIG. 2 is a graph for explaining the error correction capability of the present invention, and FIG. 3 is a Reed-Solomon code usable in the present invention. FIG. 4 is a block diagram of an example of an ALU used in a Reed-Solomon code decoder, and FIG. 5 is a block diagram of another example of an ALU used in a Reed-Solomon code decoder. FIG. 6 is a schematic diagram used for explaining a code sequence of the CIRC correction code. Description of main symbols in the drawings 2,7: C1 decoder, 4,9: C2 decoder, 3, 8: deinterleave processing stage, 5: interleave processing stage.

Claims (1)

(57) [Claims] 1. A plurality of symbols in a first arrangement state are encoded with a first error correction code capable of m-level error correction and erasure correction of n-level errors. The first of the first error correction codes
Are rearranged into a second arrangement state, and the second plurality of symbols and the first check symbol in the second arrangement state are k-th error-correctable second arrangements. In the error correction method in which the error correction code is coded, the plurality of symbols in the second arrangement state are
A first step of performing error correction of up to a predetermined number of error symbols equal to or less than k by the second error correction code, and setting an error pointer for at least the number of error symbols exceeding the predetermined number; A second step of converting the second arrangement state to the first arrangement state; and a plurality of symbols in the first arrangement state,
A third step of performing the erasure correction of up to n error symbols indicated by the error pointer set in the first step by the first error correction code, and A fourth step of converting to the second arrangement state; and a plurality of symbols in the second arrangement state,
A fifth step of performing error correction of a predetermined number of error symbols equal to or less than k using the second error correction code, and setting an error pointer for at least the number of error symbols exceeding the predetermined number; A sixth step of converting a second arrangement state to the first arrangement state; and a plurality of symbols in the first arrangement state,
A seventh step of performing error correction of a predetermined number of error symbols equal to or less than m with reference to the error pointer set in the fifth step by the first error correction code. Error correction method.