JP2796291B2 - Error correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to recording / reproducing (or transmitting) digital signals.
In particular, the present invention relates to an error correction method using an error correction code in a symbol unit. [Related Art] Recently, error correction codes have been widely used for the purpose of improving the reliability of a recording / reproducing system or a communication system.
For example, an error correction code is also applied to a digital audio disk (CD), a digital VTR, and the like for converting an audio signal or a video signal into a digital signal for recording and reproducing.
In these devices, random errors and burst errors occur simultaneously due to the effects of fluctuations in the level of the reproduced signal and dropouts. Such an error is called a compound error. FIG. 2 schematically shows an error distribution in a device in which a random error and a burst error occur simultaneously. In FIG.
The horizontal axis indicates the length of the error, and the vertical axis indicates the frequency of occurrence of the error, that is, the number of occurrences. Further, an area X is an error caused by a random error, and an area Y is an error caused by a burst error. In a system in which such a composite error occurs, a double coding configuration in which an error correction code in units of symbols (hereinafter, 8 bits are regarded as one symbol) is applied in two stages as shown in FIG. 3 is employed. (JP-A-57-10557). In FIG. 3, a first (vertical) parity 40 is added in a vertical direction to the data 30 arranged two-dimensionally. Next, a second (horizontal) parity 50 is added in the horizontal direction. As this correction code, a Reed-Solomon code (hereinafter referred to as an RS code) capable of correcting an error in a symbol unit is widely used. This is because this code has a high correction capability and is easy to implement. The data 30 shown in FIG. 3 is sequentially recorded (or transmitted) in the horizontal direction, and finally the symbols of the vertical parity 40 are recorded. Note that A and A 'are random errors, and show a case where one bit in each symbol is an error. B and B 'are short burst errors, and indicate a case where a plurality of bits in each symbol are consecutively erroneous. C is a long burst error, and shows a case where short burst errors B continue. In decoding (or receiving), first, an error corresponding to the region X, that is, a random error, is corrected in symbol units using the symbols of the horizontal parity 50. If the error cannot be corrected, it is determined that a burst error has occurred in the area Y, and an erasure flag is generated. Next, the burst error that cannot be corrected in the horizontal direction is corrected using the symbol of the vertical parity 40. At this time, the above-described method of correcting an error using the erasure flag (erasure correction) has been widely applied due to high restoration efficiency. The capability of the error correction code is determined by the number of added parities. For example, by adding parity of 4 symbols to data, errors of 2 symbols or less can be corrected. However, when the correction of two symbols, which is the limit of the correction capability, is performed, the probability of erroneous correction (correction of erroneous data) occurring for a burst error of two or more symbols becomes extremely large. Conversely, if only detection is performed without correction, the ability to detect burst errors is high, but there is a problem that the ability to correct random errors is significantly reduced. For this reason, a method has been proposed in which, even when an error is determined to be two symbols, only one symbol or less is corrected, and both a correction capability and a detection capability are simultaneously provided (Japanese Patent Application Laid-Open No. 57-15757).
No. 10557). [Problems to be Solved by the Invention] However, since the above method limits the number of corrections, the probability of erroneous correction can be reduced, but there is a problem that the decoding characteristic of a random error in bit units against a burst error is greatly deteriorated. Atsuta. An object of the present invention is to provide an error correction method in which the probability of occurrence of erroneous correction is reduced without limiting the correction capability (the number of correctable errors). [Means for Solving the Problems] The above-described problem is caused by an error (two symbols) exceeding the set error number (one symbol in this example) less than the correction capability.
Has occurred because error detection was performed unconditionally without performing error correction. In the present invention, first, after correcting a symbol error less than the correction capability (for example, errors A and B of one symbol shown in FIG. 3), the correction capability (2 in the above example) is corrected for the codeword for which the error was detected. (Symbol) is calculated. Then, for correctable errors (A ', B' in FIG. 3), it is determined whether or not the error positions are continuous. Third
Correctable (2 symbols or less) as shown at B 'in the figure
If the error positions are continuous, it can be estimated that a short burst error has occurred. Therefore, in this case, the error is corrected. Even when the error positions are not consecutive, if the error pattern is two errors per bit as indicated by A ', it is determined that two random errors have occurred, and the error is also determined. To correct. In other cases, it is determined that a long burst error has occurred or a large number of random errors have occurred, and an erasure flag is generated without performing correction. When the code to be used has a double code configuration, the erasure correction is performed using the erasure flag in the second-stage correction.
In other cases, the data to which the erasure flag is added is replaced with correlated data, and processing such as interpolation and modification is performed. As a result, it is possible to sufficiently derive the correction capability inherent in the code without substantially increasing the error correction probability. [Operation] An outline of the present invention will be described below using an RS code as an error correction code. On the Galois field GF (2), an irreducible m-order polynomial F (x)
And this root is defined as α. In the following, m = 8 and F
As (x), F (x) = x ⁸ + x ⁴ + x ³ + x ² +1 is taken. In this case, α ⁸ + α ⁴ + α ³ + α ² + 1 = 0. The RS code is defined as a code having d-1 continuous roots of α. Now, as an example of d = 5, the generator polynomial G
(X) is G (x) = (x−1) (x−α) (x−α ² ) (x−
α ³ ), and the parity check matrix H is Becomes Here, n is the code length. Therefore, for data of (n-4) symbols, 4
Assuming that a codeword to which the parity of a symbol is added is V, this satisfies H · V ^t = 0. Here, V ^t is the transpose vector of V. This code has a distance d of 5 and is capable of correcting an error of 2 symbols or less. It is assumed that an error E occurs in recording / reproduction (or transmission), and the received word becomes W. W = V + E From this, the syndromes S ₀ , S ₁ , S ₂ , and S ₃ are represented by the following equations. If an error of two symbols occurs now, assuming that these two error positions are i, j and the magnitudes of the errors are e _i and e _j , S ₀ = e _i + e _j S ₁ = e _i α + e _j α S ₂ = Two error positions i, j and error magnitudes e _i , e _j can be calculated from the relational expression of e _i α ² + e _j α ² S ₃ = e _i α ³ + e _j α ³ (1). Here, the above calculations are all performed on Galois fields GF (2 ⁸ ). If one symbol error occurs, Holds. From this, the error correction i can be calculated, and the magnitude of the error e _i is determined from S ₀ = e _i . In the present invention, after correcting an error of one symbol from the above equation (2), 2
Calculate whether symbol error correction is possible. Then, when error correction of two symbols is possible, two error positions and error patterns are calculated. If the error location i, j is j
= I ± 1, that is, when error positions are consecutive, it is determined that a short burst error has occurred, and this is corrected. If the two error patterns are specific (for example, one bit) patterns, it is determined that a random error has occurred, and this is corrected. In other cases, it is determined that a long burst error or a large number of random errors have occurred, and an erasure flag is generated without correction. Before and after recording / reproduction (or transmission), a signal may be modulated / demodulated in a form suitable for a recording medium (or transmission path). In such a system, a random error is converted into an error pattern other than one bit (for example, a two-bit pair error), but two error corrections need to be performed only when the cause of the error can be determined to be a random error. . [Embodiment] FIG. 1 shows a flowchart of an error correction system according to the present invention. The code used is an error correction code in symbol units, and the number of correctable symbols is K. The portion surrounded by a dotted line is a portion necessary for error correction according to the present invention, and the other portion is a portion for performing normal symbol error correction. First, a syndrome is calculated for each symbol (Step 1), and it is determined from the relational expression between the syndromes whether or not M (0 <M <K) symbols can be corrected (Step 2). If correctable, calculate the magnitude and location of the error,
An error correction of M symbols or less is performed by taking an exclusive OR with the original data (step 3). If the error cannot be corrected, it is calculated whether or not an error of not less than M + 1 and not more than M symbols can be corrected (step 4). If the correction is impossible, an error is detected, an erasure flag is generated, and the processing is terminated (step 5). If the error can be corrected, the error position and error magnitude are calculated (step 6). Based on the result, it is determined whether or not the error positions are continuous (Step 7). If the error positions are continuous, it is estimated that a short burst error has occurred, and correction is performed (Step 9). If the error positions are not consecutive, it is checked whether the error size is in bit units (step 8). If the error size is in bit units, it is determined that a random error has occurred. To correct the error (step 9). In other cases, it is determined that a burst error or a large number of random errors have occurred, and decoding is terminated as error detection (step 5). Next, an embodiment of the present invention will be described with reference to the block diagram of FIG. The code shows the case where the number of parity is 4 symbols in the RS code. The data input to the input terminal 10 is input to a syndrome operation circuit 11 and calculates syndromes S ₀ , S ₁ , S ₂ , and S ₃ . The arithmetic circuit 11 includes an exclusive OR (EOR) circuit 111, a latch circuit 112, and an α arithmetic circuit 113 as shown in FIG. All data is processed in units of symbols (8 bits). S ₁ as an example of the α operation circuit 113
As a specific example of calculating, a circuit expressing α with an EOR circuit 114 is preferable as shown in FIG. 5 (B). Next, returning to FIG. 4, the one-symbol error calculation circuit 12 calculates Then, an error position A1 and an error magnitude B1 (= S ₀ ) are calculated from them and output to the switching circuit 18. Here, all operations are operations on Galois field GF (2 ⁸ ), and are read-only memory (RO
M) can be realized. Then, if one correction is possible, it outputs a one correction flag C1 to the control circuit 16. The control circuit 16 outputs 1 when the 1 correction flag C1 is input.
The correction control signal D1 is output to the switching circuit 18. The two-symbol error calculation circuit 13 calculates two error positions A2 and error magnitudes B2 from equation (1), and outputs them to the switching circuit 18, the error position determination circuit 14 and the error magnitude determination circuit 15 . If two corrections can be made, a two-correction flag C2 is output to the control circuit 16. (Note that if one correction is possible, the two correction flag C2 is not generated.) If the error position determination circuit 14 determines that the two error positions are continuous, the error position determination circuit 14 sets the correctable flag P to the control circuit 16. Output to The error magnitude determination circuit 15 outputs a correctable flag Q to the control circuit 16 when the magnitude of each error is 1 bit. The control circuit 16 outputs the two-correction control signal D2 to the switching circuit 18 when the correction flag C2 is present and either P or Q occurs. As shown in FIG. 6, when the one correction control signal D1 is "1", the switching circuit 18 outputs A1 as the error position A and B1 as the error magnitude B to the error correction circuit 20. Also 2
When the correction control signal D2 is "1", A2
Is output to the error correction circuit 20 as the magnitude of the error. Further, when both the 1-correction control signal D1 and the 2-correction control signal D2 become "0", the error position A and the error magnitude B are both output to the error correction circuit 20 as "0". At the same time, the erasure flag generation circuit 17 outputs the erasure flag F to the flag output terminal 22. As described above, 1
It is assumed that there is no state where both the correction control signals D1 and D2 are "1". Further, the input data is delayed for a certain period by the delay circuit 19 and is input to the error correction circuit 20. This error correction circuit 20
The delay data K, the error position A and the error magnitude B are input to the input terminal, the error is corrected by the EOR circuit, and the corrected data L is output to the output terminal 21. The above is a case where the RS code is used and the number of check points is 4 symbols. However, the present invention is not limited to this, and it goes without saying that the present invention can be applied to other cases. The order in which data is recorded and reproduced is not regular as shown in FIG. 3, and even if irregular (shuffling or interleaving), error positions of recorded / reproduced (or transmitted) data continue. Correction processing may be performed in such a case. It is needless to say that the same processing can be performed even when an error becomes a two-bit pair error during modulation and demodulation. Further, even when the number of corrections is three or more, the processing can be performed in the same manner. [Effects of the Invention] As described above, according to the present invention, when an error correction code in symbol units is used, only a short burst error in which error positions are continuous and an error of a specific pattern (for example, 1 bit) are corrected. Thus, the original correction capability of the error correction code can be sufficiently exhibited without increasing the error correction probability.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart showing an error correction method according to the present invention, FIG. 2 is a diagram showing an error distribution when a compound error occurs, and FIG. 3 is a two-dimensional arrangement. FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is a diagram showing a syndrome operation circuit, and FIG. 6 is a diagram showing the operation of the switching circuit 18. . 11 ... syndrome operation circuit, 12 ... 1 error calculation circuit,
13 ... 2 Error calculation circuit, 14 ... Error position determination circuit, 15 ...
... Error magnitude determination circuit, 16 ... Control circuit, 17 ... Erasure flag generation circuit, 18 ... Switching circuit, 19 ... Delay circuit, 20 ... Error correction circuit.

Continuing from the front page (72) Inventor Seiichi Mita 1-280 Higashi Koigabo, Kokubunji-shi, Hitachi, Ltd. Central Research Laboratory Co., Ltd. Inventor Hiroto Yamauchi 1410 Inada, Katsuta City In-house factory, Hitachi, Ltd. (72) Inventor Norio Murata 32, Miyukicho, Kodaira-shi In-house, Koganei Factory, Hitachi Electronics Co., Ltd. No. 292, Hitachi Video Engineering Co., Ltd. (56) References JP-A-57-10557 (JP, A) JP-A-58-171146 (JP, A) JP-A-62-234426 (JP, A) 60-52964 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11B 20/18 H03M 13/00

Claims (1)

(57) [Claims] In an error correction system for adding parity having a correction capability of K symbols (K ≧ 2) to an input data sequence and correcting an error occurring in a recorded / reproduced (or transmitted) data sequence, M symbols (0 <M < K) An error correction method characterized by correcting errors according to an error position and an error pattern when it is determined that an error correction of M + 1 symbols or more and K symbols or less is possible after correcting the errors below. 2. 2. The error correction method according to claim 1, wherein when an error position is continuous, an error of M + 1 symbols or more and K symbols or less is corrected. 3. 2. An error correction method according to claim 1, wherein when an error is a specific pattern, an error of not less than M + 1 symbols and not more than K symbols is corrected. 4. 2. An error correction method according to claim 1, wherein said error correction code is an inner code having a double code configuration.