JP2874933B2 - Digital signal error correction processing device and error correction processing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial application field Conventional technology (FIG. 7) Problems to be solved by the invention (FIG. 8) Means for solving the problems (FIG. 1) Examples (i) Description of the first embodiment (FIGS. 2 to 4) (ii) Description of the second embodiment (FIGS. 5 and 6) Effects of the Invention [Overview] Digital Signal Error Processing Apparatus and The present invention relates to an error correction processing method, and particularly to a digital signal error correction processing apparatus and an error correction processing method applicable to a case where errors exceeding the error correction capability and the detection capability are mixed in multiplexed information data and the like. The purpose of the present invention is to detect an uncorrectable error and perform an accurate error correction process without making a correction or leaving it uncorrected. Parity and syndrome based on the A syndrome calculation circuit that calculates a syndrome, a calculation circuit that calculates a predetermined value based on the syndrome calculated by the syndrome calculation circuit, a parity and a syndrome calculated by the syndrome calculation circuit, and the calculation circuit An error number determination circuit that determines a number of errors included in the information data based on the calculated predetermined value and generates a correction permission signal indicating whether to permit correction of the information data,
Based on the syndrome calculated by the syndrome calculation circuit and a predetermined value calculated by the calculation circuit, an error position of the information data is calculated from an error position equation, and the number of calculated error positions is calculated. An error correction processing device having an error position detection circuit that performs a comparison between the number of errors determined by the error number determination circuit and the number of error positions of data calculated by the error position detection circuit. An error position number determination circuit, and an output circuit that performs a correction process or an interpolation process on the information data based on a correction permission signal output from the error number determination circuit and a comparison result output from the error number / error position number determination circuit. The second device is a first error correction processing device, wherein the second device has a bit number smaller than the number of bits of the standardized data sequence. When the number of pieces of information data is input, a shortening condition determination is performed to determine whether or not the error exists in the information data based on an error position of the information data calculated by the error position detection circuit. A first method of calculating parity and syndrome based on input information data; calculating a predetermined value based on the calculated syndrome; The number of errors included in the information data is determined based on the calculated parity, syndrome, and the calculated predetermined value, and a correction permission signal indicating whether correction of the information data is permitted is generated. Calculating an error location of the information data from an error location equation based on the calculated syndrome and the calculated predetermined value. Calculating the number of determined error locations, comparing the determined number of errors with the calculated number of error locations of the information data; and Performing a correction process or an interpolation process on the information data based on the signal and the comparison result. The second method is the first error correction processing method. Determining whether or not the error exists in the information data based on the position of the error in the calculated information data, when the information data having the number of bits smaller than the number of bits is input. Constitute.

[Industrial applications]

The present invention relates to an error correction processing method for a digital signal, and more particularly, to a correction processing method in a case where errors exceeding error correction capability and detection capability are mixed in multiplexed information data and the like.

2. Description of the Related Art In recent years, in the field of data communication and its processing in accordance with the increase in density and functionality of information networks, MUSE for compressing and transmitting multiplexed information data, for example, HDTV signals to a baseband bandwidth of about 8 [MHZ]. (Multipule su
2. Description of the Related Art A technology for transmitting a digital signal in which an error correction code is added to audio data or the like in a bnyquist sampling (sampling encoding) system or reproducing the digital signal is used.

According to this, a burst error or the like in which errors are locally concentrated in information data may occur during transmission of a digital signal or in a recording medium for some reason. As a result, the digital signal may include an error that is higher than the correction capability of the error correction processing circuit. In such a case, the correction processing circuit may erroneously correct the information data or leave it uncorrected.

Therefore, there is a demand for an error correction processing method capable of performing accurate error correction processing even when errors exceeding the error correction capability and the detection capability are mixed in the information data.

[Conventional technology]

7 and 8 are explanatory diagrams of a digital signal error correction processing method according to a conventional example.

FIG. 7 is a block diagram illustrating an example of an MUSE-type audio signal error correction processing method.

In the figure, an apparatus for decoding a MUSE type audio signal (hereinafter referred to as a MUSE signal) DIN includes a frame deinterleave processing circuit 1, a bit deinterleave processing circuit 2,
Error correction processing circuit 3, Word deinterleave processing circuit 4
And an interpolation processing circuit 5.

The error correction processing circuit 3 includes syndrome calculation circuits 3a and 82
It comprises a bit shift register 3b, another calculation circuit 3c, an error number determination circuit 3d, an error position detection circuit 3e, an AND circuit 3f, and an adder 3g.

The function of the device is to input the word, bit and frame interleaved MUSE signal DIN,
Perform frame and bit deinterleave processing. Next, error correction processing of the MUSE signal DIN that has been subjected to the bit deinterleaving processing is performed. After that, the corrected MUSE signal DIN is subjected to word deinterleave processing and interpolation processing, and is output to the audio reproduction circuit.

FIG. 8 is a flowchart of an error correction processing method according to a conventional example.

In the figure, first, the syndrome of the MUSE signal DIN that has been bit deinterleaved in step P1 is calculated. At this time, the MUSE signal DIN in the enhanced mode (82, 67) to which the 15-bit error correction code is added is input to the 82-bit shift register 3b and the syndrome calculation circuit 3a.

Next, in step P2, the number of errors is obtained by an error number discriminant. At this time, in the enhanced mode based on the syndrome calculation circuit, the error number discriminating circuit 3d determines that no correction is permitted if there is no error or if there is a 3-bit error. If there is an error of 1 or 2 bits, the permission of correction is identified.

Next, in step P3, the number of error positions is obtained in parallel by an error position equation, and the bits at the error positions are inverted. At this time, the characteristic value indicating the error position is substituted into the error position equation for the number of bits (one round) of the data string of the MUSE signal. In the error correction process, the solution of the error location equation is found,
In addition, each time the identification of the correction permission in step P2 is activated, the bit at the error position is inverted.

As a result, errors within the correction capability of the error correction processing circuit 3 can be corrected.

[Problems to be solved by the invention]

By the way, according to the conventional example, the MUSE signal in which a burst error or the like occurs for some reason may include an error that is higher than the correction capability of the error correction processing circuit 3. However, the error correction processing circuit 3 always performs the correction processing on the assumption that there is an error within the correction capability range.

 Therefore, the following problem may occur.

There is a case where a bit at a correct position is erroneously corrected without correcting a bit at a wrong position.

This is because the characteristic value indicating the error position is substituted into the error position equation by the number of bits (one cycle) of the data sequence of the MUSE signal when the number of error positions is obtained in step P3 in FIG. That is, every time a solution to the error position equation is found, an error correction process is performed. This allows the step
The number of errors determined in P1 is different from the number of error positions found in one cycle of the MUSE signal data string in step P3, and the correct error bit is incorrectly corrected without correcting the true error bit. It is.

Even if the error number discrimination result indicating that there are two errors in the bits of the data string is obtained in step P2, the error position may not be actually obtained, and the correction process may end.

If one of the causes is raised, the MUSE signal is shortened to 82 bits from the standardized data string = 127 bits by the error correction method using the BCH code. For this reason,
If an error equal to or greater than the correction capability is added to these 82 bits,
This is because a result may be obtained that an apparently shortened portion has an error, and a processing result that does not match the error number determination result within the original 83 bits of data is obtained.

As a result, data that actually required error correction processing is interpolated based on the data on which the error correction processing of the MUSE signal has been performed. As a result, when the audio data is reproduced, noise and the like are mixed and the sound quality is reduced. There is a problem of lowering.

The present invention has been made in view of the problems of the related art described above, and the information data is erroneously corrected, or uncorrectable errors are mixed without leaving the information data uncorrected. It is an object of the present invention to provide a digital signal error correction processing method capable of detecting an error and performing an accurate error correction processing.

[Means for solving the problem]

FIGS. 1 (a) and 1 (b) show a principle diagram of a digital signal error correction processing method according to the present invention.

The first method is an error correction process of a digital signal DS in which an error correction code EB is added to information data DA. First, in step P1, an error detection calculation process of the digital signal DS is performed. At P2 and P3, a determination process of the number of errors NE and a detection process of the number of error positions NA are performed based on the calculation processing result, and then at step P4, the number of errors NE and the number of error positions are calculated.
Performing a comparison process with the NA, and further performing an error correction process of the error position n of the information data DA based on the comparison process result in step P5, or of the information data DA based on the comparison process result in step P6. The second method is characterized in that interpolation processing is performed without performing error correction processing. The second method is the error correction processing method of the first digital signal, wherein the data stream DP of the digital signal DS in which the information data DA is standardized. When the length is further shortened, the error correction processing of the information data DA is performed based on the shortening condition of the digital signal DS and the detection processing result of the error position n, thereby achieving the above object.

[Action]

According to the first apparatus of the present invention, the error number / error position number determination circuit compares the number of errors (the number of errors) NE with the number of error positions (the number of error positions) NA, and outputs the information to the output circuit. The data DA is corrected or interpolated.

The number of errors NE is the number of errors in the information data DA determined by the error number determination circuit (determined by the coefficient and parity of each term of the error position equation), and the number of error positions NA
Is the number of solutions of the error location equation calculated by the error location detection circuit.

According to the first method of the present invention, the error correction processing of the error position n of the information data DA or the comparison processing result in step P6 is performed based on the comparison processing result between the number of errors NE and the number of error positions NA in step P5. , The interpolation processing is performed without performing the error correction processing of the information data DA.

For example, when the number of errors NE matches the number of error positions NA, it is determined that a correctable error is mixed in the information data DA. When the number of errors NE and the number of error positions NA do not match, it is determined that an uncorrectable error is mixed in the information data DA.

Then, when it is recognized that an error within the correction capability range has occurred, error correction processing of the information data DA is performed. When it is recognized that an error exceeding the correction capability range has occurred, the process proceeds to the interpolation process without performing the error correction process on the information data DA. Due to this, the digital signal DS that has caused a burst error etc. for some reason,
Even when an error exceeding the correction capability range is included, erroneous correction processing of erroneously correcting a bit at a correct position as in the conventional example can be reduced as much as possible.

As a result, the information data having an error exceeding the correction capability range is subjected to the interpolation processing based on the data that has not been subjected to the erroneous correction processing. As a result, the information data can be faithfully reproduced.

According to the second apparatus of the present invention, in the shortening condition determination circuit, when the information data DA having a smaller number of bits than the standardized data DP is input, an error exists in the information data DA. It is determined whether or not to perform.

Further, according to the second method of the present invention, when the information data DA is shortened from the data stream DP of the standardized digital signal DS, the conditions for shortening the digital signal DS and the detection processing result of the error position n , The data DA is subjected to error correction processing.

For example, when the data stream DP of the digital signal DS is standardized to M bits, a case is considered in which an m-bit digital signal DS smaller than M bits is input, as shown in FIG. Error is M-m from 0 bit of data string
If found in a bit, the input information data
Since an error has been found in a portion where no DA exists, it is determined that an uncorrectable error has been mixed in the information data DA. If an error is found within M bits from Mm bits of the data string, the input information data DA
An error has been found in the portion where is present, and it is determined that a correctable error has been mixed in the information data DA.

As in the first device and the first method, when an error within the correction processing capability has occurred, the error correction of the information data DA is performed. When an uncorrectable error is mixed, the process proceeds to the interpolation process without performing the error correction process on the information data DA. As a result, even if the digital signal DS in which a burst error or the like has occurred as in the first method contains an error exceeding the correction capability range, the error correction processing as in the conventional example is reduced as much as possible. It becomes possible.

As a result, the information data having an error exceeding the correction capability range is subjected to the interpolation processing based on the data which has not been subjected to the erroneous correction processing. As a result, the information data can be faithfully reproduced.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

2 to 5 are diagrams for explaining a digital signal error correction processing method according to the embodiment of the present invention.

(I) Description of First Embodiment FIG. 2 is a block diagram illustrating an error correction processing method for a MUSE signal according to a first embodiment of the present invention.

In the figure, reference numeral 11 denotes an 82-bit shift register, which is input data (MUSE signal) that has been subjected to bit deinterleaving processing.
D1 is input to shift up one bit at a time. The audio data of the MUSE signal will be described with reference to the data format of FIG.

12 is a syndrome calculation circuit, and a parity calculation circuit 12
a, the syndrome S1 calculation circuit 12b and the syndrome S3 calculation circuit 12c.

The parity calculation circuit 12a generates a generator polynomial G (x) = (x + 1) relating to a correction algorithm for the input data DIN.
(X ⁷ + x ³ +1) (x ⁷ + x ³ + x ² + x + 1)
The parity p is calculated from 1).

The syndrome S1 calculation circuit 12b calculates the second term (x ⁷ + x ³ +
The syndrome S1 (the coefficient a of the first order term of the error location equation) is calculated from 1). S3 calculation circuit 12c is configured to calculate the third term ^{(x 7 + x 3 + x} 2 + x + 1) from the syndrome S3.

13 is another calculating circuit, to calculate a calculated value S1 ² from the syndrome S1 = a S1 ² calculation circuit 13a, the syndrome S1
= S3 / S1 calculation circuit 13b and S for calculating operation value S3 / S1 from a
Consisting of a ² S3 / S1 and the adder 13c outputs the addition to addition value b (the coefficient of the second order term of the error position equation) a.

14 is an error number determination circuit, which inputs parity p, syndromes S1 and S3, and output result data of the adder 13c,
Correction permission data D1 indicating whether or not data correction is permitted
And the number NE of errors included in the input data. Table 1 shows criteria for permitting the error number determination circuit 14 to correct input data.

 Hereinafter, the reference contents of Table 1 will be described.

As described above, the error equation F (x) = bX ² + aX + 1
An added value of the second order term coefficient b is S1 ² and S3 / S1, the coefficient of the first order term a is S1. Therefore, when S1 and S3 are 0, the coefficient of the second-order term and the coefficient of the first-order term of the error equation F (x) are both 0, and the error equation F (x) has no solution. Will be. Therefore, if S1 and S3 are 0, there is no error in the data, so no correction is necessary,
The error number determination circuit 14 issues a signal indicating that the correction is not permitted.

Then, S1 and S3 instead 0, S1 when ² is equal and S3 / S1, S1 ² and S3 / S1 second order term coefficient b is 0 next to the addition value in the form of the error equation F (x) of The error equation F (x) becomes a linear equation and has only one solution. Therefore, in this case, there is one error in the data, which requires correction, and the error number determination circuit 14 issues a correction permission signal.

When S1 and S3 are not 0 and S1 ² is different from S3 / S1 and the parity is 0, the error equation F (x) becomes a quadratic equation and has two solutions. Therefore, there are two errors in the data, which need to be corrected, and the error number determination circuit 14 issues a correction permission signal.

When S1 and S3 are not 0 and S1 ² is different from S3 / S1 and the parity is 1, the error equation F (x) is an equation having an order larger than the second order. Therefore, a solution cannot be found by the error equation F (x) which is a quadratic equation. That is, the position of the data error cannot be found. In this case, since the correction is impossible, the error number determination circuit 14 outputs a signal indicating that the correction is not permitted.

Reference numeral 15 denotes an error position detection circuit which inputs the syndrome S1 = a and the output result data of the adder 13c and outputs an error position n, correction execution data D2, and the number of error positions NA. The detection circuit calculates an error position equation F (x) = bX ² + aX
The calculation value X = α, α ² , α ³ ,... Indicating the error position is sequentially assigned to +1. Thereby, the solution when the equation becomes F (x) = 0 is detected as the error position n of the data string. Further, the number of solutions of the equation is detected as the number of error positions NA of the data string.

Up to now, this is the same as the conventional example, but in the first embodiment of the present invention, an error number / error position number determination circuit 16 is provided.

The error number / error position number determination circuit 16 receives the error number NE and the error position number NA and outputs comparison result data D3. The comparison result data D3 indicates that, when NE 範 囲 NA, an error exceeding the correction capability range of the error correction processing circuit is mixed, and when NE = NA, the error correction processing circuit corrects the error. The content is that errors within the capability range are mixed.

Reference numeral 17 denotes a three-input logical output circuit that performs a three-input AND operation on each of the data D1 to D3 and outputs correction processing data D5.

An adder 18 inverts the bit at the error position of the input data DIN sequentially shifted up based on the correction processing data D5, and outputs the output data DOT.

FIGS. 3A and 3B show an MU according to each embodiment of the present invention.
FIG. 4 is a data format diagram of an SE signal.

FIG. 3A shows an MU in a 4-channel mode (A mode).
This is the audio data format of the SE signal. In the figure,
The audio data of the MUSE signal consists of 16 bits of frame synchronization signal
It consists of a control code of 22 bits, audio compression difference data of 16 × 67 bits, and a correction code of 16 × 15 bits, of which 1350 bits of data are transmitted as one frame. This data has been subjected to word, bit, and frame interleaving in order to efficiently correct errors during transmission.

For example, the writing process is sequentially performed in the horizontal direction, and the data transmission process is sequentially performed in the frame direction. Further, according to the transmission standard of the MUSE signal, a write data string (127, 11
2) (82,67) BCH is allowed for BCH. In this case, a correction code is added to the last 15 bits of the 82 bits in the horizontal data string.

FIG. 2B shows an MU in a two-channel mode (B mode).
This is the audio data format of the SE signal.

The error correction / detection capability of the A and B modes is such that 1-bit error correction (SEC) and 2-bit error detection (DED) are possible in the normal mode, 2-bit error correction (DEC), 3 Bit error detection (TED) is possible.

FIG. 4 is a flow chart of a method for erroneously correcting a MUSE signal according to the first embodiment of the present invention.

In the figure, when performing error correction processing of a MUSE signal (see FIG. 3) in the enhanced mode in which a 15-bit error correction code is added to audio data d1 to d32, first, in step P1, calculation of a syndrome of input data DIN Do the processing. At this time, the 82-bit shift register 11 and the syndrome calculation circuit
12 and the input data (MUSE signal) DIN that has been subjected to the bit deinterleaving processing is input.

In the parity calculation circuit 12a, the generator polynomial G (x) = (x + 1) relating to the algorithm for correcting the input data DIN
(X ⁷ + x ³ +1) (x ⁷ + x ³ + x ² + x + 1)
Parity p is calculated from 1). In the syndrome S1 calculation circuit 12b, the syndrome S from the second term (x ⁷ + x ³ +1)
1 = a is calculated. In the S3 calculation circuit 12c, the third term (x ⁷ +
^{x 3 + x 2 + x +} 1) from the syndrome S3 is calculated.

In other computational circuit 13, the arithmetic value S1 ² is calculated from the syndrome S1 = a calculated value from the syndrome S1 = a S3 /
S1 is calculated. The addition value b is output and operation value S1 ² and S3 / S1 is added.

Next, in step P2, a determination process of the number of errors NE is performed based on the calculation result of the syndrome. At this time, in the error number determination circuit 14, the parity p, the syndrome S1 = a, and the output result data of the adder 13c are input and the correction permission data D
1 and the number of errors NE are output. The discriminating ability is capable of 2-bit error correction and 3-bit error detection in the enhanced mode.

Next, in step P3, detection processing of the number of error positions NA of the input data DIN is performed. At this time, the error position detection circuit
At 15, the syndrome S1 = a and the processing result data of the adder 13c are input, and the error position n, the correction execution data D2, and the number of error positions NA are output. Further, in this circuit, the calculated values X = α, α ² , α ³ ,... Indicating the error positions are sequentially substituted into the error position equation F (x) = bX ² + aX + 1. Thus, a solution when the equation F (x) = 0 is detected as an error position n of the data string. Further, the number of solutions of the equation is detected as the number of error positions NA of the data string.

Next, in step P4, the number of errors NE of the input data DIN is compared with the number of error positions NA. At this time, the error number / error position number determination circuit 16 receives the error number NE and the error position number NA and outputs the comparison result data D3. Note that, in the case of NE ≠ NA, the comparison result data D3 has a content that an error exceeding the correction capability range of the error correction processing circuit is mixed. Further, when NE = NA, the content is such that an error within the correction capability range of the error correction processing circuit is mixed.

Further, if the comparison result NE = NA in step P5, an error correction process for the error position n of the input data DIN is performed. At this time, in the three-input logic output circuit 17, each data D1
~ D3 three-input AND logical operation processing is performed and correction processing data D
5 is output. The adder 18 inverts the bit at the error position of the input data DIN which is sequentially shifted up based on the correction processing data D5, and outputs the output data DOT.
Is output.

Alternatively, if the comparison processing result is NE ≠ NA in step P6, the processing shifts to the interpolation processing without performing the error correction processing of the error position n of the input data DIN.

Thus, according to the first error correction method of the present invention, the error correction processing of the error position n of the input data DIN or the step At P6, interpolation processing is performed without performing error correction processing on the input data DIN based on the comparison processing result.

For this reason, a burst error occurred for some reason.
Even when the MUSE signal contains an error exceeding the correction capability range, it is possible to minimize erroneous correction processing for erroneously correcting a bit at a correct position as in the conventional example.

As a result, the input data DIN having an error exceeding the correction capability range is subjected to the interpolation processing based on the correct data that has not been subjected to the erroneous correction processing. As a result, the audio data can be reproduced faithfully.

(Ii) Description of Second Embodiment FIG. 5 is a block diagram illustrating a method of erroneously correcting a MUSE signal according to a second embodiment of the present invention.

In the figure, the difference from the first embodiment is that in the second embodiment, a shortening condition determination circuit is provided at the output stage of the error position detection circuit 15.
19 are provided.

That is, the shortening condition determination circuit 19 determines whether or not the error position n occurs in 46 bits or more, and outputs the determination result data D4.

This is as shown in the data format of FIG.
When 82-bit data is permitted in the data string standardized to 7 bits, there is a state of “0” where there is no data in 1 to 45 bits, so that 45 bits and 46 bits of the data string are used as the boundary reference. This is to determine an error position.

Reference numeral 20 denotes a four-input logic output circuit, each data D1 to
It performs a four-input AND logical operation on D3 and outputs correction processing data D6. The other components having the same names and the same reference numerals have the same functions, and the description is omitted.

FIG. 6 is a flowchart illustrating an error correction processing method for a MUSE signal according to the second embodiment of the present invention.

In the figure, the difference from the first embodiment is that in the correction processing flow according to the second embodiment, the input data D
The error position n of IN is determined by adding a shortening condition.

That is, when the process proceeds to step P4 via steps P1 to P3 of the second embodiment, similarly to steps P1 to P3 of the first embodiment, the error position n of the input data DIN is determined at step P4.
, The number of errors NE is compared with the number of error positions NA by introducing a shortening condition n ≧ 46.

At this time, a data sequence DP in which the MUSE signal is standardized is 127.
When the data string that can be transmitted per bit is shortened to 82 bits, 4 of the standardized data string DP (127 bits)
When an error position n is found in a portion of 5 bits or less, it is determined that an uncorrectable error has been mixed in the input data DIN (see FIG. 1A). When an error position n is found in the shortened data string (82 bits), it is determined that a correctable error is mixed in the input data DIN.

Next, in step P5, if the shortening condition n ≧ 46 and the comparison result NE = NA, the error correction processing of the error position n of the input data DIN is performed.

Alternatively, in step P6, if the shortening condition n ≦ 45 or the comparison result is NE6NA, the process shifts to the interpolation process without correcting the error position n of the input data DIN.

Thus, according to the second error correction processing method of the present invention, when the input data DIN is shortened from the data string 127 bits of the standardized MUSE signal, the shortening condition n ≧ 4
6 and the data DI based on the detection processing result of the error position n.
N is subjected to error correction processing.

Therefore, as in the first method, when an error within the correction capability range occurs, the input data DIN error correction processing is performed. When an error exceeding the correction capability range has occurred, the process shifts to the interpolation process without performing the error correction process on the input data DIN. As a result, even if the MUSE signal having a burst error or the like contains an error exceeding the correction capability range as in the first method, the error correction processing as in the conventional example is reduced as much as possible. Becomes possible.

As a result, the input data DIN having an error exceeding the correction capability range is subjected to the interpolation processing based on the data that has not been subjected to the erroneous correction processing, so that the information data can be faithfully reproduced.

Table 2 compares the error correction processing methods of the conventional example and the first and second embodiments based on the experimental results of the present inventors.

The experimental conditions were the MUSE audio data format, the audio mode was A mode, the correction code was in enhanced mode, the basic data was silence, the number of data was 5000 frames, and error bits were inserted in the conventional example and the error correction of each embodiment. It is a comparison of processing methods.

According to this, the number of erroneous corrections can be halved in the first and second embodiments as compared with the conventional example.

In the embodiment of the present invention, the case of the MUSE signal has been described. However, a similar effect can be obtained in a communication system in which information data is multiplexed, for example, an error correction process of packet communication data to which an error bit is added.

〔The invention's effect〕

As described above, according to the present invention, the error correction processing of the error position of the input data or the interpolation processing is performed without performing the error correction processing based on the comparison processing result between the number of errors and the number of error positions.

Therefore, even if the information data that has caused a burst error or the like for some reason contains an error that exceeds the correction capability range, erroneous correction processing that erroneously corrects the bit at the correct position as in the conventional example is minimized. It becomes possible to reduce.

Further, according to the present invention, when data is shortened from a standardized information data string, error correction processing of the data can be performed based on the conditions for the shortening and the result of the processing of detecting the error position n.

As a result, the information data can be faithfully reproduced, and this greatly contributes to the improvement of the reliability of the digital signal processing device.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a digital signal error correction processing method according to the present invention. FIG. 2 is a block diagram illustrating a MUSE signal error correction processing method according to a first embodiment of the present invention. FIG. 4 is a diagram illustrating a data format of a MUSE signal according to each embodiment of the present invention. FIG. 4 is a flowchart of an error correction processing method according to the first embodiment of the present invention. FIG. 6 is a block diagram illustrating an MUSE signal error correction processing method according to an embodiment of the present invention. FIG. 6 is a flowchart of an error correction processing method according to a second embodiment of the present invention. FIG. FIG. 8 is a block diagram for explaining a signal error correction processing method. FIG. 8 is a flowchart of a conventional error correction processing method. (Explanation of codes) DS: Digital signal, NE: Number of errors, NA: Number of error positions, DA: Information data, DP: Standardized data sequence, EB: Error correction code, n: Error location.

Continuation of the front page (56) References JP-A-62-254540 (JP, A) JP-A-63-78633 (JP, A) JP-A-61-216042 (JP, A) JP-A-64-22116 (JP) JP-A-63-234425 (JP, A) JP-A-62-203015 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 1/00 H03M 13/00

Claims (4)

(57) [Claims] A bit shift register (11), a syndrome calculation circuit (12) for calculating a parity and a syndrome based on input information data (DA), and a syndrome calculation circuit (12) for calculating the parity and the syndrome. A calculation circuit (13) for calculating a predetermined value based on the syndrome; a parity and syndrome calculated by the syndrome calculation circuit (12); and a predetermined value calculated by the calculation circuit (13). The information data (DA)
Number of errors (NE) included in the information data (DA) and a correction permission signal indicating whether or not the correction of the information data (DA) is permitted; and a syndrome calculation circuit (12). ) And the predetermined value calculated by the calculation circuit (13) based on the error location equation to calculate the error location of the information data (DA) and the calculated error location. An error position detection circuit (15) for calculating a number (NA), wherein the number of errors (NE) determined by the error number determination circuit (14) and the error position detection circuit (15) Number of errors to compare with the number of error locations (NA) of the data calculated by
An error position number judging circuit (16); and a correction permission signal output by the error number judging circuit (14) and a comparison result output by the error number / error position number judging circuit (16). And an output circuit (20) for performing a correction process or an interpolation process of DA). 2. When information data (DA) having a smaller number of bits than a standardized data string (DP) is input, the information data (15) calculated by the error position detection circuit (15) is input. 2. The digital device according to claim 1, further comprising a shortening condition determining circuit (19) for determining whether or not the error exists in the information data (DA) based on a position of the error in the DA). Signal error correction processor. 3. A step of calculating parity and syndrome based on the input information data (DA); a step of calculating a predetermined value based on the calculated syndrome; The number of errors (NE) contained in the information data (DA) is determined based on the syndrome and the calculated predetermined value, and the information data (D
Generating a correction permission signal indicating whether or not to permit the correction of A); and calculating the information data (DA) from an error position equation based on the calculated syndrome and the calculated predetermined value.
Calculating the number of error locations (NA) and calculating the number of calculated error locations (NA) in the error correction processing method. The number of determined errors (NE) and the calculated information data Comparing the information data (DA) based on the correction permission signal and the comparison result, and performing a correction process or an interpolation process on the information data (DA) based on the correction enable signal and the comparison result. Error correction processing method for digital signals. 4. When information data (DA) having a smaller number of bits than a standardized data string (DP) is input, the information data (DA) is calculated based on an error position of the calculated information data (DA). 4. The digital signal error correction method according to claim 3, further comprising the step of determining whether the error exists in the information data (DA).