JP3271208B2 - Error correction decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoding device for performing error correction on encoded data.

[0002]

2. Description of the Related Art In a device or a transmission apparatus for recording and reproducing digital signals, encoding is performed when data is recorded or transmitted, and an error is generated when reproducing the encoded data. Correction methods are widely used.

FIG. 11 shows a schematic configuration of a decoding device for decoding encoded video data. In FIG. 11, a product code of the inner code and the outer code is formed, and an error flag is set for data that cannot be corrected by the outer code and error interpolation is performed, so that errors in the output data are inconspicuous. Like that.

[0004] The received RF data is transmitted to the synchronization signal detector 3.
1, after detecting the synchronization signal, the inner code error correction unit 32 corrects the error of the data of the inner code sequence in the data block by the inner code, and the number of errors is such that the inner code can correct the error. If it is larger than this, an error flag is set.

[0005] Next, the identification data restoration unit 33 performs restoration so that the values of the identification data indicating the order of the inner codes are continuous.
The data sequence converter 34 rearranges the data arranged in the inner code sequence into an outer code sequence for error correction using an outer code, stores the data in a memory, and outputs the data. If the identification data that does not exist in the format of the data is detected during the rearrangement of the data, the data is not stored in the memory. That is, since the data in the memory is not updated, when error correction using an outer code is performed, data previously stored exists in the data block.

The outer code error correction unit 35 detects the number of error flags in the rearranged outer code sequence data block. Here, assuming that the outer code is P,
Erasure correction for restoring lost data in the data of the outer code sequence for which the error flag has been set has the ability P to correct a maximum of P errors. Further, in the case of normal correction without using an error flag, it has the ability Q to correct a maximum of Q (= P / 2) errors.

When the number of error flags is equal to or less than P at the time of error correction by the outer code, erasure correction is performed and the error flag is set to 0. If there are P or more error flags, normal correction is performed. Also,
At the time of error correction by the outer code, if the number of errors included in the outer code is equal to or less than the error correction capability Q of the normal correction, error correction is performed, and the input error flag is set to 0.
To If the error correction capability Q is exceeded, it is determined that error correction is impossible, and the error flag is set to 1.

FIG. 12 shows an error correction method using an outer code of a data block of an outer code sequence and input data. The data block of the outer code sequence for performing the error correction by the outer code shown in FIG. 12A includes an identification data ID, data DA having the error corrected by the inner code, an inner code IP,
It consists of an outer code OP, and no error flag is set. When error correction by an outer code is performed on this data block, as shown in FIG. 12B, vertical data is sequentially input from the data string of the identification data ID indicated by the ECC block start point at the upper left of the data block. After all the data strings of the identification data ID are input, the data strings of the data DA on the right are sequentially input.

The data after the error correction by the outer code is rearranged again by the data sequence converter 36 into the data of the inner code sequence, and sent to the video signal processor 37 to decompose the data block. The decomposed data is subjected to error interpolation for correcting the error data using the preceding and succeeding data in the error interpolation processing unit 38, and then the decoded video data is output.

As the error correction code, a Reed-Solomon code is often used. In this Reed-Solomon code, the original polynomial is called a primitive polynomial. For example, the primitive polynomial F (X) is represented by the following equation (1).

[0011]

(Equation 1)

In the primitive polynomial shown in Equation 1, 2 ⁸ (=
256) Since there are kinds of elements, the Galois field, which is a set of a finite number of elements, is denoted as GF (2 ⁸ ), and if the primitive element is α, the 256 elements are represented by the following equations 2 and 3 It is represented by

[0013]

(Equation 2)

[0014]

(Equation 3)

The product of the Galois fields is a sum of exponents, and the sum of the Galois fields is an exclusive OR of bits.

Here, data is represented by d ₀ , d ₁ , d _2.
d _m−1 , an error correction code, so-called parity, is c ₀ ,
expressed in _{c 1, c 2 ··· c p} -1, when the data length m, the parity length p, the code length n (= m + p, where n ≦ 256) and data sequence D (X) is less Is shown by Equation 4

[0017]

(Equation 4)

Here, the data d and the error correction code c
Is an element of GF (2 ⁸ ).

When the data is divided and the remainder is used as the error correction code, the generator polynomial G (X) having the same order as the number of the error correction codes for dividing the data is represented by the following equation. It is expressed by Equation 5.

[0020]

(Equation 5)

Here, the error correction code is represented by Equation (6).

[0022]

(Equation 6)

Further, since the transmission data must be divisible by the generator polynomial G (X) shown in the above equation 5, the transmission polynomial V (X) for obtaining the transmission data is represented by a data string D
From the value obtained by shifting (X) by P digits, the error correction code C
It is expressed by Equation 7 having a value obtained by subtracting (X).

[0024]

(Equation 7)

Therefore, the respective original values are the values shown in Expression 8.

[0026]

(Equation 8)

Therefore, the above equation (7) can be transformed into the following equation (9).

[0028]

(Equation 9)

Next, when transmitting the transmission data represented by the above equation 9, an error signal is added.
(X) can be represented by Expression 10 obtained by adding an error polynomial E (X) representing an error to V (X) representing transmission data.

[0030]

(Equation 10)

Here, each element in the above equation (10) is represented by the value shown in equation (11).

[0032]

[Equation 11]

If the magnitude of the error that occurs during transmission is e, Equation 10 can be transformed into Equation 12.

[0034]

(Equation 12)

Therefore, the syndrome, which is an operation for calculating whether each element is correct or not, can be expressed by equation (13).

[0036]

(Equation 13)

By summing as shown in Equation 14,

[0038]

[Equation 14]

The error in the data represented by j is
Can be obtained by using

[0040]

(Equation 15)

In the above equation (15), e ^k (where k =
0, 1, 2, ..., n-1) represents the magnitude of the error of the k-th data.

If no error is included in the received data, the syndrome S becomes 0.

[0043]

By the way, the RF data as the received data may have a problem such as a defect due to dust or the like of a reproducing head, a so-called head clog, or a drop-out in which a part of data being transmitted is lost due to a missing part. Due to a failure in the data transmission system, the received signal level may be extremely low, and may be lower than the threshold level of the comparator that determines whether the received data is 0 or 1.

FIG. 13A shows a state of a normal reception signal by ternary detection, and FIG. 13B shows a state where the reception signal level is lowered. When normal RF data having a threshold level or more as shown in (a) of FIG. 13A is input, the input data is subjected to automatic gain control (Auto Gain Control) so that the output level becomes constant. An output from the comparator shown in FIG. 13B (b) can be obtained. However, as shown in FIG. 13B (a), when the received signal level is lower than the automatic gain control capability, the output from the comparator is lost as shown in FIG. 13B (b). Therefore, the received data becomes 0.

Similarly, FIG. 14A shows a state of a normal reception signal by binary detection, FIG. 14B shows a state where the reception signal level has decreased, and FIG. 14C shows a state where the threshold level has risen. Shown in In the case of this binary detection,
A signal having the threshold level shown in (a) of FIG. 14A and shown in (b) of FIG. 14A is output from the comparator. Further, even when the received signal level decreases as shown in (a) of FIG. 14B, the signal shown in (b) of FIG. 14B is output from the comparator. However, when the threshold level of the comparator is raised by the temperature characteristic as shown in (a) of FIG. 14C, the output from the comparator disappears as shown in (b) of FIG. May occur.

In the above-described conventional error correction decoding apparatus, a fixed number or more of 0s continue as the RF data,
When the correction code including the data and the parity is all 0, the syndrome is 0, and the data is determined to be correct. Therefore, it is not possible to detect the error caused by the decrease in the reception signal level as described above. Therefore, since the error flag after the error correction processing by the outer code is not set, the error interpolation is not performed, which adversely affects the output data. For example, when the received data is video data, data containing many errors and data with reduced errors are mixed, and the output image becomes unsightly.

Accordingly, in view of the above situation, the present invention considers the above situation, and when error correction is performed, a predetermined number of consecutive 0's or more in the received data.
It is an object of the present invention to provide an error correction decoding device which determines whether or not the data is original data and performs error interpolation when an error occurs.

[0048]

An error correction decoding apparatus according to the present invention, when performing error correction by an inner code, detects that a given number or more of 0s are continuously present in the decoded data. When an error flag is set in the sequence and the error is corrected by the outer code, if the number of data of the outer code sequence in which the error flag is not set is equal to or less than the normal error correction capability Q of the outer code, the data in the outer code sequence Q of
The above-mentioned problem is solved by forcibly converting data of +1 or more into another value so that error correction of the data of the outer code sequence is not performed. Here, the conversion to another value includes, for example, inverting data.

In the data format, identification data (ID data) provided for each inner code sequence is set to 0.
Is not present, and when the data to be decoded is subjected to error correction using an outer code, if 0 is continuously present in the data for a certain number or more, whether the data is the original data using the identification data, or It is determined whether or not the data is in an error state. When the data having the value of 0 is determined to be in an error state, an error flag is set on the inner code sequence, and when the error is corrected by the outer code, the error flag is set. When the number of data of the outer code sequence that did not stand is equal to or less than the normal error correction capability Q of the outer code, data of Q + 1 or more in the data of the outer code sequence is forcibly converted to another value, and It is characterized in that data error correction is not performed.

[0050]

According to the present invention, when error correction is performed, an error flag is set if a predetermined number or more of continuous 0 data is not original data, and the error flag is used in error interpolation processing. Error in the inside can be reduced.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of an error correction decoding device according to the present invention.

In FIG. 1, the RF data is input to a synchronization signal detection unit 1 and after detecting a synchronization signal, an inner code error correction unit 2 corrects the data of the inner code sequence in the data block using an inner code. However, if the number of errors is larger than the number by which the inner code can correct the error, an error flag is set. In FIG. 1, it is assumed that the data corresponding to the inner code in the received RF data has a continuous value of 0 due to the head clog, dropout, or the like. Therefore, in the error correction using the inner code, since the syndrome becomes 0, it is determined that no error exists, and no error flag is set.

Next, the identification data restoration unit 3 performs restoration so that the identification data indicating the order of the inner code is continuous. Here, the format of the identification data is determined in advance so that 0 does not exist. However, when the identification data has a continuous value of 0 due to an error such as a head clog or data dropout, the value of the identification data is set to 0. Become. The data sequence converter 4 rearranges the data arranged in the inner code sequence into an outer code sequence for error correction using an outer code, stores the data in a memory, and outputs the data.

After the rearrangement of the data, if the signal detector 5 detects identification data that does not exist in the data format, that is, 0, it is determined that an error has occurred, an error flag is set, and an outer code is set. It is sent to the error correction unit 6. In this case, the data in which the error flag is set is not sent, so that the data in the memory is not updated. Therefore, the data stored before exists in the data block of the outer code sequence when performing the error correction using the outer code. When the value of the identification data is not 0, even if there is continuous data having a value of 0, since this data is original data, no error flag is set and the data is sent to the outer code error correction unit 6.

The outer code error correction section 6 detects the number of error flags in the rearranged outer code sequence data block. Here, assuming that the number of the outer codes is P, the erasure correction for restoring the lost data in the data of the outer code sequence in which the error flag is set is P at the maximum.
It has the ability P to correct errors. Further, in the case of normal correction without using an error flag, it has the ability Q to correct a maximum of Q (= P / 2) errors.

If the number of the error flags is P or less at the time of error correction by the outer code, erasure correction is performed and the error flag is set to 0. If there are P or more error flags, normal correction is performed. Also,
At the time of error correction by the outer code, if the number of errors included in the outer code is equal to or less than the error correction capability Q of the normal correction, error correction is performed, and the input error flag is set to 0.
To If the error correction capability Q is exceeded, it is determined that error correction is impossible, and the error flag is set to 1.

The data after the error correction by the outer code is rearranged again by the data sequence converter 7 into the data of the inner code sequence, sent to the video signal processor 8 and decomposed into data blocks. The decomposed data is subjected to error interpolation for correcting the error data using the preceding and succeeding data in the error interpolation processing unit 9 and then decoded video data is output.

Normally, the identification data I as shown in FIG.
When no error flag is set in the data block of the outer code sequence including D, data DA, inner code IP, and outer code OP, the outer code error correction unit 6 does not perform error correction. A data block as shown is output.

Next, a data block in which an error flag has been set in the signal detection unit 5 because there is a data string whose identification data is 0 is shown. FIG. 3A shows that there are data strings of errors of P or less in the signal, and that the signal detection unit 5 has detected 0 as a value that does not exist in the format of the data in the identification data. The column is a data block for which an error flag is set. The error is constituted by the pre-update data ED left in the memory. This data block can be subjected to erasure correction by the outer code error correction section 6, and the error is corrected to 0 as shown in FIG. 3B. FIG. 4A shows an outer code sequence data block in which P or more error data strings are present. Similar to FIG. 3A, an error flag is set in the error data string. The error is constituted by the pre-update data ED which is data left in the memory. Since this data block cannot be subjected to the erasure correction by the outer code error correction unit 6, an error flag is set in all data strings, and the error interpolation processing unit 9 performs error interpolation.

Further, consider a case where the number of error data strings in a data block is very large. As shown in FIG. 5A, the pre-update data ED whose data has not been updated because it was determined to be in an error state at the time of error correction by the inner code is the error correction capability P of the erasure correction.
In a data block in which the number of data DA whose error correction has been performed by the inner code is much smaller than the error correction capability Q of the normal correction, the data ED before update is the data corrected by the inner code. Is regarded as data that has not been updated, and error correction is performed by the outer code error correction unit 6, so that all data becomes pre-update data ED as shown in FIG. 5B. Accordingly, it is determined that the error correction by the outer code has been successful, and the error flag becomes 0, so that the error interpolation processing unit 9 does not perform the error interpolation.

A data block in which all data is the pre-update data ED as shown in FIG.
Similarly to the data block A of FIG.
Is regarded as data that has been error-corrected by the inner code and has been updated. Therefore, the outer-code error correction unit 6 performs error correction, and all data as shown in FIG. A data block in which the presence error flag is 0 is configured. This data block is not subjected to error interpolation in the error interpolation processing section 9.

Therefore, at the time of data output, the data not subjected to the error interpolation processing of the data blocks shown in FIGS. 5B and 6B and the data corrected correctly are mixed. For example, when video data is output, an unsightly image is restored.

In order to solve the above-mentioned problem, a data string in which no error flag is set is calculated. If the data string is smaller than the error correction capability Q of the normal correction, the error correction capability P of the erasure correction is calculated. In the P number of data which can be corrected by the above, the error of the number equal to or more than the number obtained by adding 1 to the number of data Q which can be corrected by the error correction capability Q of the normal correction is inverted. In this case, the reason why the data of the outer code is inverted is to preserve the original data. When the number of data in the data sequence of the outer code sequence is K, the number of error flags is En, and the number of data without an error flag is Gn, the number of data without an error flag Gn is represented by the following equation (1).
6.

[0064]

(Equation 16)

FIG. 7A shows a data block obtained by inverting data of all P data of the outer code of the data block shown in FIG. 5A. This data block is not error-corrected by the outer code error correction unit 6 and
Since the error flag is output as a data block as it is set as shown in FIG.
Is subjected to error interpolation. Also, the error block shown in FIG.
As shown in FIG. 8A, the P data of the outer code is inverted, so that the outer code error correction unit 6 does not correct the error, and the error flag remains set as shown in FIG. Is output.

Next, FIG. 9 shows a schematic configuration for performing data inversion, and FIG. 10 shows the timing of each data and signal in FIG. FIG. 10 shows signals when the data block of FIG. 5A is input and the data block of FIG. 7A is output after the data corresponding to the outer code is inverted.

The input error flag signal (c) is output as an output error flag signal (n) via the flip-flop 11 and sent to the AND gate 13 via the NOT gate 12. The signal (e) from the flip-flop 19 is obtained by combining the signal (e) with the input code timing signal (b) via the OR gate 16 and the input E.
The CC block start signal (a) is generated by sending the signal via the NOT gate 17 to the flip-flop 19 via the AND gate 18. This signal (e) is sent to the AND gate 1 via the NOT gate 20.
3 and to the AND gate 25.

The AND gate 13 takes the logical product of the output signal from the NOT gate 12 and the output signal from the NOT gate 20 to generate a signal (f). It is input to the count-up control terminal of the counter 14. The counter 14 counts the data clock only during a period in which the signal (f) is "1", thereby identifying the data block identification data I.
The number of identification data for which an error flag is set in D is counted, and the counted number is sent to the comparator 15 as a signal (g). In the comparator 15, the number of the signals (g) is equal to the number of outer codes Q (= P /
If the number is less than 2), a signal (h) is generated, and this signal (h) is sent to the AND gate 25.

The input ECC block start signal (a) is output as an output ECC block start signal (l) through the flip-flop 22 and the counter 14 counts to detect the start of the next data block. Used as a reset signal to reset the number. The code timing signal (b)
Is output as an output code timing signal (m) via the flip-flop 21 and is input to the counter 23 as a reset signal.

The counter 23 counts the number of data in the data sequence of the outer code sequence, and this count is sent to the comparator 24 as a signal (i). In the comparator 24, an error flag is set for subtracting a value obtained by subtracting the number P of data that can be corrected by the error correction capability P of the erasure correction by the outer code from the number K of data of the data sequence of the outer code sequence. Number of data M
If the count value of the signal (i) is larger than the number M of data, the signal (j) indicating the data of the outer code portion where data inversion is performed becomes “1”, and this signal (J) is sent to the AND gate 25.

The above signal (e), signal (h), signal (j)
The signal (k) generated when the input data (d) passes through the AND gate 25 indicates the data of the outer code portion in the input data (d).
x. The OR gate 26 inverts the data of the outer code part in the input data by the generation of the signal (k). The above Ex. Data including the inverted data from the OR gate 26 is output as output data (o) via the flip-flop 27.

The above embodiment is an example of the present invention.
It goes without saying that other various configurations can be adopted without departing from the gist of the present invention.

[0073]

As is apparent from the above description, in the error correction decoding apparatus according to the present invention, the identification data provided for each inner code sequence in the data format is zero.
Is not present, and when the data to be decoded is subjected to error correction using an outer code, if 0 is continuously present in the data for a certain number or more, whether the data is the original data using the identification data, or It is determined whether or not the data is in an error state. When the data having the value of 0 is determined to be in an error state, an error flag is set on the inner code sequence, and when the error is corrected by the outer code, the error flag is set. When the number of data of the outer code sequence that did not stand is equal to or less than the normal error correction capability Q of the outer code, data of Q + 1 or more in the data of the outer code sequence is forcibly converted to another value, and By not performing data error correction, error correction using an outer code can be performed more accurately when a predetermined number or more of 0 data are continuously input. Make a error flag for the data blocks that can not perform error correction by the
Since error interpolation processing can be performed, errors in output data can be further reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an error correction decoding device according to the present invention.

FIG. 2 is a diagram showing a data block before error correction by an outer code and after error correction by an outer code;

FIG. 3 is a diagram showing a second data block before error correction by an outer code and after error correction by an outer code.

FIG. 4 is a diagram showing a third data block before error correction by an outer code and after error correction by an outer code;

FIG. 5 is a diagram illustrating a fourth data block before error correction by an outer code and after error correction by an outer code;

FIG. 6 is a diagram showing a fifth data block before error correction by an outer code and after error correction by an outer code;

7 is a diagram showing a data block obtained by performing data inversion and error correction on the data block shown in FIG. 5A.

8 is a diagram showing a data block obtained by performing data inversion and error correction on the data block shown in FIG. 6A.

FIG. 9 is a diagram showing a schematic configuration for performing data inversion.

FIG. 10 is a diagram showing the timing of data and signals generated according to FIG. 9;

FIG. 11 is a schematic configuration diagram of a conventional error correction decoding device.

FIG. 12 is a diagram illustrating an error correction order of a data block and input data.

FIG. 13 is a diagram showing a state of data input and output from a comparator by ternary detection.

FIG. 14 is a diagram showing a state of data input and output from a comparator by binary detection.

[Explanation of symbols]

1 Synchronization signal detection unit 2 Inner code error correction unit 3 ········· Identification data restoration unit 4, 7 ····· Data string conversion unit 5 ··· .... Signal detection unit 6 ... Outer code error correction unit 8 ... Video signal processing unit 9 ... ····························· Error interpolation processing unit 11, 19, 21, 22, 27 ······························· NOT gate 13 , 18, 25 ... AND gate 14, 23 ... Counter 15, 24 ... Comparator 16 ... ... OR gate 26 ... Ex. OR gate

Claims (4)

(57) [Claims] An encoded data is subjected to an error correction using an inner code, and then an error correction is performed using an outer code. Further, an interpolation process is performed using an error flag set for a portion where an error has occurred due to the error correction. In an error correction decoding device that decodes data by performing, when an error is corrected by an inner code, 0
When an error is detected to be present continuously for a certain number or more, an error flag is set in the inner code sequence, and when error correction is performed by the outer code, the number of data of the outer code sequence in which the error flag is not set is increased by the outer code. When the error correction capability is equal to or less than the normal error correction capability Q, the data of Q + 1 or more in the data of the outer code sequence is forcibly converted to another value so that the error correction of the data of the outer code sequence is not performed. Error correction decoding device. 2. The error correction decoding apparatus according to claim 1, wherein data of Q + 1 or more in the data of the outer code sequence is forcibly inverted and converted to the different value. 3. In the data format, zero is not present in the identification data provided for each of the inner code sequences, and when the decoded data is subjected to error correction by an outer code, a certain number of zeros are included in the data. If they exist continuously,
Using the identification data, it is determined whether the data is original data or an error state. When the data having the value of 0 is determined to be in an error state, an error flag is set in the inner code sequence. When the number of data of the outer code sequence for which the error flag is not set when the error correction is performed by the outer code is equal to or less than the normal error correction capability Q of the outer code, data of Q + 1 or more in the data of the outer code sequence is forcibly applied. 3. The error correction decoding apparatus according to claim 1, wherein the error correction decoding apparatus converts the data into another value so as not to perform error correction on the data of the outer code sequence. 4. After performing error correction on encoded data using an inner code and then correcting an error using an outer code, an interpolation process is performed using an error flag set for a portion where an error has occurred due to the error correction. In the error correction decoding device that decodes the data by performing the process, the identification data provided for each of the inner code sequences does not have 0 in the data format, and the data to be decoded is error-corrected by the outer code. At this time, if 0s are continuously present in the data for a certain number or more, it is determined whether the data is original data or an error state by using the identification data, and the data having the value of 0 is determined. An error correction decoding apparatus characterized in that an error flag is set for an inner code sequence when it is determined that is an error state.