JP3468370B2 - Playback device - Google Patents

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of the Invention The means for solving the problems to be solved by the prior art inventions (FIGS. 1 to 3, FIG. 8 and FIG. 2)
4) Operation (FIGS. 1 to 3, 8 and 24) Embodiment (1) Overall configuration (FIG. 1) (2) Playback data processing circuit (FIG. 2) (3) Viterbi decoding circuit (FIGS. 3 to 7) (4) Arithmetic circuit (FIGS. 8 to 23) (5) Error correction block (FIG. 24) (6) Effects of the embodiment (7) Effects of the invention of other embodiments

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, and can be applied to, for example, a video tape recorder for converting a video signal into a digital signal and recording / reproducing it.

[0003]

2. Description of the Related Art Conventionally, in this type of video tape recorder, a digital video signal is recorded and reproduced by applying a class 4 partial response method, thereby effectively utilizing the frequency characteristics of an electromagnetic conversion system. There has been proposed a signal recording / reproducing device capable of efficiently recording and reproducing the signal (Japanese Patent Application No. 2-412921).

That is, in this type of video tape recorder, after the video signal is quantized and converted into serial data, the arithmetic processing of the following equation is sequentially executed.

[0005]

[Equation 1]

Here, D represents a delay operator, and MOD2 represents a remainder of 2. In this way, in the video tape recorder, it is possible to effectively use intersymbol interference and generate recorded data such that the spectrum is concentrated in the middle band. Therefore, by sequentially recording the recording data thus generated on the magnetic tape, the spectrum can be concentrated in the vicinity of the maximum CN ratio in the electromagnetic conversion system, and the frequency characteristics of the electromagnetic conversion system can be effectively used. The video signal can be recorded efficiently.

Further, in the reproducing system, after converting the reproducing signal obtained through the magnetic head into a digital signal,
A predetermined arithmetic circuit executes (1 + D) arithmetic processing. That is, since the electromagnetic conversion system has the differential characteristic, the frequency characteristic can be represented by (1-D) using the delay operator D.

Therefore, at the time of reproduction, (1+
If the calculation process of D) is executed, the transfer function of the entire reproduction system can be expressed by the following equation, and the transfer function can be set to 1 for the entire recording / reproduction system for the calculation process at the time of recording.

[0009]

[Equation 2]

As a result, in this type of video tape recorder, the result of this operation can be decoded to efficiently record and reproduce the digital video signal.

By the way, when a digital signal is recorded / reproduced by using the class 4 partial response method in this way, the transfer function can be set to 1 in the entire recording / reproducing system, whereas the recording input to the magnetic head is performed. Looking at the entire reproduction system focusing on the signal, the transfer function can be represented by (1-D ² ). As a result, if the output data is decomposed into an odd column and an even column after the operation processing of (1 + D) is performed, continuous data in the output data of the odd column and the even column are correlated with (1-D). It can be represented by a relationship.

Therefore, in the reproducing system, for example, a Viterbi decoding circuit using the Ferguson algorithm is used to decode the output data of the odd-numbered column and the output data of the even-numbered column, respectively. The decoding result can be obtained.

That is, in the Viterbi decoding circuit, a threshold value is set with reference to the likelihood data one clock cycle before, and when the input data fluctuates more than the threshold data, the likelihood data is updated. At the same time, it is determined that there is a transition in the input data. Further, in the Viterbi decoding circuit, the input data between the transition and the subsequent transition is correctly judged by utilizing the correlation of the input data.

As a result, in this type of video tape recorder, the bit error rate can be remarkably improved as compared with the case where the reproduced data is simply decoded based on a predetermined threshold value. . Therefore, in this type of video tape recorder, it is possible to reliably reproduce a high density recorded digital video signal by combining error correction processing using a parity code or the like.

[0015]

By the way, in the video tape recorder of this kind, if the error correction capability can be further improved, the recording density can be improved and the quality of the reproduced image can be improved.

The present invention has been made in consideration of the above points, and an object of the present invention is to propose a reproducing apparatus capable of further improving the error correction capability as compared with the prior art.

[0017]

In order to solve such a problem, in the first invention, a reproducing apparatus 1 to which a partial response system for reproducing sequentially input signals is applied.
, An analog digital conversion circuit 32 which converts an input signal into a digital signal at a predetermined cycle and outputs input data y _K , and predetermined thresholds Δ _K−1 +1 and Δ _K−1 −.
The + merging and −merging of the input data y _K are detected based on 1 and the detection results M + and M of the + merging and −merging are detected.
The input data y _K is decoded based on − to obtain the decoded data a _K
Outputs the detect input data _{y K} NoYudo delta _K, the threshold delta _K + 1 on the basis of the likelihood delta _K, delta _K -1
And the data CV _b and CV _f with the probability of + merging and / or −merging before and after each of the continuous decoded data, and the decoded data a _K of each decoded data a _K based on the detection result. An arithmetic circuit 48 for detecting the probability data CV is provided.

Further, in the second aspect of the invention, in the reproducing apparatus 1 to which the partial response system for reproducing sequentially input signals is applied, the input signal is converted into a digital signal at a predetermined cycle and the input data y _K is output. Analog digital conversion circuit 32 and a predetermined threshold value Δ _K-1
The + merging and −merging of the input data y _K are detected with reference to +1, Δ _K−1 −1, and the input data y _K is decoded and decoded based on the detection results M + and M− of the + merging and −merging. outputs the data a _K, detects the input data y _K NoYudo delta _K, the threshold delta based on likelihood delta _K
Viterbi decoding circuit 42 that updates _K +1 and Δ _K −1, and data CV _b and CV _f of the likelihood of + merging and / or −merging before and after each successive decoded data are detected, and based on the detection result. detecting the likelihood of data CV of each decoded data a _K Te an arithmetic circuit 48, the decoded data a _K
Of the decoded data a _K based on the data CV of the probability of
And an error correction circuit 46 for outputting and performing error correction processing.

[0019] In yet a third aspect of the invention, the error correction circuit 46 based on the data CV of probability of each decoded data a _K, detecting the most uncertain decoded data a _K for each predetermined unit of decoding data a _K , The most uncertain decoded data a _K
And the adjacent symbol generation circuits 132 and 134 for bit-inverting and outputting the adjacent symbols, and the decoded data a _K and the adjacent symbols are subjected to error correction processing, and the decoded data a _K or the adjacent symbols are selectively selected based on the error correction processing result. The error correction circuits 130, 136, 138, 140 for outputting are provided.

[0020]

[0021]

For each continuous decoded data a _K , a predetermined reference value is set based on the preceding and following + merging and / or −merging, and the input data y corresponding to each decoded data a _K is set on the basis of each reference value. By detecting the value of _K , it is possible to easily detect the probability data CV for each decoded data a _K.

Further, if the decoded data a _K is subjected to error correction processing based on the thus detected probability data CV, the error correction capability can be improved accordingly.

At this time, the most uncertain decoded data a _K is detected for each predetermined unit of the decoded data a _K based on the certainty data CV, and the most uncertain decoded data a _K is bit-inverted to generate an adjacent symbol. Then, if the decoded data a _K or the adjacent symbol is selectively output based on the error correction processing result of the adjacent symbol and the decoded data a _K , the error correction capability can be easily improved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall Configuration In FIG. 1, reference numeral 1 indicates a video tape recorder as a whole, which is converted into a digital signal by a video signal processing circuit 2 and then divided into predetermined blocks. Further, the video signal processing circuit 2 interleaves the digital video signal on a block-by-block basis, adds an error correction code by an error correction circuit (PTG) 4, and outputs it.

The audio signal processing circuit 6 converts the audio signal into a digital signal and then interleaves it in a predetermined block unit. Subcode generation circuit 8
Generates subcode data such as time code, program time, user ID and the like.

The error correction circuit (PTG) 10 adds an error correction code to the output data of the audio signal processing circuit 6 and the sub code generation circuit 8 and outputs the added data. Divide and multiplex. At this time, the error correction circuits 4 and 10 convert the output data to serial data and output the serial data, and thereby output serial data that is time-division multiplexed through the adder circuit 12.

The modulator circuit (MOD) 14 includes an adder circuit 12
For the output data of, perform the arithmetic processing of equation (1),
This converts the input data into a recording signal. The reference signal generation circuit 16 generates a reference signal such as a preamble and a postamble, and a reference signal for ATF tracking control, and outputs the reference signal to the adder circuit 18, and the reference signal is added to the recording signal output from the modulation circuit 14. Superimpose.

The equalizer circuit (EQ) 20 corrects the frequency characteristic of the output signal of the adder circuit 18 and then outputs it to the magnetic head 24 through the amplifier circuit 22, thereby sequentially outputting the digital video signal and the digital video signal to the magnetic tape 26. Record the digital audio signal.

On the other hand, in the reproducing system, the reproducing signal output from the magnetic head 24 is amplified by the amplifier circuit 28 and then output to the tracking control circuit 30. As a result, in the video tape recorder 1, the tracking control circuit 30 separates the reference signal for ATF tracking control, and the tracking control of the magnetic tape 26 is performed based on this reference signal.

Further, in the reproducing system, the output signal of the amplifier circuit 28 is given to the PLL circuit 31, and the clock signal is reproduced here. Analog digital conversion circuit (A / D) 3
2 converts the output signal of the amplifier circuit 28 into a digital signal with reference to this clock signal, thereby converting the signal level of the reproduced signal into a digital signal at the clock cycle of the reproduced signal.

The equalizer circuit (EQ) 34 corrects the frequency characteristics and the amplitude characteristics of the output data of the analog digital conversion circuit 32 and outputs it. The reproduction data processing circuit 40 uses the output data of the equalizer circuit 34 as (1-
The calculation process of D) is executed, whereby the transfer function of the entire recording / reproducing system is set to a value of 1 and the reproduced signal is decoded, and then error correction processing is performed and output. As a result, the video tape recorder 1 can convert a video signal and an audio signal into a digital signal for recording and reproduction.

(2) Reproduced Data Processing Circuit In FIG. 2, the reproduced data processing circuit 40 includes an arithmetic circuit 4
In (1), the output data of the equalizer circuit 34 is subjected to a calculation process of (1-D), then separated into an odd number column and an even number column, and decoded by the Viterbi decoding circuit 42.

The time axis correction circuit (TBC) 44 converts the decoded data of the odd and even columns output from the Viterbi decoding circuit 42 into parallel data of a predetermined bit length and outputs it. The error correction block 46 performs error correction processing on the output data of the time base correction circuit 44, and then separates and outputs the digital video signal and the digital audio signal.

At this time, the arithmetic circuit 48 detects the probability CV of each bit in the decoded data a _K output from the Viterbi decoding circuit 42, and the error correction block 46
Based on the detection result CV, a so-called soft decision method is applied to execute the error correction processing, whereby the bit error can be significantly improved as compared with the conventional case.

(3) Viterbi Decoding Circuit As shown in FIG. 3, the Viterbi decoding circuit 42 processes the input data y _K separated into odd and even columns by applying the Ferguson algorithm.

Here, in the Ferguson's algorithm, as shown in FIGS. 4 to 6, the merge of the predicted input values S _K is detected, and the final transition of the predicted input values S _K is determined based on the detection result. Then, the input data y _K is decoded by this. Therefore, in the Ferguson's algorithm, when the predicted input value S _K changes from +1 to +1 or -1, + merge, and the predicted input value S _K changes from +1 to +1.
Or, it is defined as non-merging when it continues from -1 to -1, and as-merging when the prediction input value S _K changes from -1 to +1 or -1. First, the prediction input value S is detected by detecting this merging. Detect _K transitions.

This merge detection process is defined as + merge, non-merge, and -merge, respectively, when any of the formulas (3) to (5) is established by executing the arithmetic process of the following formula.

[0039]

[Equation 3]

[Equation 4]

[Equation 5]

Here, y _K represents input data.

Further, Δ _K-1 represents the likelihood of the input data y _K-1 one clock before (that is, the certainty of the input data y _K-1 ), and + merge, non-merge, and
-At the time of merging, it is defined as in equations (6) to (8).

[0042]

[Equation 6]

[Equation 7]

[Equation 8]

As a result, in the Ferguson algorithm, when the input data y _K changes by 1 or more with respect to the data Δ _K-1 of the likelihood one clock before, the merging and the merging are performed depending on whether the change is positive or negative. Judge and input data y
_The likelihood data Δ _K is updated according to the value of _K.

On the other hand, when the change in the input data y _K is small, it is judged that the data is not merged and the data Δ _K-1 of the likelihood one clock before is held as it is.

When the merge is detected in this way, in the Ferguson algorithm, a path represented by a trellis diagram is set based on the merge detection result as shown in FIG. Once detected, the path between the-merge and the + merge between them is determined. As a result, in the Ferguson algorithm, the decoding result is output based on the path represented by the trellis diagram, and in the case of this embodiment, the modulation circuit 20 converts the recording data to N.
By performing the RZI encoding process, when the value of the predicted input value S _K changes, the decoding result of the value 1 is output, whereas when the value of the predicted input value S _K does not change, the decoding result of the value 0 is output. Output.

In the case shown in FIG. 7, it is assumed that the predicted input value S _K changes -1, +1, +1, +1 by obtaining the + merge detection result at the third clock cycle from -merge. It is possible to make a judgment, and it is possible to obtain a decoding result of values 1, 0, 0.

That is, in the Viterbi decoding circuit 42,
The input data y _K separated into the odd-numbered column and the even-numbered column is given to the addition circuit 50 and the subtraction circuit 52, and the addition / subtraction of the following equation is performed between the input data y _K and the threshold value data TH1 (in this case, the value is 1). Execute the process.

[0048]

[Equation 9]

[Equation 10]

Further, the Viterbi decoding circuit 42 latches the output data of the adder circuit 50 and the subtractor circuit 52 by the latch circuits (R) 54 and 56, and then outputs it to the subtractor circuits 62 and 64 via the latch circuits 58 and 60, respectively. To do. The subtraction circuits 62 and 64 subtract the output data of the latch circuits 58 and 60 from the probability data Δ _{K-1 of} one clock cycle before, and the data of the highest bit thereof is the positive merge detection result M +, the negative merge detection. The result is output as M-.

That is, in this embodiment, the analog digital conversion circuit 32 (FIG. 1) sequentially converts an input signal into a digital signal by using a format in which a negative value is represented by 2's complement.

On the other hand, in the calculation results M1 and M2 of the subtraction circuits 62 and 64,

[Equation 11]

[Equation 12] By applying the form that expresses a negative value in 2's complement,

[Equation 13]

[Equation 14] When the relational expression of is satisfied, the logic level of the highest bit can be switched.

That is, if the equations (13) and (14) are modified, the following equation is obtained.

[Equation 15]

[Equation 16] It is possible to obtain the relational expression of, and by this, when the relation of the expression (11) is established, the plus merge detection result M + of the value 0 can be obtained, while when the relation of the expression (12) is established, the value 1 The negative merge detection result M- of
Only the data of the highest bit can be detected to easily obtain the merge detection result.

The latch circuits 66 and 68 latch the output data of the latch circuits 54 and 56, respectively, while the selection circuit 70 switches the contacts based on the merge detection results M + and M-, and the latch circuits 66 and 68. Selectively output the output data of.

The comparison circuit (COM) 72 sends a control signal to the latch circuits 74 and 76 when the relation of the equation (13) or (14) is established based on the merge detection results M + and M-. Then, the output data of the selection circuit 70 is latched by the latch circuits 74 and 76.

As a result, the Viterbi decoding circuit 42 (13)
Or, only when the relation of formula (14) is established, the likelihood data Δ _K one clock cycle before is updated according to the relations of formulas (6) and (8). The decoding result is output.

At this time, in the Viterbi decoding circuit 42,
The adder circuit 50 and the subtractor circuit 52 previously execute the arithmetic processing of the expressions (9) and (10), and selectively select the arithmetic processing results based on the merge detection results M + and M-.
By accumulating in 6, the addition circuit 50 and the subtraction circuit 5
The likelihood data Δ _K can be detected only by selectively outputting the output data of No. 2, and the likelihood data Δ _K can be detected in a shorter period.
_K can be updated.

Further, in this way, the addition circuit 50 and the subtraction circuit 52 previously execute the arithmetic processing of the equations (9) and (10), so that the addition circuit 5 is added in the Viterbi decoding circuit 42.
0, the merge detection result M +, M- can be detected only by subtracting the output data of the subtraction circuit 52 from the likelihood data Δ _K obtained up to one clock cycle before, and the merge detection result can be detected in a shorter cycle. M + and M- can be obtained.

Further, at this time, for the input data y _K ,
By expressing the negative value in the 2's complement format, the merge detection results M + and M- can be obtained with a simple configuration in which only the most significant bit data is output and in a short cycle.
Therefore, the Viterbi decoding circuit can be configured with an arithmetic processing circuit having a low operating frequency to reliably decode the reproduced signal.

Thus, the Viterbi decoding circuit 42 gives the merge detection results M + and M- to the buffer 80 via the merge buffer 78. The controller 82 outputs a control signal to the buffer 80 based on the merge detection results M + and M-.

The buffer 80 is composed of shift register circuits connected in series and sequentially transfers the input data, and switches the polarity of the input data based on the control signal of the controller 82, and transfers the decoded data. Output the data.

Thus, in the Viterbi decoding circuit 42,
The output data of the buffer 80 is arithmetically processed by (1-D) and output, and the decoding result of the recording signal is converted into the decoding result of the reproduction signal and output. Further, in the Viterbi decoding circuit 42, when + merging or −merging is detected, the merging operation circuit 84 determines the certainty of the merging (that is, corresponds to the decoded data a _K of value 1 output from the Viterbi decoding circuit). The detection result CVM is output.

Here, in the subtraction circuits 62 and 64,
Calculation processing results M1 and M2 expressed by equations (11) and (12)
By detecting the values of the output data of the subtraction circuits 62 and 64, the input data y that sufficiently satisfies the equation (3) or (5) for the decoded data a _K can be obtained.
Or by _K, it is possible to determine (3) or (5) by the input data y _K satisfying barely equation.

In this case, the decoded data a _K obtained from the input data y _K just satisfying the equation (3) or (5).
Can be judged to be less certain. On the other hand, it can be determined that the decoded data a _K obtained from the input data y _K that sufficiently satisfies the equation (3) or (5) has a sufficiently high certainty.

That is, if the magnitudes of the values of the arithmetic processing results M1 and M2 are detected, the certainty of the decoded data a _K obtained by + merging and −merging can be detected.

Therefore, it is considered that the bit error can be improved if the error correction processing or the like is executed by effectively utilizing the operation processing results M1 and M2. Furthermore, if the probability can be expressed in this way not only for the decoded data obtained by + merging and −merging, but also for all the decoded data, it can be used more effectively for error correction processing, etc., to improve bit errors. It is thought to get.

Therefore, in this embodiment, the selection circuit 8
The probability data CV of all the decoded data is detected by the arithmetic circuit 48 on the basis of the probability data CVM output from No. 4.

By the way, in the equations (11) and (12),
By including the constant term of the value 1, the merge operation circuit 84 determines the constant 1 from the output data of the subtraction circuits 62 and 64.
After subtracting

[Equation 17] Probability data CVM represented by is output.

[0068] (4) calculating circuit operation as shown in Figure 8 circuit 48 is + merge and - probability of data CVM obtained in the merging, based on the likelihood data delta _K, the decoded data a Probability data CV for _K is detected. Therefore, the arithmetic circuit 4
Reference numeral 8 sets a predetermined reference value with reference to the certainty data CVM and the likelihood data Δ _K obtained at the time of this + merging and −merging, and the input data y _K of the input data y _K is set with this reference value as a reference. By detecting the value, the probability data CV is detected.

That is, as shown in FIG. 9, in the Viterbi decoding circuit 42, continuous input data y _K , y _{K + 1} ,
A-merge may be detected before and after the intermediate input data y _{K + 1} in y _{K + 2} (the value is indicated by the size of the arrow in this case). In this case, as shown in FIGS. 10 to 12, in the Viterbi decoding circuit, the intermediate input data y _{K + 1} is the first
When the input data y _K is within the range of thresholds Δ _K +1 to Δ _K −1 determined by the likelihood data Δ _K , the decoding result of the value 0 is obtained (FIGS. 10A and 10B). .

On the other hand, when the intermediate input data y _K rises above the positive threshold Δ _K +1 (see FIG. 11).
(A)), in the Viterbi decoding circuit, - whereas merge detection result is obtained, when falls below the threshold delta _K -1 for negative, + merge detection result is obtained (FIG. 1
2 (A)). In this case, when -merging is detected, it cannot be obtained by the class 4 partial response, and thus the Viterbi decoding circuit outputs a continuous decoding result with a value of 0 (FIG. 11 (B)).

On the other hand, in the detection results of-merge, non-merge, and-merge, the first-merge detection result is judged to be non-merge error detection, so that the Viterbi decoding circuit 42 has values 0 and 0. The decoding result can be obtained (FIG. 10 (B)). On the other hand-merge,
When + merging and −merging continue, a continuous decoding result with a value of 1 can be obtained (FIG. 12 (B)).

From this, as shown in FIG. 13, for the intermediate input data y _{K + 1} sandwiched by-merge,
Threshold value Δ determined by the likelihood Δ _{K + 2} of the input data y _{K + 2 of}
Not if rises beyond the _{K + 2} +1, located in the range of the threshold delta _{K + 2} +1 of the negative-side threshold delta _K -1 determined by the first input data y _K NoYudo delta _K It can be seen that the value 0 is decoded when On the other hand, it can be seen that when the input data y _{K + 1} falls below the negative side threshold value Δ _K −1, it is decoded into the value 1.

Therefore, the closer the input data y _{K + 1} approaches the intermediate position CVC of the threshold value Δ _{K + 2} +1 to Δ _K −1, the more likely the decoded data a _{K + 1 with the} value 0 is. Although it can be determined, the threshold value Δ away from the intermediate position CVC
_The closer to _{K + 2} +1 or Δ _K −1, the more uncertain the decoded data a _{K + 1 with} a value of 0 can be determined. Value 1 for this
When it is decoded into, it is possible to judge the uncertainty as it gets closer to the negative side threshold value Δ _K −1, whereas if it falls largely to the negative side from this threshold value Δ _K −1, it becomes more than that. You can judge that it is certain.

Here, the value α of the midpoint CVC is expressed by the following equation:

[Equation 18] The maximum value CV _max of the probability when the input data y _{K + 1} is decoded to the value 0 can be expressed by the following equation.

[Formula 19] Can be expressed as

Therefore, when the input data y _{K + 1} is decoded into the value 0, the probability data CV [data] for the decoded data with the value 0 is

[Equation 20] Can be expressed as

On the other hand, when the input data y _{K + 1} is decoded into the value 1, in this case, + in the Viterbi decoding circuit.
The merge detection result is obtained, and at the same time, the certainty data CVM expressed by the equation (17) is obtained.

[Equation 21] As shown by, the probability data CV [data] can be represented.

On the other hand, as shown in FIG. 14, when the + merging is continuous with the second input data y _{K + 1} interposed therebetween, it is similar to the case where the −merging is continuous as described above with reference to FIGS. Can be judged.

That is, in this case, as shown in FIG.
Since the merge is continuous and the reverse is the case, the intermediate input data y _{K + 1} is the third input data y.
_The threshold value ΔK _{+ 2} −1 determined by the likelihood ΔK _{+ 2} of _{K + 2} does not fall, and the threshold of the first input data y _K is calculated from this threshold ΔK _{+ 2} −1. It can be seen that when it is located in the range of the positive side threshold Δ _K +1 determined by the degree Δ _K , the value 0 is decoded.

On the other hand, it can be seen that when the input data y _{K + 1} rises above the positive threshold Δ _K +1 it is decoded into the value 1. Therefore, as shown in FIG. 16, this input data y _{K + 1} changes from the threshold values Δ _{K + 2} −1 to Δ _K +1.
The closer to the intermediate position CVC, the more likely it is to judge that the decoded data with a value of 0 is more likely, while the intermediate position CVC
The further away from the threshold Δ _{K + 2} −1 or Δ _K +1 the closer the decoded data with the value 0 can be judged to be uncertain.

Accordingly, in this case, the value α of the midpoint CVC is

[Equation 22] And the maximum likelihood value CV _max when the input data y _{K + 1} is decoded to a value 0 is

[Equation 23] Can be expressed as

As a result, when the input data y _{K + 1} is decoded into the value 0, the probability data CV [data] of the decoded data with the value 0 is

[Equation 24] Can be expressed as

On the other hand, when the input data y _{K + 1} is decoded into the value 1, in this case, the Viterbi decoding circuit outputs +
By obtaining the merge detection result,

[Equation 25] As shown by, the likelihood data CV [data] can be expressed using the updated likelihood data Δ _{K + 1} .

As a result, when the same merge continues, when the next merge is + merge, the parameter M
P is the following formula

[Equation 26] Then, when the next merge-is a merge, the parameter MP is

[Equation 27] In other words, the value α of the midpoint CVC is

[Equation 28] And the maximum likelihood value CV _max when the input data y _{K + 1} is decoded to a value 0 is

[Equation 29] Can be expressed as

Therefore, when the input data y _{K + 1} is decoded into the value 0, the probability data CV [data] of the decoded data with the value 0 is

[Equation 30] Can be expressed as

On the other hand, when the input data y _{K + 1} is decoded into the value 1, it can be expressed by the equation (21) (the equation (25)).

On the other hand, if the merging before and after is different,
As shown in FIG. 17, the case where the input data y _{K + 1} is sandwiched between the − merge and the + merge, and the opposite case is the + merge,
-In some cases, merging may be continuous. Among them, when the input data y _{K + 1} is sandwiched between the − merge and the + merge, when the input data y _{K + 1} rises beyond the positive side threshold value Δ _K +1, the − merge detection result. While the positive threshold Δ _K +1 to the negative threshold Δ _K
Detection result of Nonmaji in the range of -1, in the threshold delta _K -1 or less in the range of negative + merge detection results.

Therefore, in the Viterbi decoding circuit 42, when the input data y _{K + 1} rises above the positive side threshold Δ _K +1 as shown by the trellis diagram in FIG. 0, 1, ...] is obtained, whereas the threshold value Δ _K +1 on the positive side to the threshold value Δ _{K +} on the negative side determined by the likelihood Δ _{K + 2} of the third input data. ₂ -1
In the range of, the decoding result of the value [1, 0, ...] Is obtained, and it is understood that the input data y _{K + 1} does not fall below the negative threshold Δ _{K + 2} −1.

Therefore, as shown in FIG. 19, input data y
_{If K + 1} is decoded to the value 0, the threshold Δ _{K + 2} −1
From the intermediate value CVC of Δ _K +1 to the intermediate value CVC of the input data y _{K + 1} , the decoded data a _{K + 1} of the value 0 can be judged to be more probable. The closer to the threshold value Δ _{K + 2} −1 or Δ _K +1, the closer the decoded data a _{K + 1 with the} value 0 can be judged to be uncertain.

On the other hand, when decoded to the value 1,
The closer to the positive side threshold value Δ _K +1, the more uncertain the judgment can be made. On the other hand, if the threshold value Δ _K +1 rises to the larger positive side, it can be judged to be more certain. Therefore, in this case,

[Equation 31]

[Equation 32]

[Expression 33]

[Equation 34] As shown in, the probability data CV [data] can be expressed in the same manner as the expressions (22) to (25).

[0090] On the other hand, as shown in FIG. 20, in between the input data y _{K + 1} + merge, - if the merge consecutive input data y _{K + 1} of the positive-side threshold delta _K When rising beyond +1, the detection result of-merge is obtained, while the threshold value Δ _K +1 on the positive side to the threshold value Δ on the negative side is increased.
_{A non-} merge detection result is obtained in the range of _K −1, and a + merge detection result is obtained in the range of the negative threshold Δ _K −1 or less.

Therefore, as shown in FIG. 21, in the Viterbi decoding circuit, the input data y _{K + 1} rises above the positive side threshold Δ _K +1 as shown by the Trist diagram in the figure. but if, in the range of the third input data y _{K + 2} NoYudo delta _{K + 2} positive threshold determined by the delta _{K + 2} +1 from the negative side threshold delta _K -1, the value [ ..] are obtained, and the decoding result of the values [0, 1, ...] Is obtained in the range of the negative threshold Δ _K −1 or less.

Therefore, as shown in FIG. 22, input data y
_{If K + 1} is decoded to the value 0, the threshold Δ _{K + 2} +1
Therefore, the closer the value of the input data y _{K + 1} approaches the intermediate value CVC of Δ _K −1, the more likely the decoded data a _{K + 1 with} a value of 0 can be determined to be certain. The closer to the threshold value Δ _{K + 2} +1 or Δ _K −1, the more uncertain the decoded data a _{K + 1 with the} value 0 can be determined.

On the other hand, when decoded to the value 1,
While may determine that uncertain extent that you move closer to the threshold delta _K -1 for negative, if Sagare Standing larger negative than this threshold delta _K -1, it is determined that the probable than that amount You can Therefore, in this case,

[Equation 35]

[Equation 36]

[Equation 37]

[Equation 38] As shown in, the probability data CV [data] can be expressed in the same manner as the expressions (18) to (21).

Therefore, when different merges are consecutive, the following formula is used by using the parameter MP defined by the formulas (25) and (26).

[Formula 39] Can represent the value α of the midpoint CVC, and the input data y _{K + 1} has the value 0.
The maximum value CV _max and the probability data CV [data] when decoded into

[Formula 40]

[Formula 41] If the input data y _{K + 1} is decoded into the value 1, it can be expressed by equation (17).

From this, it is understood that the probability of the intermediate input data y _{K + 1} can be detected by the common arithmetic processing regardless of the merging before and after.

At this time, the intermediate input data y _{K + 1 is} not always required.
+ And-merge do not always occur before and after,
Since there are cases where non-merging continues, the input data for which the likelihood is to be detected is set to y _ob , and the + merge or −merge input data generated in the forward direction is set to y _f.
And input data of + merge or −merge generated in the subsequent direction is y _b, and input data y _ob has a value of 0.
And when decoded to 1,

[Equation 42]

[Equation 43]

[Equation 44]

[Equation 45] Can be expressed as

Therefore, the probabilities of the input data y _f and y _b are calculated as CV _f [merge] and CV _b [merge], respectively.
], The probability data of the input data y _ob to be detected, which is expressed by the equation (43), is referred to as CV _ob [data], and the reliability CV _f [merge] and CV _b [merge] are defined.
]]

[Equation 46]

[Equation 47]

[Equation 48] It is possible to detect the probability CV of the decoded data a _K represented by

As a result, the decoding circuit 48 uses the certainty data CVM (that is, CV _f [merge] and CV _b [merge]) and the certainty data Δ _K obtained at the time of + merging and −merging as a reference. Thus, it is possible to detect the probability data CV for the decoded data a _K between the + merge and the − merge.

Based on this detection principle, the arithmetic circuit 48
In order to detect the certainty data CV, the certainty data CVM via the buffer circuits 86, 88 and 90,
Likelihood data Δ _K and input data y _K are input, and as a result, certainty data CVM, likelihood data Δ _K ,
Decoded data a _K corresponding timing of the input data y _K
Match the timing of. Buffer circuits 92, 94,
96 delays the likelihood data Δ _K , the input data y _K , and the decoded data a _K by a predetermined period and outputs the delayed data.

When the decoded data a _K output from the buffer circuit 96 rises to the value 1, the latch circuit 96 fetches the likelihood data Δ _K output from the buffer circuit 92 and then the subsequent decoded data a _K. during the period until reaching the value 1, to hold the data delta _K of this likelihood.

The arithmetic circuit 98 subtracts the output data of the buffer circuit 94 and the latch circuit 96, and then outputs the absolute value. As a result, the arithmetic circuit 98 becomes (21), (2
5) The data CV [data] of the probability when the decoded data a _K represented by the equations (34) and (38) has the value 1 is detected.

Similarly, when the decoded data a _K rises to the value 1, the buffer circuit 100 fetches the certainty data CVM output from the buffer circuit 86 and delays the decoded data a _K by a predetermined period to obtain the decoded data a _K at the value 1. When it rises to, it outputs the captured data. The latch circuit 102 is
When the decoded data a _K rises to the value 1, the buffer circuit 1
After the probability data CVM output from 00 is fetched, the probability data CVM is held for a period until the subsequent decoded data a _K rises to the value 1.

The adder circuit 104 inputs the output data of the latch circuit 102 via the latch circuit 106, and
The output data of the buffer circuit 100 is received, and the addition data obtained as a result is output. As a result, the adder circuit 104
Is the data CV of the certainty obtained at the time of + -merging and-merging before and after being defined in the second and third terms of equation (46).
The addition result of M (that is, CV _f [merge] and CV _b [merge]) is output. The addition circuit 108 receives the addition data of the arithmetic circuit 98 via the selection circuit 110,
The addition data and the output data of the addition circuit 104 are added and output.

As a result, in the adder circuit 108, when the decoded data a _K rises to the value 1, the certainty data CV represented by the equation (46) is detected and the detection result is output. .

On the other hand, when the decoded data a _K has a value of 0, the selection circuit 110 switches the contact and thereby outputs the output data of the arithmetic circuit 112 instead of the output data of the arithmetic circuit 98 to the adder circuit 108. That is, when the decoded data a _K rises to the value 1, the buffer circuit 114 takes in the input data y _K output from the buffer circuit 90, and delays the decoded data a _K by a predetermined period to set the decoded data a _K to the value 1.
It outputs when it stands up.

When the decoded data a _K output from the buffer circuit 96 rises to the value 1, the latch circuit 116 fetches the input data y _K output from the buffer circuit 114 and then the decoded data a _K continues. This input data y _K is held until the value rises to 1. The arithmetic circuit 118 outputs the output data of the buffer circuit 114,
A latch circuit 116 input via the latch circuit 120.
Is subtracted from the output data, and the subtraction data obtained as a result is divided by 1/2 to be an absolute value and output.

As a result, the arithmetic circuit 118 corresponds to the equation (40) and the following equation

[Equation 49] The maximum value CV _max of the certainty represented by is detected.

Thus, in the arithmetic circuit 48, (40)
By detecting the certainty of the decoded data a _K using the maximum certainty value CV _max represented by the equation (49) instead of the maximum certainty value CV _max of the equation, a simpler configuration can be achieved. The probability of the decoded data a _K can be detected.

On the other hand, the arithmetic circuit 122 subtracts the output data of the buffer circuit 114 and the output data of the latch circuit 120, divides the subtracted data obtained as a result and outputs it. As a result, the arithmetic circuit 122
Corresponding to equation (39), the following equation

[Equation 50] The value α of the midpoint CVC represented by is detected.

Thus, in the arithmetic circuit 48, (49)
Corresponding to the equation, the value α of the equation (50) is used instead of the value α of the equation (39) to detect the certainty of the decoded data a _K , so that the decoding can be performed with a simpler configuration. The accuracy of the data a _K can be detected.

The arithmetic circuit 112 comprises latch circuits 124, 1
The output data of the arithmetic circuits 118 and 122 is received via 26, and thereby the arithmetic processing of the equation (41) is executed based on this output data and the output data of the buffer circuit 94. As a result, the arithmetic circuit 48 adds the output data of the adder circuit 104 and the output data of the arithmetic circuit 112 via the adder circuit 108 and outputs the result, whereby the decoded data a
_{When K} has a value of 0, the data CV having the certainty of the decoded data a _K is detected.

Thus, as shown in FIG. 23, the input data y _K has the values 1.5, −1.5, 0.3, −1.2, 0.7, 1.8, 0.
5 (FIGS. 23 (A) and (B)), the Viterbi decoding circuit 42 detects a sequential merge based on the likelihood data Δ _K , and then determines a value based on this merge detection result. The decoding result of 1, 1, 0, 0, 0, 1, 0 can be obtained. Correspondingly, the arithmetic circuit 48 detects the probability data CV _b and CV _f for the + or − merge before and after, and the probability data CV is detected.
Probability data CV can be detected for each decoded data a _K based on V _b and CV _f .

(5) Error correction block As shown in FIG. 24, the error correction block 46 performs error correction processing on the decoded data a _K with reference to the certainty data CV detected by the arithmetic circuit 48.

That is, in the error correction block 46, the error correction circuit (ECC) 130 outputs the decoded data a _K.
Is converted into parallel data having a predetermined bit length and input, and error correction processing of the decoded data a _K is executed based on the parity code added at the time of recording. At this time, the error correction circuit 130 detects the decoded data a _K that cannot be error-corrected by outputting the error correction result AOK, and outputs the detection result.

The CV detection circuit 132 adds the probability data CV in 1-byte units of the decoded data a _K , and then adds the minimum value from the added values in block units for error correction processing by the error correction circuit 130. To detect. As a result, the CV detection circuit 132 causes the error correction circuit 130 to perform the error correction processing on a block-by-block basis to obtain the most uncertain decoded data a.
One byte of _K is detected, and the detection result is output to the adjacent symbol generation circuit 134.

At this time, the CV detection circuit 132 detects the data CV having the smallest certainty in the most uncertain decoded data a _K 1 byte, and outputs the detection result together. Based on this detection result, the adjacent symbol generation circuit 134 selects from the most uncertain decoded data a _K ,
A bit having the smallest value of the probability data CV is detected, and decoded data obtained by inverting this bit is output (hereinafter referred to as adjacent symbol data).

As a result, the error correction block 46 detects the most uncertain decoded data based on the certainty data CV, and if the detected decoded data has a bit error, it generates the correct data. .

The error correction circuit 136 executes error correction processing of data of adjacent symbols. At this time, the error correction circuit 136 outputs an error correction result BOK indicating whether or not the error correction can be performed on the data of the adjacent symbol. The gate circuit 138, based on the error correction results AOK and BOK,
The contact of the selection circuit 140 is switched, and thereby the decoded data DV subjected to error correction processing is output to the subsequent signal processing circuit.

That is, when the error correction processing circuit 130 can perform error correction processing, the gate circuit 138 outputs the output data of the error correction processing circuit 130 to the subsequent signal processing circuit.

On the other hand, the gate circuit 138 outputs the output data of the error correction processing circuit 136 when the error correction processing circuit 130 cannot perform the error correction processing and when the error correction processing circuit 136 can perform the error correction processing. To the subsequent signal processing circuit. Further, the gate circuit 138 outputs the output data of the error correction processing circuit 130 to the subsequent signal processing circuit when the error correction processing circuit 130 cannot perform the error correction processing and when the error correction processing circuit 136 cannot perform the error correction processing. Output.

That is, in the RS (Reed-Solomon) code of Galois field (GF) 2 ⁸ , one symbol can be expressed by using the elements on GF (2), that is, 0 and 1, using 8 bits.

[Equation 51] For a ^f represented by

[Equation 52]

[Equation 53] It can be represented by a vector expression as shown in. However,
The method of selecting equations (52) and (53) depends on the primitive generator polynomial p (x) that forms GF (2 ⁸ ).

[Equation 54] Can be expressed as

Therefore, the decoded data a _K can also be expressed in the same manner, and in this embodiment, one symbol is formed with 8 bits. At this time, the probability Pr (8 → 1) of bit error in 1 bit data out of 8 bits is

[Equation 55] The probability Pr (8 → n) of bit error in n-bit data out of 8 bits can be expressed by the following equation.

[Equation 56] It can be expressed as.

At this time, with respect to the decoded data a _K input to the error correction processing circuit 130, this bit error rate is set to Pe, and this is given by

[Equation 57] Assuming that n satisfies the relation of n> 2,

[Equation 58] The relationship is established.

That is, at this level of error rate, 2
It can be seen that errors above the bit can be ignored. Therefore, considering a bit error of 1 bit in 1 symbol (that is, 8 bits) as in this embodiment,
It is understood that the bit error can be reduced within a practically sufficient range.

Here, the input data a of the error correction circuit 130
_The probability of _K for each bit a _i is CV _j ,
The probability with the smallest value is set as CV _min .
That is,

[Equation 59] If the error cannot be corrected for this symbol, the probability of error is the highest among the 8 bits of CV _min bit a _m . Therefore, when the input data a _K has a bit error, the data β ^f obtained by inverting the bit a _m has the highest probability of being the most correct data.

That is, in this embodiment,

[Equation 60]

[Equation 61]

[Equation 62] By generating the data β ^f of the adjacent symbol represented by the adjacent symbol generating circuit 134, the error correction capability of the error correction block can be remarkably improved.

Thus, in this embodiment, the likelihood CV of the decoded data a _K is detected by effectively using the likelihood data Δ _K detected by the Viterbi decoding circuit 42, and the error correction is performed by using this detection result. By doing so, the error correction capability can be improved with a simple structure, and the digital video signal can be efficiently recorded / reproduced accordingly.

Further, at this time, the adjacent symbol is generated based on the certainty data CV, and the decoded data or the adjacent symbol is selectively output by this, whereby the error correction capability can be improved with a simple structure.

(6) Effects of the Embodiments According to the above configuration, a predetermined reference value is set on the basis of + merging and / or −merging before and after, and the certainty of the decoded data is detected based on this reference value. By doing so, the likelihood can be detected for each bit of the decoded data with a simple configuration. Therefore, the adjacent symbol is generated based on the certainty data, and the decoded data or the adjacent symbol is selectively output based on the error correction processing result of the decoded data and the adjacent symbol, so that the certainty data is effectively used. Therefore, the error correction capability can be improved.

(7) Other Embodiments In the above-mentioned embodiments, when detecting the probability data CV in the arithmetic circuit, (17), (49),
Although the case has been described in which the constant term is omitted and the arithmetic processing is performed as shown in the equation (50), the present invention is not limited to this, and the arithmetic processing may be performed by including the constant term.

Further, in the above-mentioned embodiments, the case where the error correction processing is performed using the probability data is described, but the present invention is not limited to this, and can be widely used for various signal processing, for example, the sync pattern is used. The detection accuracy can be improved by utilizing it in the case of detection.

Further, in the above-mentioned embodiment, the case where the adjacent symbol is generated by using the data of the probability detected by the arithmetic circuit and the error correction capability is improved by this, the present invention is not limited to this. Instead, it can be widely applied to error correction using various analog weights (that is, soft-decision error correction).

Further, in the above-mentioned embodiment, the case where the adjacent symbol is generated by using the probability data detected by the arithmetic circuit has been described. However, the present invention is not limited to this and, for example, a Viterbi decoding circuit is used instead. In the bit-by-bit decoding circuit that decodes the reproduced signal based on the threshold values on the positive and negative sides, the amplitude of the input data is detected based on this threshold value, and this detection result is used as the accuracy data. You may do it.

Further, in the above-mentioned embodiments, the case where the present invention is applied to the video tape recorder has been described, but the present invention is not limited to this, and a reproducing apparatus for demodulating a reproduction signal obtained from a magnetic recording medium, and further It can be widely applied to the case of reproducing an input signal obtained through various transmission means.

[0135]

As described above, according to the present invention, the front and rear +
By setting a predetermined reference value based on merging and / or merging and detecting the certainty of the decoded data, the certainty can be detected for each bit of the decoded data with a simple configuration. As a result, error correction capability can be improved by performing error correction using the data of this certainty, and a reproducing device that can reproduce the digital signal efficiently can be obtained. Further, at this time, by generating the adjacent symbol by using the certainty data, it is possible to obtain the reproducing apparatus capable of improving the error correction capability with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a video tape recorder according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the reproduction data processing circuit.

FIG. 3 is a block diagram showing a Viterbi decoding circuit.

FIG. 4 is a schematic diagram showing + merging.

FIG. 5 is a schematic diagram showing non-merging.

FIG. 6 is a schematic diagram showing merging.

FIG. 7 is a schematic diagram for explaining the operation of the Viterbi decoding circuit.

FIG. 8 is a block diagram showing an arithmetic circuit.

FIG. 9 is a schematic diagram illustrating a case where merging continues.

FIG. 10 is a schematic diagram illustrating a case where -merging, non-merging, and -merging continue.

FIG. 11 is a schematic diagram illustrating a case where -merging, -merging, and -merging continue.

FIG. 12 is a schematic diagram illustrating a case where −merging, + merging, and −merging continue.

FIG. 13 is a schematic diagram showing a decoding range when merging is continuous.

FIG. 14 is a schematic diagram showing a case where + merging continues.

FIG. 15 is a schematic diagram illustrating a decoding result when + merging continues.

FIG. 16 is a schematic diagram showing a decoding range when + merging continues.

FIG. 17 is a schematic diagram illustrating a case where −merging and + merging continue.

[Fig. 18] Fig. 18 is a schematic diagram illustrating a decoding result when -merging and + merging continue.

[Fig. 19] Fig. 19 is a schematic diagram illustrating a decoding range in the case of continuous-merging and + merging.

FIG. 20 is a schematic diagram illustrating a case where + merging and −merging continue.

FIG. 21 is a schematic diagram showing a decoding result when + merging and −merging continue.

FIG. 22 is a schematic diagram showing a decoding range when + merging and −merging continue.

FIG. 23 is a chart for explaining the operation of the arithmetic circuit.

FIG. 24 is a block diagram showing an error correction block.

[Explanation of symbols]

1 ... Video tape recorder, 40 ... Reproduction data processing circuit, 41, 48, 98, 112, 118, 122 ...
Operation circuit, 42 ... Viterbi decoding circuit, 46 ... Error correction block, 84 ... Merge operation circuit, 130, 136
...... Error detection / correction circuit, 132 ・ ・ ・ CV detection circuit, 13
4 ... Adjacent symbol generation circuit, 140 ... Selection circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-372778 (JP, A) JP-A-4-298865 (JP, A) JP-A-3-16063 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G11B 20/10 G11B 20/18 H03M 13/23

Claims (3)

(57) [Claims] 1. A reproducing device to which a partial response system for reproducing input signals which are sequentially input is applied, and an analog digital conversion circuit which converts the input signal into a digital signal at a predetermined cycle and outputs input data, Detecting + merging and-merging of the input data based on the threshold value of the input data, decoding the input data based on the detection result of the + merging and-merging, and outputting the decoded data. Detect the likelihood of
A Viterbi decoding circuit that updates the threshold value based on the likelihood, and the data of the probability of the + merging and / or the −merging before and after each of the consecutive decoded data is detected, and based on the detection result. A reproducing apparatus, comprising: an arithmetic circuit for detecting the probability data of each of the decoded data. 2. A reproducing device to which a partial response system for reproducing input signals that are sequentially input is applied, and an analog digital conversion circuit that converts the input signal into a digital signal at a predetermined cycle and outputs input data. Detecting + merging and-merging of the input data based on the threshold value of the input data, decoding the input data based on the detection result of the + merging and-merging, and outputting the decoded data. Detect the likelihood of
A Viterbi decoding circuit that updates the threshold value based on the likelihood, and the data of the probability of the + merging and / or the −merging before and after each of the consecutive decoded data is detected, and based on the detection result. An arithmetic circuit for detecting the probability data of each decoded data, and an error correction circuit for error-correcting the decoded data based on the probability data of each decoded data and outputting the decoded data. Playback device. 3. The error correction circuit detects the most uncertain decoded data for each predetermined unit of the decoded data based on the probability data of each of the decoded data, and bit-inverts the most uncertain decoded data. And an adjacent symbol generation circuit for outputting an adjacent symbol and an error correction circuit for performing error correction processing on the decoded data and the adjacent symbol and selectively outputting the decoded data or the adjacent symbol based on the error correction processing result. The reproducing apparatus according to claim 2, further comprising: