KR19980066264A - Data decoding apparatus and method and data reproducing apparatus - Google Patents

Abstract

The error detection decoding apparatus decodes the encoded data to generate decoded data on a frame basis, generates decoding information on a frame basis, decodes error correction encoded data reproduced from a recording medium, decoded data and Decoded information is stored in correspondence with frame units, and the decoded data and the decoded information are retrieved from the storage location while being frame synchronized with address data indicating the physical location of the encoded data on the recording medium.

Description

Data decoding apparatus and method, and data reproducing apparatus

The present invention relates to an error-correction code (ECC) system for correcting and analyzing errors occurring in digital data reproduced from an optical disc. More particularly, the present invention relates to an apparatus and methodology for analyzing the operation of error-correcting code.

Video information, including video and audio, is typically digitalized, compressed and recorded at variable speeds as digital data on a recording medium. According to the MPEG (Mobile Picture Experts Group) standard, video information is divided into three types of pictures (or frames): i.e. intra-coded pictures (I-pictures), predictive-coded pictures (P-pictures), and bidirectional. It is encoded into a predictive-coded picture (B-picture). I-pictures are generated by intra-frame encoding a frame of video data. P-pictures are generated by forward predictive encoding a frame of video data with respect to other frames of video data, such as immediately preceding frames. A B-picture is reproduced by predictively encoding a frame of video data bidirectionally with respect to other multiple frames of video data. I-pictures, P-pictures, and B-picture sets can be grouped to form a picture group (GOP).

Audio data can also be digitized, compressed and recorded according to the MPEG standard. In addition, the audio data can be encoded by additional transformed acoustic coding such as ATRAC (trade name).

1 shows a data reproducing apparatus 100 for reproducing data from an optical disc 104 recorded at variable speed. The apparatus 100 includes a tracking servo 102, a pickup 106, a ring buffer memory 108, a multiplex data separator 110, a video code buffer 112, a video decoder 114, a decoding system 116. , Track jump detector 126, audio code buffer 132, audio decoder 134, ring buffer controller 136, and system controller 138. The multiplex data separator 110 includes a header separator 120, a switch 122, and a separator controller 130. The decoding system 116 includes a demodulator 118, a sector detector 124, and an error-correction code (ECC) circuit 128.

In the reproducing operation, the pickup 166 irradiates a laser beam to the optical disc 104, detects the light reflected from the surface of the disc, and generates a corresponding reproducing signal S1. The reproduction signal S1 is supplied to the demodulation circuit 118 for demodulation. The demodulated data is supplied to the sector detector 124 and the ECC circuit 128. The sector detector 124 detects the number of sectors of the disk 104 corresponding to the address where the reproduced data is stored on the disk. The detected number of sectors is supplied to the ring buffer controller 136. ECC circuit 128 detects and corrects errors in the demodulated data. The operation of decoding system 116 and ring buffer controller 136 is controlled by system controller 138.

The demodulator 118 converts the reproduction signal S1 into binary through RF processing and detects an EFM + (8, 16 conversion) sync pattern. According to the constant linear velocity CLV system, rough servo adjustment is applied according to the sync pattern detected in the reproduction signal S1. Then, upon detection of the sync header by the sector detector 124, a phase-lock loop (PLL) servo is applied. If the sync header is detected several times in succession, the EFM + demodulated data S2 will be deinterleaved. A more detailed description of the operation of the decoding system 116 will be described in the next section associated with FIG. 2.

If the sector detector 124 cannot detect the number of sectors, an abnormal signal is supplied to the track jump detector 126. If the demodulated data cannot be corrected by the ECC 128, an error generation signal is supplied to the track jump detector 126. The ECC 128 supplies the ring buffer memory 108 to temporarily store the error-corrected data S10. The ring buffer controller 136 allocates a write address, a write pointer WP in the ring buffer memory 108 corresponding to the address of the detected sector number provided by the sector detector 124.

In response to the code request signal R10 from the multiplex data separator 110, the ring buffer controller 136 assigns a read address, a read pointer RP according to the corresponding data stored in the ring buffer memory 108. The read pointer RP is supplied to the ring buffer memory 108 which supplies the corresponding data S12 to the multiplex data separator 110.

The header separator separates the pack header and the packet head from the data supplied by the ring buffer memory 108. The header data is supplied to the separator controller 130, and the time division multiplexed data, which is the remaining data, is supplied to the input terminal G of the switch 122. According to the stream identifier information included in the packet header data, the separator controller 130 controls the operation of the switch 122 to demultiplex the time division multiplexed data. In particular, the switch 122 is controlled to systematically connect the input terminal G with the output terminals H1 and H2, thereby transferring the coded video data to the video code buffer 112 and the coded audio data. Route to code buffer 132. According to the data request signal received from the video code buffer 112 and the audio code buffer 132, the multiplex data separator 110 generates a code request signal R10.

According to the data decoding operation, the video decoder 114 generates a data request signal R1 supplied to the video code buffer 112. Depending on its storage state, video code buffer 112 passes data request signal R1 to multiplex data separator 110 to request additional data. The buffer 112 temporarily stores the coded video data received from the separator 110. The video decoder 114 decodes the coded video data, and supplies the decoded video data to the output terminal OUT1.

According to another data decoding operation, the audio decoder 134 generates a data request signal R2 supplied to the audio code buffer 132. Depending on its storage state, the audio code buffer 132 passes the data request signal R2 to the multiplex data separator 110 to request additional data. The buffer 132 temporarily stores the coded audio data received from the separator 110. The audio decoder 134 decodes the coded audio data and supplies the decoded audio data to the output terminal OUT2.

The tracking servo 102 and track jump detector 126 are conventional devices.

As shown in FIG. 2, the ECC circuit 128 includes RAMs 202, 206, 210 and 214 and ECC decoders 204, 208 and 212. The ECC circuit 128 processes the EFM + demodulated data S2 according to the C1 / C2 siding Reed Solomon decoding methodology (CIRC Plus). The data S2 is retrieved from the sector detector 124, stored in the RAM 24, and decoded in three series methods by the ECC decoders 25, 2f7 and 29. First, after C1 decoding is performed, C2 decoding is performed, and finally, C1 decoding is performed at the second time C12.

The operation of the ECC decoding method of the ECC circuit 128 is shown in FIG. The EFM + demodulated data S2 is recorded in the RAM 202 (EFM + record) in the order of 00, 01, ..., A8, A9, and two frames of the EFM + demodulated data are stored. The data S2 is supplied to the ECC decoder 204 in the order of 00 ', 02', ..., A8 ', 01, 03, ..., A9 of the frame. The ECC decoder 204 performs ECC decoding of the deinterleaved C1 series data to produce C1 decoded data. C1 decoded data is supplied to RAM 206 (C1 write) for storage as shown in FIG.

Error correction can be achieved by reading the error location and correction pattern from the ECC decoder 204, simultaneously reading the corresponding error data from the RAM 202 (C1 read), and executing an exclusive OR with the correction pattern and error data. have.

The ECC decoder 204 allows C2 series decoding by executing C1 series decoding for the C2 code series length. The ECC decoder 208 executes C2 series decoding in accordance with the C1 decoded data supplied from the RAM 206 in the order of 00 ', 01', 02 ', 03', ..., A9 '(C2 read) to perform C2 decoding. Generate decoded data. The ECC decoder 208 allows C1 series decoding by executing C2 series decoding for the C1 code series length. C2 decoded data is supplied to RAM 210 (C2 write) for storage as shown in FIG.

Erasure correction can be achieved by sending a non-correctable flag for each frame to a successive stage ECC decoder synchronized with the data. For erasure correction of the C2 series, the uncorrectable flag of C1 cannot be used. In this case, the error correction operation is the same as that of C1.

The ECC decoder 212 executes C12 series decoding according to the C2 decoded data supplied from the RAM 210 in the order of 00 ', 01, 02, 03, ..., A9 (C12 read) to perform C12 decoded data. Create For erasure correction of the C12 series, the uncorrectable flag of C2 can be used.

When the error correction of C12 is completed, the ECC decoding results of the C12 series may be recorded in RAM 214 in the order of 00, 01, 02, 03, ..., A9. Accordingly, the RAM 214 stores ECC decoding results of the C1, C2 and C12 series stored and read in the order of 00, 01, 02, 03, ..., A9 (reading). The decoding result is descrambled and output to the ring buffer memory 108. Subsequently, necessary sector data can be recorded.

Since the number of errors processed in the ECC circuit 128 depends on the accuracy with which the disc is cut, the measurement of the number of error processes in the ECC circuit 128 serves as an evaluation of the disc quality. The location of the error can be measured by using the sector address as an indication of the location on the disk.

When the data is modulated in convolution with the C1 and C2 series, detection error correction in ECC is performed repeatedly with each series of ECC decoding such as C1, C2, C1. For example, ECC decoding of the C2 series may be performed after ECC decoding of the C1 series. Similarly, the second C1 series detection is performed after the C2 and C1 series decoding are performed. Thus, if a result is output immediately after execution of ECC decoding, a time delay will occur with respect to the detection time of ECC results of the same C1 series.

Thus, if the ECC result can be tracked by the system controller 138 to a location on the disc, the sector address detected by the sector detector 124 is recorded and the ECC result is considered. The time delay between the sector address and the ECC result must be calculated before analyzing the ECC result and the recorded data. This calculation is not clear due to its complexity.

In addition, the amount of data per unit time to be supplied to the ECC circuit 128 is proportional to the rotational speed of the dask. Therefore, the control timing for ECC processing may be influenced by the disk speed. As a further problem, when accessing a disk at high speed, if an error result is output immediately after ECC processing is executed, it is difficult to correlate each error result of the C11, C2 and C12 series with a specific sector address on the disk.

In view of the foregoing, it is an object of the present invention to provide an error correction data decoding methodology and apparatus for detecting error locations on a disc while accessing the disc at high speed.

It is another object of the present invention to provide a methodology and apparatus for detecting error locations on a disk that rotates at high speed without the use of indeterminate complex computations.

It is a further object of the present invention to provide a methodology and apparatus for detecting an error on a disc that correlates the error with its physical location on the disc and the result of the error correction method.

It is yet another object of the present invention to provide a methodology and apparatus for detecting errors on a disc recording medium for measuring the state of the disc recording medium.

1 is a block diagram of a data reproduction and error correction device of the prior art;

2 is a block diagram of the ECC circuit of FIG.

3-6 are schematic diagrams that may be referred to to explain data decoding processed by prior art ECC circuits.

7 is a block diagram of a data reproduction and error correction apparatus according to an embodiment of the present invention.

8 is a block diagram of the ECC circuit of FIG.

9 is a block diagram that may be referred to to explain the operation of the demodulator, sector detector, and ECC circuit of FIG.

FIG. 10 is a data diagram illustrating data stored in a RAM of FIG. 8. FIG.

FIG. 11 is a data chart detailing decoding information generated by the ECC circuit of FIG. 8; FIG.

12A and 12B are timing diagrams that can be referred to to explain the operation of the ECC circuit of FIG. 8.

FIG. 13 is a data format diagram showing a format of data output from the ECC circuit of FIG. 8; FIG.

Fig. 14 is a data format diagram showing a structure of sector data.

15 is a data format diagram showing a structure of an ECC block.

16 is a data format diagram showing interleaving of PO parity (external code).

17 is a data format diagram showing a structure of a data block.

18 is a block diagram of a demodulation circuit system in accordance with another embodiment of the present invention.

19 is a schematic diagram showing the structure of a physical sector.

20 is a schematic diagram showing the structure of a data sector.

Fig. 21 is a schematic diagram that can be referred to for explaining a data storage place in the memory.

22A to 22F are timing diagrams that can be referred to for describing data storage operations.

23 is a flowchart showing a lock detection method.

24 is a flowchart showing a method for generating an SCSY signal.

25 is a flowchart showing a main-FMSY signal.

26A-26H are timing diagrams that may be referenced to describe block-top detection operations.

27A-27H are timing diagrams that may be referenced to describe a post-block-top detection method.

28A-28F are timing diagrams that can be referred to to describe the SUB-transmission method.

29 is a schematic diagram showing a structure of sector information.

30 is a flow chart showing a method for continuous detection and measurement of an IED.

Fig. 31 is a flowchart showing a method of continuously measuring ID (address).

32 is a flowchart showing a method of generating SALK.

33A-33D are timing diagrams that may be referenced for describing error correction operations in accordance with the purpose of the present invention.

34A-34I are timing diagrams that may be referenced to describe error correction operations in accordance with the purpose of the present invention.

35A to 35E, 36A to 36E, and 37A to 37E are timing diagrams that can be referred to for explaining the ECC processing control operation according to the object of the present invention.

38 is a flowchart showing an ECC processing method.

39 is a block diagram of an error correction circuit system according to another embodiment of the present invention.

40 is a data chart showing details of decoding information processed by the ECC circuit of FIG. 39; FIG.

41A-41G are timing diagrams that may be referenced to describe bus arbitration.

42 is a table that may be referenced to illustrate memory accessing during detection of one ECC block in accordance with the purpose of the present invention.

43A to 43F are timing diagrams that can be referred to for describing an error correction result.

44 is a flowchart showing a data output method.

* Explanation of symbols for main parts of the drawings

100: data reproducing apparatus 102: tracking servo

104: optical disk 106: pickup

108: ring buffer memory 110: multiplex data separator

112: video code buffer 114: video decoder

116: decoding system 126: track jump detector

132: audio code buffer 134: audio decoder

136: ring buffer controller 138: system controller

According to the object of the present invention, a data decoding apparatus for error correcting decoding error corrected encoded data reproduced from a recording medium is provided. The apparatus includes error correction decoding circuitry for error correction decoding the error corrected encoded data to generate decoded data on a frame basis, and to generate decoding information on a frame basis. The memory device stores error correction encoded data, decoded data and decoding information. The error correction decoding circuit and the memory control circuit coupled to the memory device control the memory device to store decoded data and decoding information on a frame-by-frame basis, and address data indicating a physical location of the error correction encoded data on the recording medium. Decoded data and decoding information are retrieved from the memory device while frame synchronization is performed at a low speed.

According to another object of the present invention, there is provided a data decoding method for error correcting decoding error corrected encoded data reproduced from a recording medium. This method includes error correction decoding error corrected encoded data to generate decoded data on a frame basis, generating decoded information on a frame basis, error correction encoded data, decoded data and decoding information. Storing the decoded data and the decoding information according to the frame unit in the memory; and the decoded data and the decoding information from the memory while synchronizing the frame with address data indicating the physical position of the error correction encoded data on the recording medium. Searching for;

Other objects, features and advantages according to the present invention will become more apparent from the following detailed description of the embodiments shown when read in conjunction with the accompanying drawings, in which like elements are identified with identical reference numerals.

EXAMPLE

7 shows a data reproduction and data decoding apparatus 700 according to an embodiment of the present invention. Elements of device 700 having the same structure and function as that of device 100 are labeled with the same reference numerals as used in FIG. 1. The data reproducing and decoding apparatus 700 reproduces and decodes image data and audio data from the optical disc 104 recorded at variable speed.

As shown, apparatus 700 includes tracking servo 102, pickup 106, ring buffer memory 702, multiplex data separator 704, video code buffer 710, video decoder 712, decoding Circuit 714, track jump detector 724, ring buffer controller 730, and system controller 732. Decoding circuit 714 includes a demodulator 716, a sector detector 718, and an error-correcting code (ECC) circuit 726. The multiplex data separator 704 includes a header separator 706, a switch 708, and a separator controller 728. The decoding circuit 714 and the ring buffer controller 730 are controlled by the system controller 732 which is a control device.

Tracking servo 102 and pickup 106 are conventional devices. The pickup 106 controlled by the tracking servo 102 irradiates a laser beam to the optical disc 104 and detects a pattern of light reflected from the surface of the disc. In response to the pattern of reflected light, the pickup 106 generates a reproduction signal S1 representing the data recorded on the optical disc 104. The reproduction signal S1 is supplied to the demodulator 716.

Demodulator 716 is an apparatus for demodulating a modulated signal reproduced directly from a recording medium. The preferred structure of demodulator 716 is shown in FIG. 8 and will be discussed in the next section. The reproduction signal S1 is demodulated by the demodulator 716, and the demodulated signal S2 is supplied to the sector detector 718. The sector detector 718 is a detector device for measuring the sector address of the demodulated data reproduced from the optical disc. Sector detector 718 detects an address written in each sector of the data represented by demodulated signal S2, and supplies address, preferably the number of sectors, to ring buffer controller 730. The sector detector 718 supplies the ECC circuit 718 with the remaining data contents of the demodulated signal S2. This data transfer can occur during sector synchronization.

If the sector detector 718 does not detect an address, or if the detected address is not contiguous, the sector detector 718 outputs a sector number abnormal signal supplied to the track jump detector 724 through the ring buffer controller 730. Occurs.

The ring buffer controller 730 is a control circuit for controlling the read and write operations of the ring buffer memory 702 and for monitoring data request signals indicative of data requests by the multiplexed data separator 704. The ring buffer controller 730 assigns a write address and a write pointer WP to the ring buffer memory 702 corresponding to the address of the detected sector number provided by the sector detector 718. The ring buffer memory 702 is a ring buffer memory device having a first-in first-out (FIFO) function.

The ECC circuit 726 is an error correction code circuit for processing demodulated data and performing error correction. The detailed structure of the ECC circuit 726 is provided in FIGS. 8 and 9, which will be discussed in the next section. The ECC circuit 726 detects an error with the demodulated data S2, error corrects the data by using the extra bits recorded as the data, and outputs the error corrected data S10 to the ring buffer memory 702. do. The ECC circuit 726 detects sector header data with demodulated data S2 and supplies the header data to the system controller 732 through the sector detector 726. If the data error is not corrected by the ECC circuit 726, the error generation signal E10 is generated by the ECC circuit 726 and supplied by the system controller 732.

Track jump detector 724 monitors the output of ring buffer controller 730 to detect when a track jump is required. When a track jump is required, the track jump detector 724 generates a track jump signal JP1 supplied to the track servo 102. In response to the jump signal JP1, the tracking servo 102 controls the pickup 106 to jump its reproduction operation by one track on the optical disc 104.

When the system controller 732 detects a sector number abnormal signal from the sector detector 718 or an error occurrence signal from the ECC 726, the controller generates a tracking servo to cause a corresponding adjustment during the reproducing operation of the pickup 106. The track jump detector 724 is controlled to supply the track jump signal JP1 to 102.

The error-corrected data S10 stored in the ring buffer memory 702 is supplied to the multiplex data separator 704 as data S12 in accordance with a control signal supplied by the ring buffer controller 730. In response to the code request signal R10 from the multiplex data separator 704, the ring buffer controller 730 assigns a read address, read pointer RP, to the corresponding data stored in the ring buffer memory 702. The read pointer RP is supplied to the ring buffer memory 702 which supplies the data S12 corresponding to the multiplex data separator 704.

The multiplexed data separator 704 is a demultiplexing device for demultiplexing time division multiplexed digital data multiplexed according to standards such as MPEG, for example. The operation of the multiplex data separator 704 is controlled by the separator controller 726 and the control device.

The header separator 706 is a header data detection and extraction device. The header separator 706 separates the pack header data and the packet header data from the data S12 and supplies the header data and the like to the separator controller 723. Time division multiplexed data, which is the remainder of the data S12, is supplied to the input terminal G of the switch 708.

The switch 708 is an opening and closing device having an input terminal G and an output terminal H1 and H2. The open / close state of the switch 708 is controlled by the separator controller 728. The output terminals H1 and H2 are connected to the input terminal of the video code buffer 710 and the input terminal of the audio code buffer 720, respectively. In response to the control signal from the separator controller 728, the switch 708 routes video data to the video code buffer 710 and audio data to the audio code buffer 720.

The video code buffer 710 and the audio code buffer 720 are buffer storage memory devices. The video data stored in the video code buffer 710 is supplied to the video decoder 712 in response to the video data request signal R1 supplied by the video decoder 712. Audio data stored in the audio code buffer 720 is supplied to the audio decoder 722 in response to the audio data request signal R2 supplied by the audio decoder 722. The video code buffer 710 passes the video data request signal Rl to the multiplexed data separator 704 to request additional data, depending on its operating state. The audio code buffer 720 also passes the audio data request signal R2 to the multiplexed data separator 704 to request additional data frames, depending on its operating state.

Video decoder 712 is a video signal detector for decoding unencoded and demultiplexed video data. The detector 712 supplies decoded video data SV to the output terminal OUT1. Audio detector 722 is an audio signal detector for decoding unencoded and demultiplexed audio data. Detector 722 supplies decoded audio data SA to output terminal OUT2.

Since the amount of data per unit time required for decoding may fluctuate due to the change in the amount of compression of various segments of the image data, the video detector 712 and the audio detector 722 pass through the multiplex separator 704 through the ring buffer. The rate of requesting data from 702 can vary. For example, processing of a simple image would require less data from the ring buffer memory 702.

As a result, the ring buffer memory 702 may overflow when the pickup 106 continuously reproduces data from the disc 104. To avoid the overflow condition, the track jump detector 724 calculates the current amount of data stored in the ring buffer memory 702 from the positions of the write pointer WP and the read pointer RP. When the amount of data exceeds a predetermined reference value, the ring buffer memory 702 outputs a track jump command to the tracking server 102. In this manner, the amount of data needed to ensure proper flow of data from the ring buffer memory 702 to the multiplexed data separator 704 is obtained by switching the optical disk 104 during standby operation.

When the track jump detector 724 detects a sector number abnormal signal supplied by the sector detector 718 or an error occurrence signal supplied by the ECC circuit 726, the detector includes a write pointer WP and a read pointer ( The amount of data remaining in the ring buffer memory 702 is measured from the position of RP). If the amount of data in the ring buffer memory 702 is large so that underflow can be avoided even when data is read from the memory 702 at the maximum transfer rate, the track jump detector 724 jumps the track to the tracking servo 102. Supply a command (jump back). Thus, the tracking servo 102 jumps the pickup 106 to its regeneration position. The data on the disc corresponding to the error can be played back by the pickup 106. The ring buffer controller 730 slows or stops the entire writing of new data to the ring buffer memory 702 until the number of colorters detected by the sector detector 718 is equal to the number of sectors for the track jump. But. When the amount of data stored in the ring buffer memory 702 exceeds a predetermined reference value, the operation of writing data to the memory 702 is not delayed, and the track jump operation will be executed again. Data stored in ring buffer memory 702 is transferred to multiplexed data separator 704 as needed.

8 shows a preferred structure of an error-correction code (ECC) circuit 726 that provides ECC decoding in accordance with the C1 / C2 convolutional Reed Solomon code (CIRCplus). As shown, the ECC 726 includes an ECC detector 802, an error register 804, and a RAM 806. The ECC detector 52 is a decoding circuit for error-correcting the EFM + demodulated data and for ECC-decoding such data. The error register 804 is a memory device for storing flags, error correction patterns, and error positions that cannot be error corrected. RAM 806 is a ring buffer memory device.

9 shows a preferred structure of the decoding circuit 714. As shown, the decoding circuit 714 includes a demodulator 716, a sector detector 718, an ECC 726, a RAM interface (RMIF) 908, a constant linear velocity (CLV) controller 912, and a data bus ( 918). The random memory interface (RMIF) 908 is a memory interface device, and the constant linear velocity (CLV) controller 912 is a servo controller device.

As shown in FIG. 9, the demodulator 716 includes an RF processor 902 and an EFM + demodulator, while the ECC decoder 726 includes a RAM 806, an ECC decoder 802, and an output control circuit (OCTL). 916. The RF processor 902 is a processing device, and the EFM + demodulator is a device for demodulating signals modulated according to the EFM + methodology. RAM 806 is a frame memory device, and ECC decoder 802 is a decoding device. The output control circuit (OCTL) 916 is a data output device.

The ECC decoder 902 is shown to include an ECC decoder 904 and an ECC controller 910. The ECC decoder 904 is a decoding device. The ECC controller 910 is a controller device.

The ECC decoding method is described as follows with reference to the structures shown in FIGS. 8 and 9. The playback signal S1 is RF-processed in the RF processor 402, binary coded, and the EFM + sync pattern is detected by the demodulator 716. When the EFM sync pattern is detected, rough servo control is provided by the CLV controller 912. Then, when the sync pattern of the EFM + is detected by the demodulator 716, phase-locked loop (PLL) servo control is provided. According to various successive detections of the sync pattern, EFM + demodulated data S2 is dataribbed and written to RAM 806 via RMIF 908 on a frame-by-frame basis. After the data S2 is error corrected, the data S2 is output to the ring buffer memory 702 through the OCTL 916.

The ECC circuit 726 supplies the write address of the decoded data S2 to the RAM 806 via the RMIF 908 controlled by the system controller 732. Data read from the RAM 806 is transmitted to the ECC control section 910 and the ECC decoder 904 via the RMIF 908.

If an error is detected and can be corrected, the error location and the correction pattern of the error are output from the ECC decoding section 904 to the ECC controller 802. The error position and the error correction pattern are output to the RAM 806 in units of frames and stored in the error register 804.

The error is corrected by obtaining an error position and a correction pattern from the error register 804, obtaining error data corresponding to the error position from the RAM 806, and executing an exclusive OR with the error data and the correction pattern SP. . The corrected data is written to the RAM 806.

If uncorrectable data is detected, an uncorrectable flag for that frame is stored by the error register 804 for use in the subsequent corrective correction operation.

In this way, the Ere register 804 stores the error location and correction pattern for each series C1, C2 and C12 required for ECC processing. Once the necessary data, for example the error position and the correction pattern SP, are obtained, the data S2 stored in the RAM 806 is error corrected.

After error correction and ECC decoding, decoded data S10 and sector header data SH are separated and supplied to ring buffer memory 702 and sector detector 718 respectively. Through sector detector 718, sector header data SH is supplied to ring buffer controller 730. The ring buffer controller 730 may store the decoded data S10 in the ring buffer memory 702 according to the sector header data SH.

The memory address of the data RA is determined by using the frame output number Fn in the C1 code unit and the order of the data Dn in the C1 direction based on the data address of the RAM 806 shown in FIG. Can be calculated by In the following, numbers are quoted in hexadecimal.

Dn: data number ((00-A9)

Fn: frame number (00-B9)

RA: RAM address (0000-7FFF)

Fna = Fn + 46 + 101

Fna = Fna + Dn if (ECC Mode = C2)

(Fna FF), Fna = Fna + 46-100. (One)

(Dn = 00) AND (00 Dn 80)

RA = [(Fna) x 80] + Dn [6: 0]... (2)

(Dn = 80) AND (80 Dn A0)

RA = [(Fna + 18) x 20] + Dn [4: 0]... (3)

(Dn = A0) AND (A0 Dn AF)

RA = [(Fna + BA-100) x 10] + Dn [3: 0]... (4)

The RMIF 908 performs ECC decoding of three series C1, C2, and C12 with the AA, AB, AC, AD, AE, and AF addresses of the frame including the data leading each series. Write to RAM 806. When ECC results are written in AA, AB, AC, for example, the memory address RA of RAM 806 corresponding to the ECC decoding results for three series C1, C2 and C12 is frame number Fn and data. It can be easily generated by using the numbers AA, AB and AC.

Error information corresponding to coded data recorded on the optical disc 104, which is an ECC result ER, is represented by 8-bit data in the format shown in FIG. According to this format for ER, the ECC correction number is set to bits 0, 1, 2 and 3, the presence or absence of an error is set to bit 4, the ECC result of the C12 series is set to bit 5, the ECC result Is set to bit 6 and the indication that an error cannot be corrected is set to bit 7.

By using this format it is possible to monitor the number and type of ECC corrections as well as the presence and absence of errors.

12A and 12B show examples of output timings of the ECIC result ER.

12B is an enlarged view of one frame cycle of FIG. 12A. After the ECC decoding is executed, the ECC decoding results ER of the three series C1, C2 and C12 are output in units of frames together with the sector address data. The ECC result ER read from RAM 806 via user data DAT (e.g. video data and / or audio data), sector address data ADD and RMIF 908 is passed via OCTL 916. It is output via the bus 918. Strobe signals (ASTB, DSTB, ESTB) are added to each data to measure the data content.

In the apparatus 700 for providing an appropriate amount of data for decoding processing, in RFCK, the channel bit rate of reproduction is set to a value much larger than the reference channel bit rate of 26.6 Mbits / s at the time of disc recording (cutting). .

When ECC decoding is completed by the ECC circuit 726, the ere strobe signal ESTB providing the output timing of the ECC result ER is output from the OCTL 916 in a normally ECC-decoded frame. For example, as shown in Fig. 12B, since only the frames of the C1 series can be decoded due to the difference in the interleaved length, the ER of the C1 series is output as ESTB = 1.

The address strobe signal ASTB providing the output timing of the sector address ADD on the disk 104 is continuously output. By reading the data during the period when the address strobe signal ASTB = 1, the position on the optical disc 104 corresponding to the read frame can be confirmed. As shown in Fig. 12A, since the sector address ADD is located at the start frame of the multi-frame sector, ASTB = 1 for the frame having the sector address ADD. Therefore, immediately after the data strobe signal DSTB, the user data DAT is instructed (Fig. 12B).

13 shows a preferred sector format for S10 data output from bus 918. After 3 bytes of the error result ER are output, sink data, header data, and user data are output for each frame.

The ECC result ER, which has been decoded in each series of the user data DAT and the user data DAT decoded by the RMIF 908, is output from the RAM 806, and the user data DAT as the ECC result ER. Is supplied as the output data S10 together with the sector address data ADD with frame synchronization. By this method, the ECC result ER corresponding to the sector address ADD of the optical disc 104 is easily detected. Therefore, the error detected in the data reproduced from the disc and its ECC correction are easily analyzed. Even when the disc is accessed at high speed, the ECC error can be analyzed at about the same time as the data is played from the disc.

14 to 17 show data formats according to another embodiment of the present invention when recording in one cluster unit (32 kilobytes). As shown in Fig. 14, two kilobytes (2,060 bytes) of data are extracted as one sector, and four bytes of overhead are added. The overhead includes an error detection code (EDC) for detecting errors.

As shown in Fig. 15, data of 2,064 (2,060 + 4) bytes corresponding to one sector is formed as data of 12 x 172 (2,064) bytes. Sixteen data sectors are collected and configured as 192 (= 12x16) x 172 bytes of data. The 16-byte external code PO is added to 192 x 172 bytes of data for each byte in the vertical (column) direction as parity. The 10-byte internal code PI is added to 208 (= 192 + 6) x 172 bytes of data for each byte in the horizontal (row) direction as parity.

As shown in Fig. 16, data blocked by 208 (= 192 + 6) x 182 (= 172 + 0) bytes, an external code (PO) column of 16 x 182 bytes is divided into 16 columns of 1 x 182 bytes, and , Each of which is inserted under each of the 16 sector data including 12 x 182 bytes, numbered 0 to 15, and interleaved. Thus, one sector of data includes 13 (= 12 + 1) x 182 bytes.

The data of 208 x 182 bytes shown in FIG. 16 is vertically divided into two frames as shown in FIG. A block of 91 bytes is treated as one frame. The two byte frame synchronization signal PS is added at the beginning of each of the data of the 91 byte frame. As a result, the data of one frame is summed up to 93 bytes in total, and the entire data structure is composed of 208 x (93 x 2) bytes as shown in FIG. It is defined as data of one cluster (one ECC block). The actual data section, excluding the overhead section, is 2 kilobytes (= 2,048 x 16 / 1,024 kilobytes).

One cluster (1 ECC block) is composed of 16 sectors, and one sector is composed of 24 frames. In a separate embodiment, data is recorded on the optical disc 104 in clusters.

18 shows a demodulation device 1800 based on device 700 that is compatible with the separate data format described above. The demodulation device 1800 includes a demodulator 716, a constant linear velocity (CLV) controller 1806, a drive interface 1808, a sector detector 718, a RAM controller 1812, an error-detection code (ECC) circuit 726. ), And a host CPU 1814.

Demodulator 716 is a demodulation device that includes an RF processor 1802 and an EFM + demodulator 1804. The RF processor 1802 is a processing device. EFM + demodulator 1804 is a demodulation circuit for drumming EFM + encoded data. CLV controller 1806 is a controller device. Drive interface 1808 is an interface device. Sector detector 718 is a sector detection device including subcode (SBCD) circuit 1810. SBCD 1810 detects the sector as the signal output demodulated by EFM + demodulator 1804. RAM controller 1812 corresponding to RMIF 908 (FIG. 9) is a control device for controlling the writing of data from RAM 1818 to RAM 1818. Host CPU 1814, corresponding to system controller 732 (FIG. 7), controls each section of device 1800.

The ECC 726 is an error-correcting code device including an ECC control unit 1816, a ring buffer memory 1817, an ECC core 1820, and an output control (OCTL) circuit 1822. The ECC controller 1816 is a control device that uses the ECA, ECD, and SFLG supplied from the ECC core circuit 1820 to substantially correct the error.

Ring buffer memory 1817 is a buffer memory device that includes RAM 1818.

The RAM 1818 is a memory device that temporarily stores data when the ECC controller 1816 corrects an error. ECC core circuit 1820 corresponding to ECC decoder 904 (FIG. 9) generates ECA, ECD, and SFLG for supply to ECC controller 1816 using Reed-Solomon codes (PI and PO). The output control (OCTL) circuit 1822 performs EDC descrambling and controls the output of the data.

In the following description, a significant number of abbreviations have been used, which are defined and described just below for the convenience of the reader.

H: logical high signal

L: Logical Low Signal

Block-top: Signal that is H at the time of sector when SYLK signal is H

C11M: System operating clock with frequency of 11.2896 MHz

DSTB: Data strobe signal that is H while main data is output as stream data (SD)

ECA: error correction address indicating the location (address) of the error

ECCK: Operation Clock for ECC Core Circuit 1820

ECD: Error correction data to correct data when added exclusively and logically to error data

ECDE: Control signal to indicate the end of input data

ECOD: This signal is H when the error is found to be uncorrectable.

ECOR: Strobe signal indicating the output of data together with data that can be corrected (ECA, ECD)

ECYE: Control signal indicating the end of a cycle of input coded data

EDT: data read from RAM 1818 and sent to ECC controller circuit 1816 for error correction

ESTB: Error correction strobe signal that is H during transmission of error correction result (ER)

ESTT: Control signal indicating the start of input data

EFM + W Frame: (EFM + Write Frame Counter) This signal indicates the main frame to be written to RAM 1818.

HDEN: Strobe signal for sector header data

Main-FMSY: (Main Frame Sink) This signal is H at the main sink (leading sink) of each PI column.

MWEN: (Write Enabled Memory) This signal enables EFM + demodulated data to be written to RAM 1818.

MWRQ: (Write Requested Memory) This signal indicates a request to write EFM + demodulated data to RAM 1818.

OUTE: interpolation (output) flag

OSTT: (start ECC output) This signal outputs ESTT after 477 ECCK in a particular code sequence.

RDT: data on a read data bus to RAM 1818

SALK: (sector address lock) This signal indicates that the sector address ID is correctly detected.

SAUL: (sector address unlock) A signal with the opposite polarity as the SALK signal.

SCSY: (sector sync) This signal goes H in the SY0 frame to indicate the start of a sector.

SD: stream data (decoded output data)

SDCK: Stream Data Clock

SPLG: Sector flag indicating an uncorrectable error for PI1 correction

SINF: Sector information strobe signal that becomes H at the start of a sector

SUB: Data transmitted to SBCD circuit 1810, including ID and IED

SYLK: (Sink Lock) This signal goes to H when three sync codes are detected consecutively.

SYUL: (Sink Unlock) This signal has the opposite polarity as the SYLK signal.

WDT: data on the write data bus to RAM 1818

XHWE: (Write Enabled Sector Header) This signal enables the output of sector information to be supplied from the SBCD circuit 1810 to the RAM 1818.

The RF processor 1802 receives the RF signal reproduced by the pickup 106 from the optical disc 104 (shown in FIG. 7), and converts the RF signal into a binary signal. The binary signal is supplied to the EFM + demodulator 1804. EFM + demodulator 1804 applies EFM + demodulation to a binary signal and detects a synchronization pattern in the signal. Based on the synchronization pattern supplied from the EFM + demodulator 1804, the CLV controller 1806 controls the drive interface (drive IF) 1808 to roughly adjust the optical disc servomechanism (not shown) so that the internal sync code (Fig. The rotation of the optical disc 104 is further adjusted by enabling detection of SY0 to SY7) of 22A to 22F and allowing a servo mechanism (not shown) on the locked loop (PLL).

19 shows an example of the structure of the physical sector of the optical disc 104. As shown in FIG. As shown, the physical sector comprises 26 sync frames: two horizontal sync frames and 13 vertical sync frames. Each sync frame is composed of 32 channel bits of sync code SY0 to SY7 (16 bits (= 2 bytes) represented as data bits before modulation) and 1,456 channel bits of data section (728 bits represented as data bits before modulation (= 91). Bytes)). The data section of the leading sync frame includes ID information (sector number), IED information (error-detection code for ID), and main data, for example audio and video data.

Preferably, the lower 22 bits of the sync pattern of 32 channel bits are set to 0001000000000000010001, which is defined as a unique pattern that does not appear in the data.

As shown in Fig. 19, the data section of each sync frame on the left side of the figure has main data recorded thereon, and the data section of the last sync frame on the left side of the figure shows PO (parity) information recorded thereon. Have The sync frame on the right side of FIG. 19 has main data and PI information recorded above = 1, and the final frame except one sync frame on the right side of the figure has EDC and PI (parity) information recorded thereon, and The final sync frame on the right side has the PO and PI information recorded on it.

20 shows a further detailed description of the data in each sector except for the PI and PO information. Data in one sector contains ID (sector number) (4 bytes), IED (error-detection code for ID (2 bytes)), RSV (conserved area) (6 bytes), main data and EDC (4 bytes). Include. The main data is preferably scrambled.

Sixteen such sections of data were collected and 16 bytes of PO code and 10 bytes of PI code were added to the data sector as shown in FIG. 15. PO codes are interleaved between 16 rows to be located within each data sector. The obtained data is added to the frame synchronization (FS) code represented by the sync code SYx (x = 0, 1, 2, ... 7) as shown in FIG. 17, and then EFM + demodulated. This organizes the physical sectors in the ECC block into 13 x 2 sync frames as shown in FIG.

Since the ECC block is composed of 16 sectors, the lower 4 bits of the physical sector address are any of 0000 to 1111. As a result, the physical address of the leading sector of the ECC block is 0000.

The main data is preferably scrambled by adding exclusively logically scrambled data generated using a value specified by the lower four to seven bits of the physical sector address as an initial value.

The data demodulated by the EFM + demodulator 1804 (FIG. 18) is stored in the RAM 1818 under the control of the ram controller 1812. 21 shows one ECC block of data. In reading the data stored in the RAM 1818, the RAM controller 1812 preferably obtains the desired data by specifying its address by row and column as shown. For example, the data x of the Nth byte of the Mth row can be read from the RAM 1818 by specifying two values (M, N).

When the SBCD circuit 1810 recognizes the start of a sector of data recorded on the optical disc 104 based on the type and continuity of the sync code, the data demodulated by the EFM + demodulator 1804 starts with leading data. Stored in sequence in 1818.

22A-22F show corresponding signal timings and will be described in detail below.

23 is a flowchart illustrating a method of the EFM + demodulator 1804 for detecting a sync lock state. In step SP1, it is measured whether or not the sync codes SY0 to SY7 shown in Fig. 19 are detected in each sync frame. If so, the method proceeds to step SP2 to increment the variable SC lock by one and set the variable SC unlock to zero. The variable SC lock indicates the number of successively detected sync codes, and the variable SC lock indicates the number of consecutive failures to detect the sync code.

Next, in step SP3, it is measured whether or not the variable SC lock is equal to 3, which indicates a state in which three sync codes are continuously detected. If the variable SC lock is less than 3, the method returns to step SP1, otherwise processing proceeds to step SP4. In step SP4, the sync lock state is initialized and it is measured whether the SYLK signal is set to H. In step SP5, the variable SC lock is set to 2, and the process returns to step SP1 to further measure whether three sync codes have been detected successively.

However, if the sync code has not been detected at all, and measured in step SP1, the method is advanced to step SP6. In step SP6, the variable SC lock is incremented by one, and the variable SC lock is set to zero. The processing proceeds to step SP7, where the variable SC unlock is measured whether or not equal to 3 indicating that detection of the sync code has failed three times in succession. If the detection of the sync code fails twice in succession, the method returns to step SP1. If the detection of the sync code has failed three times in succession, the method proceeds to step SP8 to set the SYLK signal to L.

The method further passes from step SP8 to step SP9 to set the variable SC unlock to two. If no sunk code is detected at the next sync code occurrence, the variable SC unlock is set to 2 to keep the SYLK signal at L. The method then returns to step SP1.

In this way, EFM + demodulator 1804 detects a sync code that monitors whether the sink is locked. In the above embodiment, it is preferable to set the reference number in case of detection or failure to 3, and the reference number NLOCK of the continuous detection time and the reference number NUNLOCK of the continuous failure time may be set to different values, respectively.

EFM + demodulator 1804 executes the method shown in the flow chart of FIG. 24, at which time the SYLK signal becomes H, i.e., the lock state is initialized as described above. In step SP21, it is measured whether or not the sync code SY0 located at the start of each sector is detected. If so, the method passes to step SP22 to set the SCSY signal representing the start of the sector to H for a specified time. The method then proceeds to step SP23 to measure whether the SYLK signal has changed to L, otherwise (i.e., the signal remains H), the method repeats similar processing (SP21). Return to). If it is determined in step SP21 that the sync code SY0 is not detected, the processing proceeds to step SP23.

As noted above, the EFM + demodulator 1804 generates a SCSY signal at the beginning of each sector as shown in FIG. 22A.

Moreover, when the SYLK signal goes to H, the EFM + demodulator 1804 performs the method shown in the flowchart of FIG. In step SP31, when the two horizontal sync frames shown in FIG. 19 are collectively referred to as the main frame, it is measured whether a sync code is detected in the main frame. The sync code shown on the left side of FIG. 19 is referred to as the main frame sync. If so, the method passes to step SP32 so that the EFM + demodulator 1804 can generate the main-FMSY signal shown in FIG. 22B. If no main frame sync is detected at step SP31, the processing at step SP32 is skipped, and the processing proceeds to step SP33.

In step SP33, it is measured whether the SYLK signal changes to L, and if not (ie, the signal remains H), the method returns to step SP31. In contrast, the generation of the main-PMSY signal is stopped. In this way, EFM + demodulator 1804 generates a Main.-FMSY signal every main frame sync period (period of two horizontal sync frames in FIG. 19).

When the SCSY signal is input by the DFM + demodulator 1804, the RAM controller 1812 sets the MWEN signal to H as shown in FIG. 22D, and writes currently detected sector data to the RAM 1818. The RAM controller 1812 uses an EFM + W frame counter (not shown) to count the main frame shown in FIG. The timing of this operation is shown in Fig. 22E. This count value indicates the number of upward main frames shown in FIG. 19, starting from the top of the main frame.

The RAM controller 1812 uses a PI1 frame counter (not shown) to manage the number of main frames sent to the RAM 1818. The timing of this operation is shown in Fig. 22F.

When the data of the first main frame (numbered 0) shown in FIG. 19 is written to the RAM 1818, this data of the main frame is supplied to the ECC controller 1816 under the control of the ram controller 1818. The ECC controller 1816 sends this data to the ECC core circuit 1820 for error correction. The ECC core circuit 1820 performs PI1 processing and correction. Once corrected, data is written back to RAM 1818.

After PI1 correction (first process of PI correction), RAM controller 1812 reads the ID and IED data (SUI3) from zero-numbered mainframe data stored in RAM 1818, and stores this data in FIG. 22C. Transmit to SBCD circuit 1810 via the data bus in accordance with the timing of the SUB signal numbered zero. Since the ID and IED data are located only at the time of each sector as shown in Fig. 19, this transmission is performed only from the main frame of number zero. The SBCD circuit 1810 then detects the address ID of the corresponding physical sector.

The lower 4 bits of the address of the detected physical sector enable the leading sector of the ECC block to be detected.

26A to 26H are timing diagrams showing the block-top direction after transmission of ID, and FIGS. 27A to 27H are timing diagrams showing the process following the block-top direction. These timing diagrams are described in more detail later.

28A to 28F are timing diagrams showing timing for transmission of ID. As shown in FIG. 28A, the RAM controller 1812 supplies an HDEN signal to the SBCD circuit 1810 indicating the timing at which ID and IED data (2 bytes) are read from the RAM 1818. ID data (4 bytes) and IED data (2 bytes) are read data RDT (FIG. 28C) containing 8 bits (bits 7-0) as clock C11M (FIG. 28F) at a frequency of 11.2896 MHz from RAM 1818. Is transmitted to the SBCD 1810 synchronized.

The SFLG signal (= 1) supplied by the ECC core 1820 to the ECC controller 1816 indicates that the ID and IED data have been corrected by the PI1 correction process (if it cannot be corrected, the SFLG signal is H). Upon receiving the ID (sector address), the SBCD circuit 1810 responds to the sector information corresponding to this ID (sector) according to an instruction from the host CPU 1814 such as an interpolation flag, a start sector, and a generation mode for the end sector. (SI) occurs. For example, for a sector having an ID specified by the host CPU 1814 as data to be output, sector information bit 5 is set to 1 and bit 4 is set to 0.

Fig. 29 shows the structure of the sector information SI. As shown in this figure, each bit of sector information SI represents the following information.

Bit 7: Setting the interpolation flag (OUTF) generation mode

(1: interpolation flag generation mode)

Bit 6: Reading error of ECC block (1 when the lower 4 bits of the physical sector address are 0) (1: leading sector)

Bit 5: Start sector (1 when physical sector address matches start sector address specified by host CPU 40) (1: Start sector)

Bit 4: End sector (1 when the physical sector address matches the end sector address specified by the host CPU 40) (1: End sector)

Bit 3: Bit 3 of the descramble initialization address (7th bit of the physical sector address)

Bit 2: Bit 2 of the descramble initialization address (sixth bit of the physical sector address)

Bit 1: Bit 1 of descramble initialization address (5th bit of physical sector address)

Bit 0: Bit of descramble initialization address bit 4 of physical sector address)

After the 4-byte ID and the 2-byte IED are used to check as described below with reference to Figs. 30-32, the XHWE signal shown in Fig. 28D is set to L by the ECC controller 1816. The sector information SI is transmitted and recorded from the SBCD circuit 1810 to the RAM 1818 as 8-bit write data WDT.

Sector information for 16 sectors is stored so as to correspond to 16 PI rows of the position, as shown in FIG. Thus, by specifying the number of specified PI rows, corresponding sector information can be obtained.

A description of how the SBCD circuit 1810 checks the ID and the IED will be described with reference to the flowcharts shown in FIGS. 30 to 32. The SBCD circuit 1810 measures whether there are N consecutive sectors measured to have a normal IED check result, and in this embodiment preferably three consecutive sectors, for example no error is detected in the ID. The processing shown in the flowchart of FIG. 30 is executed for this purpose.

In step SP41, it is measured whether the obtained IED check is normal. If so, the method proceeds to step SP42 to increment by one the variable SA lock indicating the number of sectors having a normal ID. The variable SA unlock, which indicates the number of consecutive sectors having an abnormal ID, for example an error in the ID, is set to zero.

After step SP42, the processing method proceeds to step SP43 to determine whether the variable SA lock is equal to three. If it is determined that the variable SA lock weighted in step SP42 is not equal to 3, the method returns to step SP41. If the variable SA lock is determined to be equal to 3, that is, three sectors with normal IDs are reproduced in succession, the method passes to step SP44 to set the flag IECOK to H. After step SP44, in step SP45, the variable SA lock is set to 2, and the processing method returns to step SP41 to detect the number of successive normal results from the subsequent IED check.

If the IED is determined to be abnormal at step SP41, the method passes to step SP46 to increment the variable SA lock one by one and set the variable SA lock to zero. Then, in step SP47, it is determined whether the variable SA unlock is equal to 3, and if not, the method returns to step SP41.

If the variable SA unlock is measured to be equal to 3 in step SP47, that is, if three sectors with abnormal IED check results are detected in succession, the method proceeds to step SP48 with the flag IECOK set to L. do. In a subsequent step SP49, if the next IED check precludes abnormal results, the variable SA unlock is set to 2 and the processing returns to step SP41 to detect three consecutive sectors having abnormal IED check results. do.

As noted above, the SBCD circuit 1810 sets the flag IECOK to H if three or more consecutive IED checks result in normal results, while the flag IECOK if three or more consecutive IED checks result in abnormal results. Is set to L. The SBCD circuit 1810 further performs the method shown in FIG. 31 to measure the continuity of the ID (address). It is preferable that IDs of sectors in one ECC block are sequentially increased.

First, it is measured whether an ID (sector address) is detected. If so, the method proceeds to step SP62 to store the ID for comparison with a subsequent ID.

In the next step SP63, it is measured whether the current ID is greater than the last detected and stored ID. If so, the method proceeds to step SP64 to increment the variable NS one by one indicating that the current ID is continuously detected. The variable NNS indicating that no ID was detected at all or the detected ID is not continuous is set to zero.

After step SP64, it is measured at step SP65 whether the variable NS is equal to 3, and if not (i.e., the detection of each of three consecutive IDs incremented by one fails), SP61). If the variable NS is determined to be equal to 3, the method passes to step SP66 to set the flag AS to H, indicating that the continuous ID is normal. If the subsequent ID is detected in step SP67, the variable NS is set to 2, and the processing method returns to step SP61 to further detect that three consecutive correction IDs have been detected.

If the ID is not detected at all in step SP61 or if the currently detected ID is no more than one larger than the previous ID in step SP63 (the ID is measured as not continuous), then the method has a flag SALK. Proceeding to step SP68 to determine whether or not H. The flag SALK is described below with reference to FIG. 32 and is set to H when three or more consecutive IED checks result in a normal result and the continuity of three or more IDs is maintained.

If the flag SALK is measured to be set to H in step SP68, the method proceeds to step SP69 to interpolate the ID. Since no ID is detected at all, or the detected ID is not contiguous, 1 is added to the previous ID to generate a new ID, which is used instead of the detected ID. After step SP69, the processing proceeds to step SP70. If the flag SALK is detected as L in step SP68, the processing proceeds to step SP70.

In step SP70, the variable NNS is incremented by one, and the variable NS is set to zero. At step SP71 it is measured whether the variable NNS is equal to 3, and if not, the method returns to step SP61. However, if the variable NNS is measured to be equal to 3, the method passes to step SP72 where the flag AS is set to L. If the subsequent ID is not detected in step SP73, the method returns to step SP61 to set the variable NNS to 2 and further detect three consecutive failures in detecting the ID.

As described above, the SBCD circuit 1810 sets the flag AS to H when the IDs are continuous, while setting this flag to L when the IDs are not continuous. SBCD circuit 134 uses the two flags IECOK and AS generated in the same manner as above to generate flag SALK.

As shown in the flowchart of FIG. 32, it is measured at step SP81 whether the flag IECOK is H, and if so, the method proceeds to step SP82 to measure whether the flag AS is H. If it is measured in step SP82 that the flag AS is H, the method passes to step SP83 where the flag ASLK is set to H.

If the flag IECOK is measured to be L at step SP81 or if the flag AS is measured to be L at step SP82, the method passes to step SP70 where the flag SALK is set to L.

As described above, the SBCD circuit 1830 sets the flag SALK to H when three or more consecutive IEDs are normal or three or more consecutive IDs are each increased by one. The flag SALK is set to L when three or more consecutive IEDs are abnormal or detection of three consecutive IDs fails.

The host CPU 1814 detects the access position of the pickup 106 on the optical disc 104 by referring to the SALK flag and the ID data.

The PI1 correction result can be added to the SA lock or SA unlock state shown in Figs. 33A to 33D. Moreover, although the reference number for the SA lock or SA unlock is preferably set to 3, it can be set to a different value by the host CPU 1814.

When SYLK becomes L when SALK = L (SALK = H), the recording of the EFM + demodulated data by RAM 1818 and ECC controller 1816 by EFM + demodulator 1804 is reset. The unlock state is sequentially canceled (SAUL = L), and SYLK becomes H. The record of EFM + demodulated data then reoccupies RAM 1818.

The unlock is forcibly executed by the host CPU 1814. For example, the host CPU 1814 may initiate an unlock state after track jump to reset the ECC controller 1816. The unlock ecology may simply be automatically canceled without instructions by the host CPU 1814 or by the host CPU 1814.

If SYLK = H (locked state) and bit 6 of the sector information is 1 indicating the start of the sector, the SBCD circuit 1810 goes to SYLlC to L indicating that the lock is relaxed as shown in Figs. 26A to 26H. Keep the block-top at H until

In the case of block-top = L, the value of the EFM + W frame changes from 12 once to 0 when SCSY and main-FMSY become H indicating the start of the sector. The value of EFM + W changes repeatedly from 0 to 12 for each main frame.

However, when block-top = H, the value of the EFM + W frame continues to increase even after reaching 13 as shown in Figs. 27A to 27H. As a result, the data of the main frame of each ECC block are sequentially stored at different addresses of the RAM 1818 as shown in FIG.

The EFM + demodulated data is written sequentially and similarly to RAM 1818, during which PI1 correction is performed. Once PI1 correction of the data in one ECC block (208 columns of data) is completed, ECC processing in the PO column direction is executed (PO correction).

In order to read data in the PO column direction, the PO rows must be interleaved (FIG. 16). Thus, when the column corresponding to the Nth byte shown in FIG. 21 is read, the data of this column is read down, its interleaved PO row is skipped, and the code of the only PO rows in the same column corresponding to the Nth byte Is read and supplied to the ECC core circuit 1820.

Once the ECC core circuit 1820 is completed, PO correction (all columns except the PI column on the right side of FIG. 21 (ie, column 172) are processed), and PI2 correction (second process of PI correction) is executed. . ECC processing in the PI row direction is executed twice to improve error correction performance.

In PO correction, erasure correction is performed depending on the error flag (PI1 flag) generated based on the result of the PI correction. In PI2 correction, erasure correction is performed using an error flag (PO flag) that is also generated based on the result of the PO correction. These erase corrections are performed to improve error correction as described above.

The PI sequence of PI2 corrected data is sent from RAM 1818 to OCTL circuit 1822, where main data is descrambled for each sector using bits 3 through 0 of the sector information shown in FIG. The OCTL circuit 1822 also executes EDC-related operations. Based on the result of this operation and the presence of an error flag added to the main data, it is determined whether any error exists in the desired sector. Based on this measurement, the host CPU 1814 measures whether data can be read back from the optical disc 104. If so, the host CPLT 1814 attempts to access the optical disc 104 again. Alternatively, the data in the sector containing the error is output to the multiplex data separator 704 (FIG. 7).

ECC core circuit 1820 includes a general Reed-Solomon code error correction (LSI) in which core length, parity number, and correction mode (both normal or normal and sweep correction) can be programmed. The ECC core 1820 preferably enables multi-coded, sequentially coded data (plural code sequences of different code lengths) to be decoded in real time. Reed-Solomon code error correction (LSI) includes, for example, CXD307-111G (trade name) available from Sony, and application specific integrated circuits (ASICs) formed using these LSIs can operate as ECC cores. have. This ECC core can be arbitrarily inserted into the ECC core circuit 1820 shown in FIG.

33A-33D show timing of signals during error correction operations. In this figure, ESTT (FIG. 33A) is a control signal indicative of the start of a code (PI or PO row), and ECDE (FIG. 33B) is a control signal indicative of the end of a code (PI or PO line). ECYE (FIG. 33C) is a control signal indicating the end of a code (PI or PO row) cycle. These signals are supplied from the RAM controller 1812 to the ECC core circuit 1820 through the ECC controller 1816. The ECC core circuit 1820 uses these control signals to verify the data supplied from the RAM 1818.

As shown in Figures 33A-33D, the PI code is transmitted during 182 ECCK between ESTT and EDCE. The PO code is also sent during 208 ECCK between ESTT and EDCE.

If the code of the PI row and the code of the PO column have different code lengths, the data to be corrected (EDT) and the error flags for erasure correction (PI1, PI2 and PO flags) are the PI row and PO column code lengths (in this embodiment). By adopting a code cycle length longer than 208 of the PO column code, the code sequence can be input at the same timing, as shown in FIGS. 33A-33D. These values can be set for parameters such as code length and parity number. This setting can be changed by supplying the new setting data to the ECC core circuit 1820 and automatically changing its internal setting based on the supplied data when the ESTT goes to H.

The data correction result is output using 477 ECCK cycles as shown in the following equation.

[Equation 5]

Throughput = 2 x NCYC + 3 x PCYC + 13

= 2 x 208 + 3 x 16 + 13 = 477 (ECCK)

In Equation 5, NCYC represents a longer PI row and PO column code length, and PCYC represents a larger parity number. As shown in Figs. 36A to 36E, the OSTT (Fig. 33D) is delayed from the ECC core circuit 1820 to the ECC controller (Fig. 33A) by the time required for the data output cycle (when the correction result is output). 1816). In this embodiment, the OSTT is delayed by 477 ECCK relative to the ESTT.

When error detection is executed and it is found that the detected error cannot be corrected, the ECC core circuit 1820 sends O.CODEERR (Fig. 34G) = L to the ECC controller 1816 when OSTT (Fig. 33E) becomes H. Outputs Next, the 8-bit data indicating the error pattern (the data to which the error data is exclusively logically added to obtain correction data) ECD [7: 0] (Fig. 34H) and the error position (the position (address) where the error occurs) are shown. Indicating 8-bit data) ECA [7: 0] (Fig. 34I) is output when ECOR (Fig. 34F) is H.

In the erase correction mode, the error position ECA [7: 0] data corresponding to the position where the error flag EFLG (FIG. 34C) is input is certainly output, but when the data at that position is correct, the error pattern ECD [7: 0] = 00.

If the error cannot be corrected, OSTT (FIG. 34E) is switched to H, O.CODEERR (FIG. 34G) is simultaneously switched to H, and ECOR (FIG. 34F) is prevented from going to H sequentially (this timing Not shown). In addition, the output of O.CODEERR (FIG. 34G) is latched until OSTT (FIG. 34E) changes back to H, while ECOR (FIG. 34F), ECD [7: 0] (FIG. 34H) and ECA [7: 0] (FIG. 34I) continues to output until OSTT (FIG. 34E) changes back to H. FIG.

35A to 35E, 36A to 36E, and 37A to 37E are timing diagrams showing control provided during ECC processing. The PI1-R, PO-R, and PI2-R shown in Figs. 35B, 36B, and 37B are respectively PI1 (first process of PI correction), PO (PO) of data EDT [7: 0] and EFLG (Fig. 34C). Correction) and PI2 (second processing of PI correction) sequences, and errors that may be corrected for this are the ECC core circuit 1820 from the RAM 1818 through the ECC controller 1816 circuit 136. Is sent to.

As shown in FIGS. 35A, 36A, and 37A, the MWRQ signal is fed 182 times to RAM 1818 to record data EFM + W (182 bytes of data) from EFM + demodulator 1804 in one PI row. As a result, the EFM + demodulated data in one PI row is recorded in the RAM 1818. While the data of one PI row is written, the data of the ECC block already written in the RAM 1818 is read and transmitted to the ECC core circuit 1820 through the ECC controller 1816. That is, while data of the PI row is written to the RAM 1818 at low speed, data of another PI row or PO column that has already been written is read three times at high speed. When data of the PI row is transmitted at the time of the sector, the subcode data ID and IED are also read. Writing and reading are performed in such a way that one operation is executed while the others are suspended.

For example, when PI1 correction of an ECC block is performed, data of one PI row is read during a timing period in which writing of data of one PI row is performed. Data in one PI row is read from RAM 1816 and sent to ECC core circuit 1820 via ECC controller 1816. In Figures 35B, 36B and 37B, although 208 ECCK was used to read the data PI1-R for PI1 correction, this number of ECCKs was applied to the length of the PO column, which is the longest data length, to transfer the data in the PI row. Only 182 ECCKs are used for data transmission.

38 is a flowchart illustrating a method used by RAM controller 1812 to write and read data to and from RAM 1818 to perform ECC correction. In step SP101, the RAM controller 1812 transmits data of one PI row from the RAM 1818 to the ECC core circuit 1820. In this embodiment, the PI code (parity) and PO code (parity) are added to each ECC block. Until the correction and rewriting of the first PI sequence of data from the first ECC block is complete, the PO sequence of data PO-R or the PI2 sequence of read data PI2-R cannot be transferred from the same ECC block. In this case, no data is transmitted at all during the subsequent 2 × 208 ECCK. If subcode data SUB exists after the data, it is sent to step SP102. Thus, the RAM controller 1812 sequentially transmits data of one PI row of the first ECC block and subcode data if necessary.

In step SP103, it is measured whether PI1-R data has been transmitted in row 208 of the first ECC block and accordingly whether transmission of all data of the 208 PI rows of the first ECC block has been completed. Otherwise, processing returns to step SP101, otherwise, processing proceeds to step SP104.

In step SP104, the RAM controller 1812 initiates transmission of the PO-R from the first ECC block during PI1-R and subsequent 182 MWRQ from the second ECC block following the first ECC block. That is, PI1-R is first transmitted from the second ECC block following the first ECC block during the subsequent 182 MWRQ, and then PO-R is transmitted twice from the first ECC block (two rows of PO data are transmitted). ).

These operations are each performed for 182 MWQR periods. Once the PO data of column 172 of the first ECC block is transmitted, the RAM controller 1812 obtains a positive result in step SP105 and follows the PI2 sequence of data PI2-R from the first ECC block (SP106). To transmit. The data PI2-R is transmitted at the same timing at which the data PO-R of the first ECC block shown in Fig. 36B is transmitted. At this point, the data PI1-R belongs to the next ECC block (second ECC block). PI2-R of the 208 PI rows of the first ECC block is transmitted in this manner, and when the processing of PI1-R, PO-R and PI2-R of the first ECC block is completed, the RAM controller 1812 performs the step ( A positive result is obtained in SP107, and the process returns to step SP101 to continue processing of the next ECC block.

The ECCX (FIG. 34A) is uniquely output to the ECC core circuit 1820 during data transfer from the RAM Jay 1812. Further, the correction result of the transmitted data is output as 477 clock ECCK after their input as described above. Therefore, the result of determining whether the data sequence contains an error (FIGS. 35C, 36C and 37C) is output when the following sequence except two is transmitted from these sequences (FIGS. 35B, 36B and 38B). This output is stored in the ERR FIFO circuit 3904 (FIG. 39) as described below.

When the data to be error-corrected is input from the RAM 1818 to the ECC controller 1816 as described above, the controller 1816 performs PI1 correction of the data of one PI row and outputs the result after 477 ECCK. (Figures 35C, 36C and 37C). The result is sent to the ERR FIFO 3904 used as a cold buffer in the ECC controller 1816 described below and stored temporarily. This data is further read out from the ERR FIFO 3904 and sent back to RAM 1818 as data for which error correction has been completed, and written to it as data PI1-W as shown in FIGS. 36D and 37D. The data on which the PO or PI2 correction is completed is also recorded in the RAM 1818 as data PO-W or PI2-W, respectively.

Data for which error correction has been completed is further read for each PI row using a period of 182 SDCK and output from the OCTL circuit 1822 as shown in FIGS. 35E, 36E, and 37E.

39 is provided with the same reference numerals as in FIG. 18, and is a block diagram showing a preferable flow of signals during error correction processing. The ECC controller 1816 disposes the memory device (ERR coefficient) 3902, the other memory device (ERR FIFO) 3904, the flag memory (flag) 3906, and the OR-circuit (EX-OR) circuit 3908. It is preferable to include.

The error memory device 3904 is a memory device having a first-in, first-out storage capacity. The flag memory 3906 is another memory device. The OR circuit 3908 is a device that logically sums the two quantities.

The demodulated data output from the EFM + demodulator 1804 is written to the ram 1818 under the control of the ram controller 1812. The sub data (ID and IED) stored at the start of each sector are read from RAM 1818 and sent to SBCD circuit 1810.

The SBCD circuit 1810 generates sector information SI as shown in FIG. Sector information SI is transmitted from SBCD circuit 1810 and recorded in RAM 1818.

The RAM controller 1812 is an error correction data EDT including 8-bit groups of data of one PI row recorded in the RAM 1818 as the ECC controller 1816 (the EDT data shown in FIG. 39 is directly connected to the ECC core circuit for convenience. Supplied to the ECC core circuit 1820. When data of one PI row is supplied to the ECC core circuit 1820, this circuit 1820 generates 8-bit error correction data ECD (FIG. 34H) and 8-bit error correction address ECA (FIG. 34I). Use a PI code. The error correction data ECD and error correction address ECA are transmitted and written from the ECC core circuit 1820 to the ERR FIFO 3904.

To substantially correct the error, the RAM controller 1812 reads the data EDT of the PI row and supplies it to the EX-OR circuit 3908. The EX-OR circuit 3908 is supplied with error correction data ECD and error correction address ECA from the ERR FIFO 3904. The EX-OR circuit 3908 corrects the error by logically adding together the error correction data ECD and the data EDT read from the RAM controller 1812 with bits specified by the error correction address ECA. The error corrected data is written back to RAM 1818 via RAM controller 1812.

In addition, the ECC core circuit 1820 generates an error correction result ER including 8-bit data as shown in FIG. 40 from the ECD and the ECA, and stores the result ER in the ERR COUNT 3902 for storing the result ER. Supply. The error correction result of one byte is recorded in the RAM 1818 through the RAM controller 1812 so as to correspond to the PI row as shown in FIG.

8-bit data of the error correction result ER shown in FIG. 40 represents the following information.

Bit 7: Uncorrectable error (0: correctable, 1: uncorrectable) (1 if an error in the series is found to be uncorrectable)

Bit 6: PO (0: PI, 1: PO) (indicates a series of PI rows or PO columns)

Bit 5: PI2 (0: PI1, 1: PI2) (indicates PI1 or PI2 series)

Bit 4: Correction number (value of the fifth bit (MSB) of the error correction number)

Bit 3: Correction number (fourth bit value of four bits representing error correction number)

Bit 2: Correction number (third bit value of four bits representing error correction number)

Bit 1: Number of corrections (second bit value of four bits representing error correction number)

Bit 0: Number of corrections (second bit value of four bits representing error correction number)

An error flag indicating whether data is corrected by the PI1 correction process (bit 7 of the PI1 flag and the error correction result ER) is sent to the ERR COUNT 3902 and the flag RAM 3906C as part of the error correction result ER. Stored.

This PI1 correction process is executed for the 208 PI rows shown in FIG.

The RAM controller 1812 reads 208 bytes of data in the first PO column from the RAM 1818 and supplies this data as an EDT to the ECC core circuit 1820 via the ECC controller 1816. The PI1 flag recorded in the flag RAM 3906 is also retrieved and supplied to the ECC core circuit 1820. The ECC core circuit 1820 uses pattern PO and PI flags that generate ECD and ECA for normal correction or erase correction. ECD and ECA are supplied to and stored therein from the ECC core circuit 1820 to the ERR FIFO 3904. The error correction result ER for this PO column generated by the ECC core circuit 1820 based on the ECD and ECA is also sent and stored in the ERR COUNT 3902. The PO flag corresponding to bit 7 of the error correction result ER may be written to the flag RAM 3906.

The data ECT of the PO column read from the RAM 1818 is supplied to the EX-OR circuit 3908. The EX-OR circuit 3908 is supplied with the ECD and the ECA from the ERR FIFO 3904. The EX-OR circuit 3908 corrects the error by adding exclusively logically the ECD and the EDT together to correspond to the bits of the address specified by the ECA. The error corrected data is written back to the RAM 1818.

The error correction result ER for this PO column is also read from ERR COUNT 3902 and written to RAM 1818. The error correction result ER for this PO column is substantially recorded at a position corresponding to 172 PI rows (starting from the top).

This PO correction is performed on the 172 PO column.

After PI1 and PO correction processing, when PI2 correction processing is performed, the data of the first PI row is read from RAM 1818 as an EDT and supplied to ECC core circuit 1820. The PO flag recorded in the flag RAM 3906 is also read and supplied to the ECC core circuit 1820. The ECC core circuit 1820 uses this PO flag and parity PI to generate ECD and ECA, and supplies both to the ERR FIFO 3904.

The data of the PI columns supplied to the ECD and ECA and EX-OR circuits 3908 and read from the RAM 1818 that are recorded in the ERR FIFO 3904 are added together logically exclusively to correct errors. The error corrected data is written to the RAM 1818 via the RAM controller 1812 by the EX-OR circuit 3908.

The ECC core circuit 1820 also generates error correction results (ER) from the ECD and ECA and supplies them to the ERR CPUNT 3902 to store them. The PI2 flag corresponding to bit 7 is also written to flag RAM 3906.

The error correction result ER in the PI2-row recorded in the ERR COUNT 3902 is read therefrom and written to the RAM 1818. The error correction result ER for the PI2 row is recorded at each position corresponding to each 208 PI row of the ECC block.

41A-41G are timing diagrams illustrating bus arbitration for accessing RAM 1818. FIG. In this figure, EFMREG (FIG. 41A) is a signal output to RAM controller 1812 by EFM + demodulator 1804 to request writing EFM + demodulated data to RAM 1818. OUTREQ (FIG. 41B) is a signal output to RAM controller 1812 by OCTL circuit 1822 that requests reading of ECC-processed data from RAM 1818. ECCREQ (FIG. 41C) provides RAM to correct data or obtain error-corrected data by sending data to ECC core circuit 1820, or to request SUB transfers (ID and IED) from SBCD circuit 1810. A signal output to the RAM controller 1812 by the ECC controller 1816 to access 1818.

The RAM controller 1812 presets priority levels for these signals and sequentially outputs an acknowledgment (ACK) signal to the RAM 1818 according to the priority levels when these requests are simultaneously required. EFMACK (FIG. 41D), OUTACK (FIG. 41E), and ECCACK (FIG. 41F) are recognition signals for EFMREQ, OUTREQ, and ECCREQ, respectively. The priority level is preferably set in the order of OUTREQ, EFMREQ, and ECCREQ. Therefore, the RAM controller 1812 outputs the ACK signal to the corresponding REQ signal in accordance with the priority level as shown in FIG. These signals are received in synchronization with C11M (FIG. 41G) used as the system clock.

As noted above, in accordance with the present invention, access to RAM 1818 is obtained in response to EFMREQ, ECCREQ or OUTREQ during each specified cycle. However, this cycle may vary depending on the type of deployment or ram 1818 or the speed of access.

42 shows the number of accesses to RAM 1818 required to perform PI1, PI2, and PO corrections of data of one ECC block. As shown, the number of accesses to RAM 1818 required to perform PI1, PO, and PI2 corrections is 214, 716 per ECC block, and the average value per main frame is 1,033. For example, the number of accesses to RAM 1818 during the recording of EFM + demodulated data is 182 per main frame, the ECC execution cycle length is 208 bytes (208 main frames), and 37,856 (= 182 x 208) accesses are blocked. Per party is required. The value is obtained by calculating the number of accesses required for each operation and adding all the obtained values together.

43A through 43F are timing diagrams showing timings for the output of the error correction result data ER from the RAM 1818 through the OCTL circuit 1822. In this figure, the time base for the position prior to 182 SDCK shown in FIGS. 35E, 36E and 37E is expanded. SDCK (FIG. 43A) specifies the clock signal used to output the ER as stream data. SINF (Fig. 43B) is a sector information strobe signal that becomes H at the time of a sector, and indicates that the transmitted data is sector information (SI).

ESTB (FIG. 43C) is an error correction result strobe signal as it becomes H indicating that the error correction result ER can be transmitted. In each PI row, one byte is assigned to each of the error correction results (ER) for PI1, PO, and PI2, so that the data of the result occupies a total of three bytes. Since this data is output in the order in which it is stored (Figure 21), the series with which the particular result is associated can be confirmed by checking bits 5 and 6 (Figure 40) of the data. For PI rows for which no PO correction results are output, the ESTB goes to L when those results are output.

DSTB (FIG. 43D) is a data strobe signal that is H when signal SD [7: 0] (FIG. 43E) is main data. These three signals SINF, ESTB, and DSTB are generated by the OCTL circuit 1822. The sector information SI and the error correction result ER are output just before the data in the direction of the PI row is output using 182 SDCK as shown in FIG. 43E.

OUTE (interpolation flag) (FIG. 43F) is an error flag for main data added to main data before output based on the PI and PO uncorrectable error flags stored in the flag RAM 3906. FIG.

OCTL circuit 1822 decodes bits 4 and 5 (FIG. 29) of sector information generated by SBCD circuit 1810.

0. It is measured whether data in a sector in which coding has been completed can be output. Bits 4 and 5 of the sector information indicate end and start sectors, respectively, as shown in FIG. Therefore, the OCTL circuit 1822 outputs sector data having bits 4 = 0 and bits 5 = 1 according to data in a particular sector (data to be output).

The OCTL circuit 1822 measures, for example, the presence of an error flag in the main data or whether the EDC result satisfies a state preset by the host CPU 1814, and if so, outputs decoded data. Otherwise, this circuit stops the output of the decode data and provides the information of the host CPU 1814 in error.

For example, the data output conditions are preferably as follows.

(1) Data can be specified for output.

(2) Not all errors can be detected from the ECC results.

(3) Not all error flags can be added to the main data.

When these output states are set, data satisfying these conditions is finally output. In addition, despite this state, the host CPU 1814 can forcibly suppress the data output.

The OCTL circuit 1822 sequentially outputs the main data, sector information SI, and error correction result ER in the order of the output sequence of the sector data shown in FIG.

The OCTL circuit 1822 of step SP111 first analyzes the result of the end sector detection stored in bit 4 of the sector information SI and the result of the start sector detection stored in bit 5. As a result, it is measured that data in which bit 4 is zero and bit 5 is one is output.

This processing method proceeds to step SP112 where it is determined whether decoded data can be output. If not, the processing method passes to step SP114 to stop the data output operation. The stop is for example done by terminating the data strobe signal by the OCTL circuit 1822. On the other hand, if the decoded data satisfies the output condition and is output, this processing method passes to step SP113.

In step SP113, the OCTL circuit 1822 performs each strobe signal of the output data and outputs, that is, the strobe signal SINF for the sector information SI (FIG. 43B), the error correction result ER (FIG. 43C). ) And a strobe signal (DSTB) for main data (FIG. 43D). The processing proceeds to step SP115. In step SP115, the OCTL circuit 1822 outputs data in the order of sector information SI, error correction result ER, and main data D0, D1, D2 .... Once all sector data is output, the output of sector data will be terminated.

In the above embodiment, the RAM 1818 from the RAM 1818 to the ECC core circuit 1820 during the data transfer period of 182 MWRQ (PI1-R, PO-R and PI2-R (35A to 35E, 36A to 36E and 37A to 37E)). The transmitted data is read from the RAM in accordance with the transmission clock ECCK. In this case, by stopping the transmission clock ECCK for a specific time between the data transfer periods PI1-R, PO-R and PL-R, the transfer of data PI1-R, PO-R and PI2-R It is suspended during this suspension period. That is, a period during which data is not transmitted may be formed between data (PI1-R, PO-R and PI2-R) series.

During this pause, the RAM controller 1812 transfers main data to the ECC controller 1816 via the ECC core circuit 1820 to use the RAM 1818 by using the error pattern and correction pattern of the ERR FIFO (error register). The error is corrected by reading the corresponding data from the data, executing an exclusive logic addition with the EX-OR circuit 3908, and writing the corrected data back into the RAM 1818 to execute ECC processing.

After the PI1 correction (PI1-W) is executed, the RAM controller 1812 is stored in the main frame numbered 0 and the sector address information (ID) stored in the RAM 1818 at sub-timing (FIGS. 35B, 36B, and 37B). The error detection code (IED) corresponding to the data is read, and these are transmitted to the SBCD circuit 1810. When the SBCD circuit 1810 detects the physical sector address ID, the circuit generates sector information SI according to the interpolation flag generation mode, start sector and end sector assigned by the host CPU 140, This information is written to RAM 1818 to correspond to a given PI row.

When writing EFM + demodulated data to RAM 1818, RAM controller 1812 is error-corrected based on OUTREQ (FIG. 41B) with sector information SI and error correction result ER from RAM 1818. The main data is read and this information is sent to the OCTL circuit 1822.

When the OCTL circuit 1822 measures whether decoded sector data can be output based on the sector information, the circuit determines the strobe signal SINF of the sector information SI and the strobe signal ESTB of the error correction result ER. ) And the strobe signal DSTB of the main data are outputted, respectively. Therefore, as shown in Figs. 43A to 43F, this data can be output in the order of sector information SI, error correction result ER, and main data D0, D1, D2 ....

As described above, as the error correction result ER including sector data, 3 bytes of PI, PO, and PI2 correction is output, the main data is output after the sector information SI. At this point, by analyzing bits 5 and 6 of the error correction result ER, whether the error correction result is PI or PO (bit 6) and PI1 or PI2 can be easily measured.

In addition, the main data D0 leading to the sector data includes sector address information ID that allows the physical address corresponding to the error correction result ER (the address on the optical disk 104) to be easily measured.

According to the arrangement, the sector correction (SI) and the error correction result (ER) are output immediately before outputting the main data of the decoded ECC block data, so that the error correction result (ER) and the optical disc 104 in the sector unit of the main data are output. The sector address information of the image can be obtained almost simultaneously with the output of the main data. Therefore, ECC error analysis corresponding to sector address information can be easily performed.

As described above, according to the present invention, the data decoding apparatus and method thereof decode corresponding to the address data of the coded data recorded on the recording medium when the coded data recorded on the recording medium is read and decoded therefrom. It can be realized in such a way that the decoding information of the data can be read. Thus, the state of the recording medium can be easily analyzed by considering decoding information corresponding to the address data.

Furthermore, in accordance with the present invention, in a data reproducing apparatus for reproducing a video signal and / or an audio signal, the data reproducing apparatus records the coded data recorded on the recording medium when the coded data is read from the recording medium and decoded. The decoding information of the decoded data corresponding to the address data of can be realized in a manner that can be read. Thus, the state of the recording medium can be easily analyzed by considering decoding information corresponding to the address data.

While embodiments of the present invention and variations thereof have been described in detail in the specification, the present invention is not limited to these exact embodiments and variations, and the scope of the invention as defined by the claims appended with other modifications and variations and It should be understood that it can be influenced by those skilled in the art without departing from the spirit.

Claims (24)

Error correction decoding means for error correction decoding the data to generate decoded data on a frame basis, and generating decoding information on a frame basis, the error correction encoded data, the decoded data and the decoding Memory means for storing information and control the memory means for storing the decoded data and the decoding information according to a frame unit, and with address data indicating a physical location of the error correction encoded data on the recording medium. An error correction encoded reproduced from a recording medium comprising memory control means, coupled to said error correction decoding means and said memory means, for retrieving said decoded data and said decoding information from said memory means while frame synchronization. Data on Data decoding apparatus for decoding correction. 2. The apparatus of claim 1, wherein the error correction encoded data is encoded according to a C1 / C2 convolutional Reed Solomon code. 3. The data decoding apparatus according to claim 2, wherein said memory control means stores said decoded data and said decoding information in said memory means corresponding to each error correction code series of said C1 / C2 convolutional resolmon code. A data decoding apparatus according to claim 1, wherein said recording medium is a disk-shaped storage medium, and said error correction encoded data is stored in a sector thereon. 5. The data decoding according to claim 4, wherein said memory control means retrieves said decoded data and said decoding information from said memory means while being synchronized with a sector address of said error correction encoded data stored on said disk shaped storage medium. Device. The method of claim 1, wherein the error correction encoded data encodes a frame of user data according to an error correction inner code in a column direction of the frame to generate a column encoded frame, and corrects an error in a row direction of the frame. And a data decoding device generated by encoding the column encoded frame according to an outer code. 7. The apparatus according to claim 6, wherein the error correction decoding means decodes the error correction encoded data by blocks in units of columns, and the error correction decoding means decodes the error correction encoded data by blocks in units of rows. And the error correction decoding means decodes the error correction encoded data in the column unit again. 8. A data decoding apparatus according to claim 7, wherein said error correction decoding means includes error correction means for error correcting said error correction encoded data as a function of error location and error pattern. Error correction decoding the error correction encoded data to generate decoded data on a frame basis, generating decoding information on a frame basis, storing the error correction encoded data, the decoded data, and the decoding information. Storing the decoded data and the decoding information in a memory corresponding to a frame unit, and decoding from the memory while frame synchronization with address data indicating a physical location of the error correction encoded data on the recording medium. Retrieving the corrected data and the decoding information, and error correcting decoding the error correction encoded data reproduced from the recording medium. 10. The method of claim 9, wherein the error correction encoded data is encoded according to a C1 / C2 convolutional Reed Solomon code. 11. The method of claim 10, further comprising storing the decoded data and the decoding information corresponding to each error correction code series of the C1 / C2 convolutional Reed Solomon code. 10. The data decoding method according to claim 9, wherein said recording medium is a disk-shaped storage medium, on which said error correction encoded data is stored in a sector. 13. The data decoding method of claim 12, further comprising retrieving the decoded data and the decoding information while being synchronized with the sector address of the error correction encoded data stored on the disk shaped storage medium. 10. The method of claim 9, wherein the error correction encoded data encodes a frame of user data according to an error correction inner code in a column direction of the frame to generate a column encoded frame, and error correction in a row direction of the frame. And a data decoding method generated by encoding the column encoded frame according to an outer code. 15. The method of claim 14, wherein the error correcting decoding comprises: decoding the error corrected encoded data by the block in columns, decoding the error corrected encoded data by the block in rows, again. Decoding the error correction encoded data in units of columns. 16. The data decoding method of claim 15, wherein the error correction decoding step comprises error correcting the error correction encoded data as a function of error location and error pattern. Reproducing means for reproducing the error corrected encoded data from the recording medium, error correction decoding the error correction encoded data to generate decoded data on a frame basis, and error correction decoding for generating decoding information on a frame basis Means for storing said decoded data and said decoding information in accordance with means, memory means for storing said error correction encoded data, said decoded data and said decoding information, and said recording means for storing said decoded data and said decoding information; Coupled to the error correction decoding means and the memory means for retrieving the decoded data and the decoding information from the memory means while frame synchronization with address data indicating a physical location of the error correction encoded data on a medium, Memory control Means for reproducing error correction encoded data from a recording medium. 18. The apparatus of claim 17, wherein the error correction encoded data is encoded according to a C1 / C2 convolutional Reed Solomon code. 19. The data reproducing apparatus as set forth in claim 18, wherein said memory control means stores said decoded data and said decoding information in said memory means corresponding to each error correction code series of said C1 / C2 convolutional Reed Solomon code. 18. The data reproducing apparatus according to claim 17, wherein said recording medium is a disk-shaped storage medium, and said error correction encoded data is stored in a sector thereon. 21. The data reproduction according to claim 20, wherein said memory control means retrieves said decoded data and said decoding information from said memory means while being synchronized with a sector address of said error correction encoded data stored on said disk shaped storage medium. Device. 18. The method of claim 17, wherein the frame of user data is encoded according to an error correction inner code in the column direction of the frame such that the raw error correction encoded data generates a column encoded frame, and the error correction in the row direction of the frame. And a data reproduction device generated by encoding the column encoded frame according to an outer code. 23. The apparatus of claim 22, wherein the error correction decoding means decodes the error correction encoded data by blocks in units of columns, and the error correction decoding means decodes the error correction encoded data by blocks in units of rows. And the error correction decoding means decodes the error correction encoded data in the column unit again. A data reproducing apparatus as set forth in claim 23, wherein said error correction decoding means includes error correction means for error correcting the error correction encoded data as a function of error position and error pattern.