JPH09265730A - Data reproducing device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time from reading out of a disk until outputting decoded data without increasing a circuit scale or a clock rate. SOLUTION: When demodulated reproduced data have been written in a ring buffer memory 5 and one ECC block of data have been written in the ring buffer memory 5, the one block of data are transferred from the ring buffer memory 5 to an error correction circuit 7 to perform an error correction processing of PI series, and also when one ECC block of data are written in an error correction memory 6 to perform an error correction processing of PO series at the error correction circuit 7, and further, when an error correction processing of the PI series has been performed and completed, the data are transferred from the error correction memory 7 to the ring buffer memory 5, which 5 is made to output the data at a required transfer rate. Since the data writing in the error correction memory 7 from the ring buffer memory 5 and the error correction processing of PI series at the error correction circuit 7 are performed simultaneously, the data processing speed is shorten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a DVD.
The present invention relates to a data reproducing apparatus and a data reproducing method suitable for use in performing variable rate reproduction with (Digital Video Disc).

[0002]

2. Description of the Related Art An optical disk (DVD) capable of recording a large amount of data by using a laser beam having a short wavelength and an objective lens having a large numerical aperture has been developed. The DVD includes, for example, MPEG (Moving Pocture).
It is used to record digital video signals compressed by the Expert Group 2 standard. The DVD is also expected as a data recording medium for recording a large amount of data.

As a reproducing apparatus for reproducing recorded data of a DVD, there has been proposed a reproducing apparatus adapted to a variable rate. Such a variable-rate compatible playback device is provided with a ring buffer memory. The ring buffer memory is basically configured as shown in FIG.

As shown in FIG. 21, the ring buffer memory has an address configuration such that when it reaches the end address, it returns to the head address. That is, as shown in FIG. 21, when the address is “0” to “11”, the address is advanced to “0”, “1”, “2”, ... Returning to the address "0", the process proceeds to "1", "2", ... Again. Such a ring buffer memory is specifically constituted by a FIFO.

WP is a write pointer, and this write pointer WP indicates an address at which writing has been completed. EP is an ECC end pointer, and this ECC end pointer indicates an address at which the error correction processing has been completed. RP is a read pointer, and the read pointer RP indicates the address at which the reading is completed.
In the case shown in the figure, since the write pointer WP is located at the address "11", the data is written up to the address "11". Since the ECC end pointer EP is located at the address "9", the error correction process is completed up to the address "9". Read pointer R
Since P is located at the address "2", the address "2"
Writing has been completed up to that point. Therefore, the error correction processing is completed at the addresses “3” to “9”, the readable data is located, and the addresses “0” to “2” are
The data that has already been read and is no longer needed is located, and the newly written data is located at addresses "10" and "11".

In the ring buffer memory described above, it is necessary that the read pointer RP does not overtake the ECC end pointer EP. In addition, the ECC end pointer EP
Must not overtake the write pointer WP. The write pointer WP is the read pointer RP.
When it catches up with, the writing of demodulated data is temporarily stopped (overflow control).

22 to 24 can be considered as a configuration of the data reproducing apparatus provided with such a ring buffer memory and adapted to the variable rate.

In FIG. 22, from the demodulation circuit 101,
Demodulated data of a reproduction signal of the optical disk is output. This demodulated data is first stored in the ring buffer memory 102 (access e). Ring buffer memory 102
When one ECC block worth of data is stored in
As shown in (1), the data stored in the ring buffer memory 102 is transferred to an error correction processing circuit 103, where an error correction process is performed. First, the error correction process
The I series processing is performed (access f1), the PO series processing is performed (access f2), and the PI series processing is performed again (access f3). When the error correction processing for the PI series, the PO series, and the PI series again is completed, data transfer becomes possible. In response to the output request, as shown in FIG. 24, the data for which the error correction processing has been completed is read from the ring buffer memory 102, and the read data is descrambled and the error detection circuit 104.
, And transferred to the external host computer 105 via the interface 106 (access g).

[0009]

In a disk playback apparatus compatible with a variable rate, it is conceivable that a connection with a host computer is established by, for example, an ATAPI interface, and data is transferred at a transfer rate of the ATAPI interface (16.6 MB / s). Have been. Further, it is considered that the disc is read at a double speed as usual.

However, in the above-described conventional data reproducing apparatus, the ring buffer memory 102 performs variable rate control,
Since it is used for error correction encoding processing, many accesses to the ring buffer memory 102 occur,
It is difficult to meet such demands.

That is, in the configuration described above, the access (access e) for writing the data of the demodulation circuit 101 and the access (access f1) for error correction processing of the PI series are performed on the ring buffer memory 102. P
Access for access to O-series error correction (access f
2), an access (access f3) for error correction processing of the PI sequence again, and an access (access g) for outputting data in response to an output request occur. FIG. 25 shows the timing of these accesses. As described above, since a large number of accesses are made to the ring buffer memory 102, it is difficult to double the read speed of the disk and make the output rate correspond to the rate of the ATAPI interface.

By increasing the data width of the ring buffer memory or increasing the frequency of the operation clock,
Although it is conceivable to meet such a demand, increasing the data width of the buffer memory or increasing the frequency of the operation clock leads to an increase in circuit size and cost.

Therefore, as shown in FIGS. 26 to 29, it is conceivable to provide a memory 113 for error correction processing separately from the ring buffer memory 112. In FIG. 26, demodulation circuit 111 outputs demodulated data of a reproduction signal of an optical disc. The demodulated data for one ECC block is first stored in the error correction memory 113 (access H). Then, as shown in FIG.
The error correction circuit 114 performs the PI series processing (access I1), the PO series processing (access I2), and the PI series processing again (access I).
3). When the error correction processing of the PI series, the PO series, and the PI series again is completed, as shown in FIG. 28, the data of the memory 113 for the error correction processing is read (access J), and the descrambling and error detection circuit 115. Descrambled in. Then, this data is transferred to the ring buffer memory 112 (access h). In response to the output request, as shown in FIG. 29, the data for which the error correction processing has been completed is read from the ring buffer memory 112 and transferred to the external host computer 116 via the interface 117 (access i). .

As described above, when the error correction memory 113 is provided separately from the ring buffer 112, it is not necessary to access the ring buffer memory 112 at the time of error correction processing. However, in this example, since the input data access (access h) to the ring buffer memory 112 occurs after the error correction processing is completed, the timing becomes as shown in FIG. , It is difficult to meet the demand that the output be an ATAPI interface.

Therefore, as shown in FIGS. 31 to 34, two memories, a memory 123 and a memory 124, are prepared for error correction, and while one memory writes demodulated data, the other memory writes an error. It is conceivable to perform correction processing. In FIG. 31, demodulation circuit 121 outputs demodulated data of a reproduction signal of an optical disc. The demodulated data for one ECC block is first stored in the error correction memory 123 (access K). Then, as shown in FIG. 32, the error correction circuit 1
25, the processing of the PI series is performed (access L
1), PO series processing is performed (access L2), and PI series processing is performed again (access L3). At this time, at the same time, the demodulation data for the next one ECC block from the demodulation circuit 121 is transferred to the other memory 1 for error correction processing.
24 (access K). When the error correction processing of the PI series, the PO series, and the PI series again is completed, as shown in FIG. 33, the data in the memory 123 for the error correction processing is read (access M), and the descramble and error detection circuit 116. Descrambled in. Then, this data is transferred to the ring buffer memory 122 (access k). In response to the output request, as shown in FIG. 34, the data for which the error correction processing has been completed is read from the ring buffer memory 122, and is transmitted via the interface 128 to the external host computer 1.
27 (access l).

In this way, the demodulated data is written (access K) and the error correction process (accesses L1 and L) is performed.
2 and L3) occur simultaneously, the timing becomes as shown in FIG. 35, and the time from the reading of the disk to the output of the error correction processing data can be shortened. As a result, it is possible to meet the demand that the disc read speed is doubled and the output is performed by the ATAPI interface.

However, in such a configuration, two memories 123 and 12 are used as memories for error correction processing.
4B is required, which causes a problem that the circuit scale increases.

Therefore, an object of the present invention is to provide a data reproducing apparatus and a data reproducing method capable of shortening the time from the reading of the disk to the output of the decoded data without increasing the circuit scale or increasing the clock speed. To provide.

[0019]

According to the present invention, there is provided reproducing means for reproducing a recording medium on which digital data is recorded, a ring buffer memory for variable rate control, and error correction processing for data reproduced from the recording medium. An error correction unit for performing error correction and an error correction memory for storing data of an error correction block for performing error correction by the error correction unit are provided, and reproduction data reproduced from a recording medium is written in a ring buffer memory to generate a ring buffer. When the data for the error correction block is written in the memory, the data for the error correction block is sent from the ring buffer memory to the error correction memory and the error correction means, and the data for the error correction block is sent to the error correction memory. At the same time as writing, the first error correction means
Error correction processing is performed in the direction of, and when data for an error correction block is written in the error correction memory, error correction processing is performed in the second direction by the error correction means, and
When the error correction processing is completed in the second direction, the error-corrected data is transferred from the error correction memory to the ring buffer memory, and the error-corrected data transferred to the ring buffer memory is required. The data reproducing device is designed to output at the transfer rate.

According to the present invention, in a data reproducing method for reproducing at a variable rate from a recording medium on which digital data is recorded, reproduced data reproduced from the recording medium is
When the step of writing to the ring buffer memory and the data for the error correction block is written in the ring buffer memory, the data for the error correction block is sent from the ring buffer memory to the error correction memory and to the error correction means for error correction. The data for the error correction block is written in the memory for error correction, and at the same time, the step for performing the error correction processing in the first direction by the error correction means, and the data for the error correction block is written in the memory for error correction. Then, the step of performing error correction processing in the second direction by the error correction means, and when the error correction processing is completed in the first and second directions, the error-corrected data is transferred from the error correction memory to the ring buffer. After the step of transferring to the memory and after the error correction processing transferred to the ring buffer memory A data reproducing method comprising the step of outputting at a transfer rate that is required for over data.

When the demodulated reproduction data is written in the ring buffer memory and one ECC block worth of data is written in the ring buffer memory, one ECC block worth of data is sent from the ring buffer memory to the error correction circuit and the PI series error correction process is performed. At the same time, the data for one ECC block is written in the memory for error correction, and then the error correction circuit performs error correction processing of the PO series by the data stored in the memory for error correction,
Furthermore, PI series error correction processing is performed, and when the error correction processing is completed, data is transferred from the error correction memory to the ring buffer memory, and data is output from the ring buffer memory at the required transfer rate. I have to. Writing data from the ring buffer memory to the memory for error correction and PI in the error correction circuit
Since the error correction processing of the series occurs at the same time, the data processing speed is shortened, for example, reading the disk at double speed,
The ATAPI interface can transfer data at 16.6 Mbit / s.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 is an optical disc. As the optical disc 1, an optical disc (DVD) capable of recording a large amount of data by using a laser beam having a short wavelength and an objective lens having a large numerical aperture is used.

FIG. 2 shows the structure of one sector when recording / reproducing data on the optical disc 1. As shown in FIG. 2, one sector consists of (12 rows × 172 bytes) of data. At the beginning of one sector, a 4-byte ID indicating a physical address and a 2-byte parity IEC for this ID are provided. Then, 2048 bytes after the 6-byte reserve data RSV are used as a main data area. At the end of one sector, a 4-byte error detection code is added.

As shown in FIG. 3, data (1
2 rows x 172 bytes) are collected for 16 sectors and (19
Two-dimensionally arranged in 2 rows × 172 bytes) to form an ECC block. For data of (192 rows × 172 bytes), the parity P of the inner code of 10 bytes in the row direction
I ((182,172,11) Reed-Solomon code)
Is added, and 16 columns of outer code parity PO in the column direction are added.
((208,192,17) Reed-Solomon code) is added.

The error-correction-coded data is interleaved so that 16 rows of parity PO are arranged in each data sector. Then, a sync of a predetermined pattern is added, and 8-16 modulation (called EFM plus) is performed and recorded. Therefore, the physical configuration of one sector of data recorded on the disc is as shown in FIG. Since it is 8-16 modulated, 1456
The bits correspond to 91 bytes. In FIG. 4, S
Y0, SY1, SY2, ... Denote sync patterns.

In FIG. 1, a pickup 2 is provided for the optical disc 1. The pickup 2 is movable by a servo circuit 13 in the radial direction of the disk. The pickup 2 reproduces a recording signal of the optical disc 1. The reproduced signal from the optical pickup 2 is
It is supplied to the demodulation circuit 3. The demodulation circuit 3 performs demodulation processing by EFM plus.

The output of the demodulation circuit 3 is supplied to the sector detection circuit 4. The sector is detected by detecting the sync patterns SY0, SY1, SY2, ... In the reproduced data by the sector detection circuit 4. The output of the sector detection circuit 4 is supplied to the memory controller 10.

The optical disc 1 is reproduced at double speed, for example. A ring buffer memory 5 is provided to enable variable rate reproduction. The ring buffer memory 5 is composed of, for example, a FIFO. The ring buffer memory 5 is controlled by the buffer controller 10.

In the disc reproducing apparatus to which the present invention is applied, as shown in FIG. 5, the output of the demodulation circuit 3 is first written in the ring buffer memory 5 (access a).
When one ECC block worth of data is stored in the ring buffer memory 5, next, as shown in FIG. 6, one ECC is transferred from the ring buffer memory 5 to the error correction memory 6.
The demodulation data for the block is transferred (access c), and at the same time, the error correction circuit 7 performs error correction processing of the PI series (access B1). Then, as shown in FIG. 7, the PO series error correction process is performed using the data stored in the error correction memory 6 (access B
2) Further, PI series error correction processing is performed again (access B3).

When the error correction processing is completed, as shown in FIG. 8, data is read from the error correction memory 6 (access C), and this data is passed through the descramble and error detection circuit 8 to the ring buffer. It is written in the memory 5 (access d). The scramble process is
This is the exclusive OR of the scramble data and the main data generated with the value selected by the lower 7 to 4 bits of the physical address as an initial value.

The data read from the error correction memory 6 and stored in the ring buffer memory 5 can be output because the error correction processing has been completed. FIG.
As shown in, data is read from the ring buffer memory 5 by the output request (access b).

When the write pointer of the ring buffer memory 5 catches up with the read pointer, the ring buffer memory 5 overflows. Therefore, in FIG. 1, the system controller 11 monitors the read pointer WP and the write pointer RP in the buffer controller 10. The write pointer WP and the read pointer RP calculate the amount of data currently stored in the ring buffer memory 5. When the amount of data exceeds a preset storage amount, it is determined that the ring buffer memory 5 may overflow, and a track jump command is sent to the track jump control circuit 12 (overflow processing). The output of the track jump control circuit 12 is supplied to the servo circuit 13, and the track jump control is performed as needed.

In FIG. 1, an optical disk reproducing apparatus to which the present invention is applied has an ATAPI interface 15
Is provided, and this ATAPI interface 1
The data can be transferred to the host computer 16 via the server 5. In addition, a video decoder 17 and an audio decoder 18 are provided, and the optical disc 1 has M
When a video signal compressed by PEG2 is recorded, this video signal can be reproduced.

When data is transferred to the host computer 16 via the ATAPI interface 15, the request signal from the host computer 16 causes the data to be read from the ring buffer memory 5. This data is sent to the host computer 16 via the ATAPI interface 15.

When reproducing a video signal compressed and recorded in MPEG2 on the optical disc 1, a request signal is generated based on the remaining buffer capacity of the video buffer 20 and the audio buffer 21, and the ring signal is generated by this request signal. Data is read from the buffer memory 5. The output of the ring buffer memory 5 is supplied to the demultiplexer 19. The demultiplexer 19 separates video data and audio data according to the information in the packet header.

The video data is supplied to the video buffer video decoder 17 via the video buffer 20. The audio data is supplied to the audio decoder 18 via the audio buffer 21. The video data is decoded by the video decoder 17 based on, for example, MPEG2. The decoded video signal is output from the output terminal 22. The audio data is decoded by the audio decoder 18. The decoded audio data is output from the output terminal 23.

As described above, in the data reproducing apparatus to which the present invention is applied, the demodulated reproduced data is written in the ring buffer memory 5 and 1EC is stored in the ring buffer memory 5.
When C blocks worth of data is written, 1 ECC blocks worth of data is sent from the ring buffer memory 5 to the error correction circuit 7 to perform PI series error correction processing, and at the same time, 1 ECC blocks worth of data is put into the error correction memory 6. Writing, and then the error correction circuit 7 performs error correction processing of the PO series by the data stored in the memory 6 for error correction, further performs error correction processing of the PI series, and when the error correction processing is completed, the error Data is transferred from the correction memory 6 to the ring buffer memory 5, and the ring buffer memory 5 is transferred at the required transfer rate.
I am trying to output the data from.

Therefore, in the ring buffer memory 5, pointers are arranged as shown in FIG.
~ As shown in FIG. 13, the pointer moves.

That is, the address of the ring buffer memory 5 is constructed such that the end address follows the start address and returns to the start address when the end address is reached. WP is a write pointer, and the write pointer WP indicates an address where writing has been completed. EP is an ECC end pointer, and this ECC end pointer indicates an address at which the error correction processing has been completed. RP is a read pointer, and the read pointer RP indicates the address at which the reading is completed.

Data before error correction is written up to the write pointer WP. Then, the data before the error correction is subjected to the error correction processing in the error correction circuit 7, is sent from the error correction memory 6 to the ring buffer memory 5, and up to the error pointer EP,
It is data that can be output after error correction processing has been completed. Then, the reading is completed up to the read pointer RP.

As shown in FIG. 11, first, the demodulated data is written in the ring buffer memory 5. When the writing of the demodulated data is completed, the write pointer WP is advanced by one ECC block, the data is transferred from the ring buffer memory 5 to the memory 6 for error correction, the data is transferred to the error correction circuit 7, and the PI series, PO series,
Error correction processing of the PI series is performed. When the error correction processing is completed, descrambling and error detection processing is executed, the error-corrected data is transferred from the error correction memory 6 to the ring buffer memory 5, and when the data transfer of the block is completed, The error pointer EP is advanced by one block.

As shown in FIG. 12, the data after the error correction processing becomes outputable data. When there is an output request signal, data is read from the ring buffer memory 5,
The read pointer RP is advanced. At this time, it is determined from the read pointer RP and the error pointer EP whether there is outputable data. That is, the relationship between the error pointer EP and the read pointer RP is determined. The relationship between the error pointer EP and the read pointer RP is E
If P> RP, there is data that can be output, so the data is output to the subsequent stage and the read pointer RP is advanced.
If EP = RP, there is no outputable data, and no data is output.

As shown in FIG. 13, when there is no data output request from the subsequent circuit, the write pointer WP advances, but the read pointer RP is stopped, so the write pointer WP becomes the read pointer RP. catch up. When the write pointer WP catches up with the read pointer RP and EP = RP, the write operation is temporarily stopped. Then, when a track jump is required, the track jump is performed. (Overflow control). After that, when the read pointer RP advances and an input possible area is generated, the demodulated data can be written.

FIG. 14 shows the structure of an error correction circuit used in a disc reproducing apparatus to which the present invention is applied.

In FIG. 14, the error correction circuit 7 is composed of an error correction integrated circuit 51, an error buffer 52, a flag memory 53, and an error counter 54. The error correction integrated circuit 51 is an integrated circuit that performs a Reed-Solomon code error correction process. The data EDT [7: 0] and the flag EFLG for erasure correction from the flag memory 53 are input to the error correction integrated circuit 51 via the RAM interface 56. In the error correction integrated circuit 51, parameters such as a code length and a parity number can be set programmably.

The error buffer 52 is composed of a FIFO. As a result of the error correction processing in the error correction integrated circuit 51, the error pattern is stored in the error buffer 52. The output of the error buffer 52 is supplied to the EX-OR circuit 55. The EX-OR circuit 55 includes R
Data from the error correction memory 6 is supplied via the AM interface 56. In the case of the error pattern, in order to correct the error, the data from the error buffer 52 and the data from the memory 6 for error correction are exclusive-ORed at the timing of the position of the error to generate the error. Is corrected and returned to the memory 6 for error correction again.

The flag memory 53 stores a pointer of an error flag indicating an error position. The error flag is used when performing erasure correction.

The error counter 54 counts the number of errors as a result of the error correction processing in the error correction integrated circuit 51.

FIG. 15 and FIG. 16 are timing charts showing the operation of this error correction circuit. In FIG. 15, ESTT
Is a control signal indicating the beginning of the code, ECDE is a control signal indicating the end of the code, and ECYE is a control signal indicating the end of the code cycle. As shown in FIG. 15, the correction result is output in the cycle represented by the following equation. Throughput = 2 × NCYC + 3 × PCYC + 13 Note that NCYC represents the longer code length and PCYC represents the longer parity number.

As shown in FIG. 16, the error correction integrated circuit 51 operates with a single clock ECCK. In FIG. 16, OSTT is a delayed output of the control signal ESTT, and is output 477 clocks (ECCK clock) after the control signal ESTT in a certain code sequence. Then, if an error is detected and the error can be corrected, ECOD = at the same time as OSTT = 1.
0, and then at the position of ECOR = 1, the error pattern ECD [7: 0] and the error position ECA [7:
0] is output.

In the erasure correction mode, the error pattern ECD [7: 0] and the error position EC
A [7: 0] data is always output, but if the data at that position is correct, the error pattern is ECD [7:].
0] = 00 (H).

FIG. 17 shows the timing of execution control of error correction processing in the PI series, and FIG. 18 shows the timing of execution control of error correction processing in the PO series. Here, PI-R and PO-R are the transfer timings of the input data EDT [7: 0] of each series and the error flag. During the data transfer of this series, the timing for performing the error correction operation is entered. The clock ECCK is output only during the data transfer period.

As shown in FIG. 17, for example, the result of whether or not there is an error in the data transferred by PI-R is 44.
Since it is output after 5 (ECCK clock), it will be output after the data of that series is transferred and while the two series of data are being transferred. The resulting output is temporarily written to the error buffer 52. Similarly, PO
-R is also output after transferring the data of the series and while transferring the two series data.

Error correction result, error pattern ECD
[7: 0] and error position ECA [7: 0]
Data written to the error buffer 51 is read out from the error correction memory 6 at the error correction timing, and the exclusive OR with the error pattern read from the buffer 52 is obtained. It is written back to the memory 6 of.

Here, since the data having the error pattern ECD [7: 0] = 00 (H) at the time of erasure correction is actually correct, it is meaningless even if the correction operation is performed. Therefore, writing to the error buffer 52 is performed. Not performed.

As described above, in the data reproducing apparatus to which the present invention is applied, the demodulated reproduced data is written in the ring buffer memory 5 and 1E is written in the ring buffer memory 5.
When the data for the CC block is written, the data for one ECC block is sent from the ring buffer memory 5 to the error correction circuit 7 to perform PI series error correction processing, and at the same time, the data for one ECC block is stored in the memory 6 for error correction. Writing, and then the error correction circuit 7 performs error correction processing of the PO series by the data stored in the memory 6 for error correction, further performs error correction processing of the PI series, and when the error correction processing is completed, the error Data is transferred from the correction memory 6 to the ring buffer memory 5, and the ring buffer memory 5 is transferred at the required transfer rate.
I am trying to output the data from. Since the data writing from the ring buffer memory 5 to the error correction memory 6 and the PI series error correction processing in the error correction circuit 7 occur at the same time, the data processing speed is shortened, for example, the disk is read at double speed. , ATAPI interface makes it possible to transfer data at 16.6 Mbit / s. This will be verified below.

As shown in FIGS. 5 to 9, in the disc reproducing apparatus to which the present invention is applied, access to the ring buffer memory 5 and access to the error correction memory 6 occur. FIG. 19 shows the timing of these accesses.

For access to the ring buffer memory 5, the ring buffer memory 5 output from the demodulation circuit 3 is used.
Write to (access a), ring buffer memory 5
From the ring buffer memory 5 to the error correction memory 6 (access c), and writing of the output of the descramble and error detection circuit 8 to the ring buffer memory 5 (access d). )
There is.

Further, as the access to the error correction memory 6, PI series error correction processing (access B1), PO series error correction processing (access B2),
There is another PI-series error correction process (access B3), and data descrambled by the descramble circuit 8 is transferred to the ring buffer memory 5 (access C).

The rate of demodulated data when the disc is reproduced at 1 × speed is 26.16 Mbit / s. AT
The transfer rate required by the API interface is 1
It is 6.6 MByte / s.

The ring buffer memory 5 has a word access (16 bits), and the number of n word page access cycles is 3 + 2 × n cycles.

The memory 6 for error correction is byte-accessed (8 bits), and the number of n-byte page access cycles is 3 + 2 × n cycles. The frequency of the master clock is 40 MHz.

First, the disc is reproduced at double speed, and ATA is reproduced.
This indicates that the ring buffer memory 5 can be accessed when transferred by the PI interface.

As shown in FIG. 4, the number of bits of one sync frame is 1456 bits, and a sync pattern of 32 bits is added to this. Therefore, the total number of bits in one sync frame is 1456 + 32 = 1488 bits.

The rate of demodulated data when the disc is reproduced at 1 × speed is 26.16 Mbit / s. Therefore, the sync frame frequency is as follows: sync frame frequency = 26.16 MHz / (32 + 1456) = 26.16 MHz / 1488 = 17.58065 KHz.

The master clock is 40 MHz, and one clock of this master clock is one cycle. The sync frame frequency is 17.58065 KHz
And 2 sync frames are PI series (182 bytes)
Therefore, when one frame of the PI sequence is converted into the number of cycles, it becomes 2 × 40 MHz / 17.58065 KHz = 4550 cycles.

On the other hand, when outputting the data from the ring buffer memory 5, if the 12-byte data is output in 26 cycles, the ATAPI interface transfer rate of 16.6 MByte / s can be satisfied.

That is, 12 bytes of data are converted to 40 MH
When it takes 26 cycles to transfer with the z clock, (12 bytes / 26 cycles) × 40 MHz = 18.4.
It becomes 6 Mbytes / s (> 16.6 Mbytes / s), which can satisfy the transfer rate of 16.6 Mbytes / s in the ATAPI interface.

In the ring buffer memory 5, the number of n word page access cycles is (3 + 2 × n) cycles. For example, when 12 bytes of data are accessed to the ring buffer memory 5, since 12 bytes = 6 word pages, (n = 6), and the number of access cycles of the ring buffer memory 5 is 3 + 2 × 6 = 15 cycles. Become. Therefore, the number of cycles when accessing 12-byte data with the buffer memory 5 is 15 cycles.

As described above, if the data is transferred from the ring buffer memory 5 at such a pace that 12-byte data is output in 26 cycles, the transfer rate of the ATAPI interface can be satisfied. The number of cycles for accessing 12 bytes of data is 15 silles. From this, as shown in FIG. 20, 11 of 26 cycles can be assigned to another job.

Assuming that a request for output is always generated, the access to the ring buffer memory 5 is 4550 cycles per frame × 128 bytes / 26 cycles = 21.
Although it is 00 bytes, in reality data will be output to the host at 16.6 Mbytes / s, so access to the ring buffer memory 5 for an output request is 16.67 Mbytes per frame. / S × 4550 / 40MHz = 18
It is enough if you can access 96 bytes. As a result, the 26 cycles including the output and other jobs are 26 × 1896/2100 = 23.47, which can be converted to about 23.5 cycles.

As mentioned above, 11 out of 26 cycles
The cycle can be assigned to another job. 1
Since the number of frames is 4450, the number of cycles that can be assigned to another job during one frame is 4550 × (11/26) = 1925. Data is transferred from the ring buffer memory 5 to the error correction memory 6 and the error correction circuit 7 in the cycle thus allocated.

As shown in FIG. 3, the PI sequence is 172
It consists of bytes of data and 10 bytes of parity. P
At the time of I decoding, if this is accessed every 8 bytes / 11 cycles, 182/8 = 22.75, so 23 times × 11 cycles × 3 = 759 cycles.

Since PI decoding is executed when the data from the buffer memory 5 is transferred to the memory 7 for error correction, (5 + 5 + 1) × 5 = 55 cycles are required for writing / reading the correction operation and correcting the correction result. It is not used as a dummy cycle for writing.

The refresh cycle is about 16
Assuming a CAS-before-RAS refresh cycle of once per microsecond, 5 * 8 = 40 cycles are inserted into the ECC transfer of each frame, then 759 + 55 + 40 = 854. The number of cycles assigned to other jobs is 1
Since it is 925 cycles, it becomes 1925 / (759 + 55 + 40) = 2.25, and the double speed access to the ring buffer memory 5 becomes possible.

Next, it will be explained that double speed is possible by accessing the memory 6 for error correction.

The memory 6 for error correction is byte-accessed, and the number of cycles required for n-byte access is
(3 + 2 × n) cycles.

182 bytes of PI series are 8 bytes / 1
182/8 = 2 as page access every 9 cycles
At 2.75, it is transferred every 8 bytes / 26, so
Converting 8 bytes / 26 cycles to 8 bytes / 23.5 cycles gives 23 times × 23.5 cycles = 540.5 cycles (1).

208 bytes of a PO series frame is 1
2 bytes for page access every 6 bytes / 35 cycles
Since 08/16 = 13, 13 times × 35 cycles = 455 cycles (2).

The 182 bytes of the frame of the second PI series are 182/16 = 11.375 as page access every 16 bytes / 35 cycles, so that 12 times × 35 = 420 cycles (3).

Since an output frame is 182 bytes and this is a page access for every 8 bytes / 19 cycles, 182/8 = 22.75 can be transferred every 8 bytes / 26 cycles, so 8 bytes / 26 cycles are required. Converting to 8 bytes / 24 cycles, 23 times × 23.5 cycles = 540.5 cycles (4).

In addition, 5 cycles × 13372 = 66860 cycles (5) are required for the correction operation and 5 × 8 × 208 = 8320 cycles / block (6) are required for the refresh cycle.

The block total of these (1) to (6) is 540.5 × 208 + 455 × 172 + 420 × 208.
+ 66860 + 8320 = 465649 cycles.

Since 1550 clocks of 40 MHz can take 4550 cycles in the PI frame, (4550 × 208) /465649=2.032, and double speed is possible for the memory 6 for error correction.

In the above example, as the error correction code, the product code composed of the PI series and the PO series is used, but an error correction code having another configuration may be used. In this example, the PI sequence is decoded and P
Although the PI series is further decoded after the O series is decoded, the error correction processing may be completed for the PI series decoding and the PO series decoding.

[0086]

According to the present invention, when the demodulated reproduction data is written in the ring buffer memory and one ECC block worth of data is written in the ring buffer memory,
One ECC block worth of data is sent from the ring buffer memory to the error correction circuit to perform PI series error correction processing, and one ECC block worth of data is written to the error correction memory, and then stored in the error correction memory. The error correction circuit performs PO series error correction processing on the data, further performs PI series error correction processing, and when the error correction processing is completed, the data is transferred from the error correction memory to the ring buffer memory,
Data is output from the ring buffer memory at the required transfer rate. Since data writing from the ring buffer memory to the error correction memory and error correction processing of the PI series in the error correction circuit occur at the same time, the data processing speed is shortened. For example, the disk is read at double speed and the ATAPI interface is used. In 1
Data can be transferred at 6.6 Mbit / s.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a disk reproducing apparatus to which the present invention has been applied.

FIG. 2 is a schematic diagram illustrating a data format of a DVD.

FIG. 3 is a schematic diagram illustrating a data format of a DVD.

FIG. 4 is a schematic diagram illustrating a data format of a DVD.

FIG. 5 is a block diagram used for explaining an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 6 is a block diagram used for explaining an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 7 is a block diagram used for explaining an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 8 is a block diagram used for explaining an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 9 is a block diagram used for explaining an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 10 is a schematic diagram used for explaining a ring buffer in an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 11 is a schematic diagram used for explaining a ring buffer in an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 12 is a schematic diagram used for explaining a ring buffer in an example of a disc reproducing device to which the present invention is applied.

FIG. 13 is a schematic diagram used for explaining a ring buffer in an example of a disc reproducing device to which the present invention is applied.

FIG. 14 is a block diagram used for explaining an error correction circuit in an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 15 is a timing diagram used for explaining an error correction circuit in an example of a disk reproducing device to which the present invention is applied.

FIG. 16 is a timing diagram used for explaining an error correction circuit in an example of a disk reproducing device to which the present invention is applied.

FIG. 17 is a timing diagram used for explaining an error correction circuit in an example of a disk reproducing device to which the present invention is applied.

FIG. 18 is a timing diagram used for explaining an error correction circuit in an example of a disc reproducing device to which the present invention is applied.

FIG. 19 is a timing chart used for explaining an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 20 is a timing chart used for explaining an example of a disc reproducing apparatus to which the present invention is applied.

FIG. 21 is a schematic diagram used to describe a basic configuration of a ring buffer memory.

FIG. 22 is a block diagram used for explaining an example of a conventional disc reproducing apparatus.

FIG. 23 is a block diagram used for explaining an example of a conventional disc reproducing apparatus.

FIG. 24 is a block diagram used for explaining an example of a conventional disc reproducing apparatus.

FIG. 25 is a timing chart used for explaining an example of a conventional disc reproducing apparatus.

FIG. 26 is a block diagram used for explaining another example of the conventional disc reproducing apparatus.

FIG. 27 is a block diagram used for explaining another example of the conventional disc reproducing apparatus.

FIG. 28 is a block diagram used for describing another example of the conventional disc reproducing apparatus.

FIG. 29 is a block diagram used for explaining another example of the conventional disc reproducing apparatus.

FIG. 30 is a timing chart used for explaining another example of the conventional disc reproducing apparatus.

FIG. 31 is a block diagram used for explaining still another example of the conventional disc reproducing apparatus.

FIG. 32 is a block diagram used for explaining still another example of the conventional disc reproducing apparatus.

FIG. 33 is a block diagram used for explaining still another example of the conventional disc reproducing apparatus.

FIG. 34 is a block diagram used for explaining still another example of the conventional disc reproducing apparatus.

FIG. 35 is a timing chart used for explaining still another example of the conventional disc reproducing apparatus.

[Explanation of symbols]

1 ... Optical disc, 5 ... Ring buffer memory,
6 ... Memory for error correction, 7 ... Error correction circuit

Claims (4)

[Claims] 1. A reproducing unit for reproducing a recording medium on which digital data is recorded, a ring buffer memory for variable rate control, an error correcting unit for performing an error correction process on the data reproduced from the recording medium, An error correction memory that stores data of an error correction block for performing error correction by an error correction unit is provided, and reproduction data reproduced from the recording medium is written to the ring buffer memory, and the ring buffer memory is provided with the reproduction data. When the data for the error correction block is written, the data for the error correction block is sent from the ring buffer memory to the memory for error correction and to the error correction means, and the error correction block is stored in the memory for error correction. At the same time as writing the minute data, By the first
Error correction processing is performed in the above direction, and when the error correction block data is written in the error correction memory, the error correction means performs error correction processing in the second direction, When the error correction processing is completed in the direction of 2, the error-corrected data is transferred from the error correction memory to the ring buffer memory, and the error-corrected data transferred to the ring buffer memory is transferred to the ring buffer memory. A data playback device that outputs at the required transfer rate. 2. After performing error correction processing in the second direction, error correction processing is performed again in the first direction, and the first direction, the second direction, and The data reproducing apparatus according to claim 1, wherein when the error correction processing is completed in the first direction, the data subjected to the error correction processing is transferred from the error correction memory to the ring buffer memory. 3. A data reproducing method for reproducing at a variable rate from a recording medium on which digital data is recorded, the method comprising: writing the reproduced data reproduced from the recording medium into a ring buffer memory; When the data for the error correction block is written in the memory, the data for the error correction block is sent from the ring buffer memory to the error correction memory and the error correction means, and the error correction block is stored in the error correction memory. Of the error correction block in the first direction at the same time that the error correction block is written in the memory for error correction. A step of performing error correction processing in the second direction by the correction means, When the error correction processing is completed in the direction of, the step of transferring the error-corrected data from the error correction memory to the ring buffer memory, and the data after the error correction processing transferred to the ring buffer memory Is output at the required transfer rate. 4. After performing error correction processing in the second direction, error correction processing is performed again in the first direction, and the first direction, the second direction, and again 4. The data reproducing method according to claim 3, wherein when the error correction processing is completed in the first direction, the data subjected to the error correction processing is transferred from the error correction memory to the ring buffer memory.