KR980011293A - A decoding apparatus of a digital video disk system - Google Patents

Abstract

According to the present invention, the error correction memory and the variable bit control memory, which exist separately, are constituted by a single memory, and the address comparator is disposed at the previous stage of the error correction unit, thereby improving the data processing speed for data error correction and variable bit reproduction And more particularly, to a decoding apparatus and a data processing method for a digital video disk reproducing system.

The decoding apparatus of the present invention includes memory means for performing an error correction function and a variable bit control function of data together and memory control means for controlling data processing in accordance with the state of the variable bit control memory in the memory means. Meanwhile, the data processing method of the present invention includes the steps of inputting demodulated data to an address comparator to determine whether or not it is desired sector data, and outputting it to a memory control means in the case of desired sector data; A step of reading the error-corrected data from the memory means and judging whether or not it is MPEG data for all the sector data; and if the data is not MPEG data, And performing variable bit control processing in the case of MPEG data and transmitting the variable bit control processing.

According to the present invention, it is possible to improve the processing speed of data for error correction and variable bit reproduction of data, and to simplify the configuration of the system.

Description

A decoding apparatus of a digital video disk system

FIG. 1 is a block diagram of a decoding apparatus of a conventional digital video disc reproducing system. FIG.

FIG. 2 is a block diagram of a decoding apparatus of a digital video disk reproducing system according to an embodiment of the present invention; FIG.

FIG. 3 is a flow chart of data at the time of data processing by the second view apparatus. FIG.

FIG. 4 shows an example of the use of partitioning for a dynamic random access memory (DRAM) in a second drawing device; FIG.

FIG. 5 is a block diagram of a decoding apparatus of a digital video disk reproducing system according to another embodiment of the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

1: Demodulator 2: Memory controller

3: Error correction memory 4: SRAM

5: error correction unit 6: address comparator

7: Interface control unit 8: Variable bit control memory

11: Demodulator 12: Address comparator

13: SRAM 14: memory controller

16: ECC 17: DRAM

18: Interface controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video disk system, and more particularly, to a decoding apparatus of a digital video disk reproducing system that performs variable bit control and error correction.

In recent years, systems have been developed for recording and reproducing moving pictures on / from a high density optical disk by compressing an image using a high-efficiency coding technology. According to a variable bit rate digital video disk system, It is possible to realize the reproduction of the moving picture for two hours together with the concept of the " movie on the disk " This variable bit rate digital video disk system uses a variable bit rate coding technique in which the amount of code generated in response to complicated image information changes and a system similar to MPEG2 to ensure a high quality image.

In this variable bit rate digital video disk reproducing system, a typical decoding apparatus has a configuration as shown in FIG. 1, the data demodulated by the demodulator 1 during the reproduction of a digital video disc (hereinafter referred to as DVD) is supplied to the memory controller 2, Error correction is performed by the correction memory (3) (4) and the error correction unit (5). Here, a static random access memory (SRAM) is used as the error correction memory. The error-corrected data is sent to the address comparator 6, and the address comparator 6 reads the sector address of the data and determines whether or not the data is transmitted to the interface control unit 7. Further, the address comparator 6 generates a jump signal when the variable bit control memory 8 is full, and causes the servo to read the data of all the tracks and waits for the data to be connected. During this period, the level of the variable bit control memory 8 is lowered and the variable bit control memory 8 stores the data again when the waiting data sector is input. The interface control unit 7 may control the data transmission to MPEG and may separate the system data from the input data.

The memory 3 for error correction and the memo line 8 for variable bit reproduction exist separately and a sector address comparator 8 is provided between the memory for error correction 3 and the memory 8 for variable bit control 5) is positioned to control the flow stop and connection of data.

However, in such a conventional apparatus, the processing speed of data is delayed by a time required for reading and writing data in the memory for error correction, and the error correction memory and the variable bit control memory are separately provided.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a decoding apparatus of a DVD reproduction system which improves the variable bit control of data and the speed of data processing for error correction.

Another object of the present invention is to improve the processing speed of data by setting an address comparator in front of an error correction portion in data error correction and variable bit control, and then writing data to the memory after correcting the PI error.

It is still another object of the present invention to provide a decoding apparatus for a DVD reproduction system that simplifies the configuration by replacing the existing error correction memory and variable bit control memory with one memory.

According to another aspect of the present invention, there is provided a decoding apparatus for a DVD reproduction system, comprising: memory means for performing an error correction function and a variable bit control function of data; And memory control means for controlling data processing in accordance with the state.

Further, the apparatus further includes an address comparator which is located at the front end of the memory control unit and determines whether data is to be transferred according to the state of the variable bit control memory in the memory means.

A data processing method of a DVD reproducing system according to the present invention includes the steps of inputting demodulated data to an address comparator to determine whether or not it is desired sector data and outputting it to a memory control means in case of desired sector data; The method comprising the steps of: performing error correction on the input data and writing it into the memory means; reading the error-corrected data from the memory means to determine whether or not it is MPEG data for all sector data; If the data is not data, directly transmitting the variable bit control process and transmitting the variable bit control process if it is MPEG data.

These and other objects and advantages of the present invention will become more apparent from the detailed description of an embodiment of the present invention with reference to the drawings.

The configuration and operation of a preferred embodiment of the present invention will now be described in detail with reference to FIGS. 2 to 5.

FIG. 2 is a block diagram showing a configuration of an embodiment of a decoding apparatus of a DVD reproducing system according to the present invention. 2, the decoding apparatus includes an ediths comparator 12 disposed at the next stage of the demodulator 11 to receive demodulated data from the demodulator 11, and data with a PI error correction frame unit (here, 182 bytes) , And a memory (2) is provided with a small number of memories (2), and three frames of SRAM are used. And a memory 17 made up of a dynamic random access memory (DRAM) for error correction, variable bit control, and data search information (hereinafter referred to as DSI). The memory control unit 14 controls the data arrangement of the memory 17 and performs error correction by inputting and outputting data in units of frames into an error correction block from the error correction unit 6. [

The error correction in the DVD reproducing system is normally performed on data of 37856 bytes horizontally by 182 bytes and vertically by 208 bytes. The PI error correction and the vertical correction are referred to as PO error correction in this way. The apparatus of the present invention controls the memory controller 14 to control the PI error correction and the PO error correction in a cyclic manner by providing two SRAM memories 15 for the two frames. After the error correction is completed, the memory controller 14 selects MPEG data, system data, and DSI data, and outputs system data to the system buffer (not shown) and MPEG data and DSI data to the interface controller 7. If the DRAM 17 is full, an overflow signal overflow is sent to the address comparator 12 to stop the data transfer. The interface control unit 18 controls the data transmission to the MPEG, and discards data not required by MPEG out of data of 16 sectors per block and transfers the remaining data to a track buffer (not shown).

FIG. 3 is a data flow chart for data processing by the decoding apparatus of the DVD system according to the present invention. As shown in FIG. 3, the data demodulated by the demodulator 11 is first input to the address comparator 12 in step 1, and it is determined whether or not the sector data is a desired sector data. Here, there are two types of sector addresses to be connected, one is the sector address stored while the data transmission is stopped by the overflow signal of the DRAM 17, and the other is the sector Address.

Here, FIG. 4 shows an example of using a partition for the DRAM 17 having the storage capacity of 256K × 16 bits. As shown in FIG. 4, E1 and E2 are arranged so as to circulate each other for error correction into an area corresponding to one block. That is, if the PI error is corrected for E1, the PO error is corrected for E2, and if the PI error is corrected for E2, the PO error is corrected. The area from B1 to B12 in the figure is a circulating area for variable bit control. The DSI area is an area for storing DSI data.

Next, if it is determined in step 2 that the input data is the desired sector data, the data is transmitted to the memory controller 14 in units of 182 bytes, and the memory controller 14 transmits the data to the error corrector 16 To perform PI error correction. After the PI error correction is completed, data is written to DRAM 17 in step 3. Then, in step 4, the data written in the DRAM 17 is read out, and the PO error correction is performed in units of 208 bytes. After the PO error correction is completed, the data is written back to the DRAM 17 (step 5), and the error correction is completed. After completion of the error correction, error corrected data is read from the DRAM. In step 6, whether or not all the sector data are MPEG data is determined. If the error data is not MPEG data, 17 to the interface control unit 18 (step 7). In step 8, the interface control unit 18 transmits only the sector data required by the MPEG in the block unit data of 16 sectors.

FIG. 5 is a block diagram showing the configuration of another embodiment of a decoding apparatus for a DVD reproduction system according to the present invention. As shown in FIG. 5, in the embodiment of FIG. 5, all the components are the same as the embodiment of FIG. 2, only the address comparator 12 is shown in the embodiment of FIG. 2 arranged at the front end of the memory controller 14 Differs only in that the address comparator 12 is disposed between the memory controller 14 and the DRAM 17. [ Therefore, in the configuration of the fifth embodiment, each constituent element is given the same reference numeral as the corresponding constituent element of FIG. 2, and a description thereof will be omitted. Compared with the configuration of the second embodiment, the configuration of the fifth embodiment is advantageous in that the data input to the address comparator 12 is error-corrected data, so that the comparator operates more stably. On the other hand, The overall system control speed is lowered because of the delay.

As described above, according to the present invention, since the error correction memory and the variable bit control memory, which exist separately, are constituted by a single memory and the address comparator is disposed at the preceding stage of the error correction unit, error correction and variable bit reproduction The processing speed of the data can be improved and the configuration of the system can be made simpler.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventive concept as defined by the appended claims. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the matters described in the claims.

Claims (5)

A digital video disk system for performing variable bit control and error correction of data, comprising: memory means for performing an error correction function and a variable bit control function of data together; And memory control means for controlling data processing in accordance with the state of the variable bit control memory in said memory means. 2. The digital video disk reproducing apparatus according to claim 1, wherein the memory means comprises a region for circulating for error correction, a region circulating for variable bit control, and a dynamic random access memory divided into regions for data search information A decoding device in a system. 2. The digital video disk reproducing system according to claim 1, further comprising an address comparator which is located at a previous stage of the memory control unit and determines whether data is to be transferred according to the state of the variable bit control memory in the memory means, / RTI > 2. The digital video recorder according to claim 1, further comprising an address comparator located between the memory means and the memory control unit and determining whether data is to be transferred according to the state of the variable bit control memory in the memory means. Decoding apparatus of the reproduction system. A digital video disk reproducing system for performing variable bit control and error correction of data, the system comprising: a demultiplexer for inputting demodulated data to an address comparator to determine whether it is desired sector data, and outputting the demodulated data to memory control means Wow; Performing error correction on the data input from the memory control means and writing the data into the memory means; Reading the error-corrected data from the memory means and determining whether or not all sector data is MPEG data; And transmitting and receiving variable bit control processing in the case where the data is not MPEG data in the determination step and in the case of MPEG data. ※ Note: It is disclosed by the contents of the first application.