JPS62274933A - Error detection system - Google Patents

Abstract

PURPOSE:To improve the error detection capability by generating parities whose number corresponds to the number of data words in a frame on a basis of data words in the same positions in respective frames of a correction sequence and adding them to a sector and detecting error with these parities. CONSTITUTION:Plural error detection codes (parities) generated on a basis of data in the same columns of sectors are added to each sector of a data string by a detection code adding circuit 1. Data in each sector to which parities are added is inputted to an error correction code circuit 2, and error correction codes Q2 and R2 generated on a basis of data words of a C1 correction sequence are added to data in each sector including said parities, and interleaving is performed to add error correction codes Q1 and R1 generated on a basis of data words of a C1 correction sequence. The data string reproduced by an optical disc drive 3 is inputted to an error correction decoding circuit 4 and hasd each sector subjected to two-stage error correction of C1 correction and C2 correction and is inputted to an error detecting circuit 5. The error detecting circuit 5 detects whether error correction in the circuit 4 is correct or not for each sector in accordance with a syndrome generated on a basis of reproduced data and parities.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In an error detection method after error correction for each data word of digital data in a plurality of sectors of a frame consisting of a plurality of data words, a correction sequence is Parity equal to the number of data words in a frame is generated based on multiple data words in the same word position in each frame and added to the sector, and error detection after error correction during decoding is performed using this parity. By doing so, the error detection ability is improved.

[Industrial application field]

The present invention relates to an error detection method in recording/reproducing, information processing, code transmission, etc. by a high-density recording device such as an optical disk memory or a magneto-optical memory.

[Conventional technology]

As one of the error correction methods, interleaving is performed to avoid continuous errors in burst state, and even if such continuous errors occur, continuous errors can be prevented by converting data words and rearranging them to the data string before interleaving. Correction is performed by converting the errors into discrete errors.

A CRC code is used as a code to detect whether or not this correction has been performed correctly.

[Problem that the invention seeks to solve]

This CRC code has a high ability to detect continuous errors, but a low ability to detect discrete errors.

An object of the present invention is to compensate for such a decrease in the error detection ability of the CRC code.

[Means for solving problems]

Parity is generated based on the data words written in each series (hereinafter referred to as a column) of multiple data words that have the same word position in each frame of the correction series in the error correction interleave memory, and The parity is added to the column, an error correction code based on one or more error correction sequences is added to the data for each sector including this parity, error correction is performed using the error correction code in the error correction sequence during decoding, and then the above parity is added. Error detection is now performed.

Furthermore, the error detection ability is improved by ORing with error detection during error correction.

[For production]

FIG. 1 is a diagram showing the state of one sector of data and parity in a deinterleaved memory.

The correction sequence is the direction in which the data that generates the error correction code is lined up, and is tilted as shown by the broken line in Figure 1, but the number of data is the same as one frame, and is shown by the arrow. The data aligned in the direction occupy the same word position within the frame of each correction series, and their data strings intersect with the data strings of the frames of the correction sequence.

The error detection parity of the present invention is generated from data occupying the same word position within the frame of the correction sequence described above.

〔Example〕

FIG. 2 is a block diagram showing the error correction and error detection section of the optical disk memory device. The error detection code adding circuit 1 includes the encoding circuit 100 of the embodiment shown in FIG. The decoding circuit 500 of the embodiment shown in FIG. 4 is provided.

In addition, in this embodiment, two stages of error correction using 01 correction and 02 correction are performed, but the two sets of error correction codes (Q+
, R+ and Qz, Rz) are not particularly limited, and a b-adjacent code, a Reed-Solomon code, or other code can be used as the error correction code.

The detailed content of error correction processing can be found in the technical literature (Modern Digital Audio Technology co-authored by Mitsuyoshi Niyamashita and Hiroyasu Minayoshi).
Ohmsha, pages 6o to 76) describes the case of a compact disc, and a detailed explanation of this embodiment will be omitted.

(Error Correction and Error Detection) An outline of the operation in which generated data is recorded and reproduced and subjected to error correction and error detection will be described with reference to FIG.

A digital data string outputted from a data output device (not shown) is sent to a detection code adding circuit 1 where a plurality of error detection codes ( Parity (hereinafter referred to as parity) is added to each sector.

The data for each sector to which parity has been added is input to the error correction code circuit 2, and error correction codes Q2 and R2 generated based on the data words of the 02 correction series are added to the data for each sector including the parity. , and error correction codes Q and R, which are interleaved and generated based on the data words of the 01 correction series, are added.

The data for each sector including the parity and error correction code configured in this manner is recorded on a disk by the optical disk drive 3.

Next, the data string reproduced by the optical disk drive 3 is input to the error correction decoding circuit 4, where it is corrected by 01 for each sector.
A two-stage error correction of 02 correction is performed.

The data subjected to error correction as described above is input to the error detection circuit 5. The error detection circuit 5 detects that no data is erroneously corrected in the error correction by the error correction decoding circuit 4 due to the syndrome generated based on the reproduced data and parity, as will be explained later in (Syndrome generation). Alternatively, it is detected for each sector whether or not any error data has been missed, and if an error is detected by this detection, the entire sector is detected as an error.

Next, the data format of one sector in this embodiment will be explained.

(Data Format) FIG. 5 shows the data format of one sector in the embodiment, and FIG. 6 shows the state of one sector in the deinterleave memory of the 02 correction series.

The broken lines in FIG. 6 indicate the directions of the C0 correction series and the 02 correction series, and the arrows indicate the direction ( the column direction).

In this example, one sector includes 256 frames of data and 8
It consists of word parity, and ■The frame consists of 8 words, so the number of data words in one sector is 20.
It is 48.

Next, the parity generation process will be explained.

(Generation of parity) If the data string of one sector is Dl...D2o48,
Parity P, -P is generated by the following formula.

I P, -Σ D,,? , ...(1
) However, i is 1 to 8, the total is 1Ilod2 addition, n is the number of data words in one sector, m is the number of data words in one frame, and in this example, n=2048,
Since m=8, equation (11) becomes as follows.

However, ■ indicates addition of mad 2.

FIG. 3 is a block diagram of the encoding circuit 100, where P, ~
Each parity register 01 to 108 of pe is calculated by formula (2)
From the first term on the right side of
1 to D2.48 and the output data of parity registers 01 to 108 are selected and output, and the adder 120 selects and outputs the output data of parity registers 01 to 108 and the input data value.
d Perform 2 additions.

The control unit 140 controls the parity registers 101 to 108.
and controls the operation of the selector 130.

Next, the parity generation circuit generates the input data D, ~
D1 to D204B as output data for D204B
The operation of outputting parity P+''Pe will be explained.

Parity register 1 is input before one sector of data is input.
01 to 108 are reset, and the value held by that register is set to O.

When one sector of data starts to be input and data D1 is input to the adder 120, under the control of the control unit 140, P,
Parity register 101 is selected and the value it holds is 0
is output and sent to adder 120, and the other parity registers 102-108 do not output.

Data D1 and P1 parity register 10 in adder 120
The value O held by 1 is mod 2 added and output, and the added value is input only to the parity register 101 selected under the control of the control unit 140 and is held by the other parity registers 102. -108 are not input.

During the above operation, the selector 130 is controlled by the control section 140 and outputs the input data D1 as output data, but the output data O of the P1 parity register 101 is not accepted as input data under the control of the control section 140. ,P.

The value of parity register 101 is not output.

When data D2 is input to adder 120 following data D1, control unit 140 controls P2 parity register 102 to send value O held in P2 parity register 102 to adder 120.

Adder 120 connects data D2 and P2 parity register 1
Add Hod 2 to the value O held in 02 and output it.
The added value D2 is input to and held in the parity register 102 controlled by the control unit 140, while the selector 130 outputs only the data D2 as described above.

Similarly, each time data D3 to D11 are input to the adder 120, the control unit 140 causes the parity register 10 to
3 to I08 are selected respectively, and the parity register 10
Data D3 to D8 are held in 3 to 108. Furthermore, during this time, the selector 130 successively sends out data D3 to D following data D2.

When data D is input to the adder 120 following the data D8, the value D1 held in the parity register 101 is outputted from the parity register 101 and input to the adder 120, and the adder 120 mod 2 Additional value D1 due to addition
D9 is output, and the parity register 101 holds ■D, and the selector 130 outputs data D9 following data D8.

In this way, each parity register 101 to 108 is selected once every 8 data inputs under the control of the control unit 140 for each data word of data D+ -D 204B, and the output and input operations are performed according to the row. Update the held value.

By the following operation, the data DI""Dz. 46
are sequentially input, the selector 130 outputs data D1 to
At the time when D2°48 is sequentially output and data Dro4e is output, the expression (
Parities P1 to P8 shown in 2) are held.

Next, the control unit 140 controls the parity registers 101 to 108.
By controlling the selector 130 to sequentially output the values held by the parity register 101 to the parity register 101, and by controlling the selector 130 to sequentially accept output data from the parity registers 101 to 10 as input data. Parities P1 to P8 are sequentially output from the selector 130 following data D2.48.

In this way, the data is sent to the error correction code circuit 2 with 8 words of parity added to each sector.

Next, the error correction codes Q, , R are reproduced.

, Q, ,R, will explain the process of generating syndromes for detecting errors in data subjected to C1 correction and 02 correction with reference to FIG.

Syndrome Generation) If the reproduced and error-corrected data and the parity are D1' to D2°48' and PI' to P8', syndromes 81 to S8 are generated by the following equations.

However, each symbol and character is the same as 2fil, and the formula (
Similarly to 2), equation (3) becomes as follows.

a data string to which the parity PI-Pfi is added;
...D2゜4eyPl ...P8 is interleaved in the error correction code circuit 2 and recorded on the disk, but the data string reproduced from the disk is interleaved in the error correction circuit 4.
Since the data words are converted into data words at
'~P8' are two data strings D1...D2゜4ByP
I... Corresponds to each pH data, and constitutes a reproduced data string '...D2°4B'+PI'...P8'. Therefore, if there is no error in the reproduced data D,'~D2°48' and the parities P1'~P8', the values of equation (4) will all be 0, and conversely, at least any of the values of equation (4) will be zero. If one of them is not O, then this sector contains an incorrect word.

FIG. 4 is a block diagram of the decoding circuit 500.
Each syndrome register 501 to 508 of Ss is expressed by the formula (
Starting from the first term on the right side of 4), each term sequentially holds the Hod 2-added value to hold each syndrome SI to Sll generated by a predetermined number of operations, and the adder 520 stores the syndrome registers 501 to 508. The error determination circuit 530 performs 11od 2 addition of the output value of and the value of each reproduced data.
is the reproduced data D1' when at least one syndrome among the syndromes S I"" S n generated in the syndrome registers 501 to 508 is 0.
- It is determined that there is an error in D2°48', and that sector is determined to be an error.

The control unit 540 controls the syndrome registers 501 to 5.
08 and the operation of the error determination circuit 530.

Next, the syndrome generation and error detection operations performed by the decoding circuit 500 will be described.

(2) Reset the syndrome registers 501 to 508 before the reproduction data of the sector is input, and set the value held by the register to 0.

When one sector of reproduction data starts to be input and data DI' is input to the adder 520, the control unit 540 controls the Sl syndrome register 501 to hold (lI!).
A zero is output and sent to adder 520.

The adder 520 adds mod 2 the data DI' and S to the value 0 held in the syndrome register 501 and outputs the result, and the added value D1' is input to the S1 syndrome register 501 which is selectively controlled by the control unit 540. is retained.

During the above operation, the error determination circuit 530 is controlled by the control unit 540, and the S1 syndrome register 501
No judgment is made even if output data O is input.

As described above, each syndrome register 5 of 81 to Sll
01 to 508 and the adder 520 perform the same operations as the parity registers 101 to 108 and the adder 120 of the PI-P8 of the encoding circuit 100, and the control unit 540 controls each of the syndrome registers 501 to 508. Each time data is input, similarly to the control unit 140 of the encoding circuit 100, the syndrome registers 501 to 508 are selectively controlled to output and input only the selected syndrome register. Column DI'・
...D2゜48'tP1'...When P8' is input, the syndromes shown in equation (4) are stored in the syndrome registers 501 to 508. Each of the syndromes 81 to s8 thus generated is stored in the syndrome registers 501 to 508. are sequentially sent to the error determination circuit 530 and determined under the control of the control unit 540, and if there is even one syndrome whose value is 0,
The error determination circuit 530 detects the sector as an error.

As described above, parity and syndrome are generated for multiple data words that have the same word position in the frame corresponding to each series of one correction series, so one word error is generated in each column of a sector. can be detected.

Moreover, high detection ability can be obtained by "ORing" the detection result of the error detection circuit and the error detection in 02 correction.

In the embodiment, two sets of error correction codes are used, but
As explained above, the number of sequences and the types of correction codes are not limited to those in the embodiment.

Further, the data is not limited by the data format, such as the number of data, as long as the number of data constituting a frame is constant.

〔Effect of the invention〕

By performing error detection using parity generated by data occupying the same data word position within the frame of the error correction sequence, error detection capability can be improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of an implementation device, Fig. 3 is an encoding circuit of an embodiment, Fig. 4 is a decoding circuit of an embodiment, and Fig. 5 is data of an embodiment. Format, 6th
The figure is a diagram showing the state of the deinterleave memory. Patent Applicant: Ricoh Co., Ltd. - %Figure 3 A? J-hi format jL coding circuit No. 4■

Claims (2)

[Claims] (1) In an error detection method after word-by-word error correction of digital data in a sector consisting of a plurality of frames of a plurality of data words, the word position in each frame of the correction sequence is the same before the addition of an error correction code. Generate as many parities as the number of data words in the frame based on the plurality of data words and add them to this sector, and when decoding, generate the above parity and the parity for the sector after error correction for each data word. An error detection method characterized in that error detection is performed by generating as many syndromes as there are data words in a frame based on decoded data of data that contributed to the frame. (2) The error detection method according to claim 1, wherein the parity is generated by performing an exclusive OR for each bit of a plurality of data words contributing to the generation of the parity.