JP2001292066A - Error correction device and error correction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction device that can reduce a time for error check processing without increasing the circuit scale. SOLUTION: A data buffer 14 receives data including a product code whose error is corrected in 1st and 2nd directions and temporarily stores the data. An exclusive OR arithmetic circuit 9 uses an error quantity detected by the error correction in the 1st direction and data stored in a storage element 11 to calculate a 1st error check result. A PI direction error check circuit 3 checks an error after the error correction in the 1st direction in response to the 1st error check result, and a PO direction part error check circuit 8 and a PO direction summing error check circuit 6 use the error quantity detected at the error correction in the 2nd direction to calculate the 2nd error check result. An exclusive OR arithmetic circuit 5 generates a final error check result on the basis of the 1st and 2nd error check results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction apparatus and an error correction method for a data transfer system, and more particularly to an apparatus and a method for processing error correction and checking of a multidimensional code such as a product code at a high speed. .

[0002]

2. Description of the Related Art As recording, reproduction and transmission of video information and the like having a large amount of information have been performed as digital signals, error correction and correction have been required to improve the reliability of recorded or transmitted information. The importance of error checking increases. In particular, when real-time recording or reproduction is required, high-speed processing is required to perform error correction and inspection on such a large amount of information.

A conventional data transfer system, for example, a recordable / reproducible magneto-optical disk device, adds an error correction code composed of a product code to received data and stores the data in a storage medium.

[0004] Thereafter, the stored data is called to an error correction device as necessary, and after error correction, error checking is performed with an error check code (hereinafter, referred to as EDC). After being confirmed, it is output to the outside.

Similarly, in a read-only optical disk device, the stored data is called to an error correction device as necessary, and after error correction, error checking is performed with an error check code to confirm that there is no error. Is confirmed and then output to the outside.

In a conventional error correction method, for example,
In a DVD (Digital Video Disc), data read from the disc is temporarily stored in, for example, an SDRAM (Sy
It is stored in a buffer of an external semiconductor storage element such as an nchronous dynamic random access memory (NCH). Thereafter, the data is called by the error correction device, and the error is corrected.

For example, in a DVD, a product code is used in which data is arranged in a rectangle and error correction codes in two directions, a vertical direction (PO) and a horizontal direction (PI) are added.

FIG. 17 shows the format of a conventional DVD error correction product symbol. In the information data of 172 bytes (Byte) × 192 rows (row) arranged in two dimensions,
Data to which a parity PI (error correction inner code) of 10 bytes (Byte) in the horizontal direction and a parity PO (outer code of error correction) of 16 bytes (Byte) in the vertical direction are added to 1
It is a block. In FIG. 17, the horizontal direction is also called the PI direction, and the vertical direction is also called the PO direction.

FIG. 18 is a diagram showing the relationship between the error correction product code (error correction inner code and error correction outer code) and the error check code (EDC) of the DVD shown in FIG.

The above-mentioned one block is divided into 16 sectors, and one sector is composed of a data array of 172 bytes × 12 rows, and these data arrays have 4 data at the end thereof.
Includes Byte EDC.

FIG. 19 is a diagram showing a data array of one sector including an error check code, in which numbers are assigned in descending order from the first bit.

The data for one sector is bit data b1
The data are arranged as data from 6511 to bit data b0, and bit data b31-b0 correspond to EDC.

FIG. 20 shows a DV having the above configuration.
First to perform error correction and error check on D data
FIG. 7 is a schematic block diagram for explaining a configuration of a conventional example.

Referring to FIG. 20, a basic pattern for decoding is based on, for example, the following procedure.

1) An input signal is stored in a data buffer (SDRAM) 24 via a data bus 21, and a PI direction error correction circuit 20 reads data in the PI direction from the data buffer 24 and calculates a syndrome.

2) The PI direction error correction circuit 20 detects an error amount and an error position from the value of the syndrome in the PI direction, and performs error correction on the data stored in the data buffer 24.

3) Next, the PO direction error correction circuit 22 reads data in the PO direction from the data buffer 24 and calculates a syndrome.

4) The PO direction error correction circuit 22 calculates an error amount and an error position based on the value of the syndrome in the PO direction, and performs error correction on the data stored in the data buffer 24.

An error is corrected by repeating the above processing. 5) After these error corrections are completed, the error checking circuit 23
The data is read from the data buffer 24, and it is confirmed that there is no error using the error check code.

[0020]

A problem that arises when the above processing is performed is that after error correction, the data buffer (SDRAM) 24 is accessed again and an error check is performed. The error checking operation requires a lot of time.

For example, in the structure shown in FIG. 20, since data is read from data buffer 24 to error checking circuit 23 only after error correction is performed using data read from data buffer 24, a relatively long time is required. The number of times data is read from or written to the data buffer 24 increases, and the processing time becomes longer.

To solve this problem, for example, there is a method disclosed in Japanese Patent Application Laid-Open No. H11-55129.

FIG. 21 is a schematic block diagram for explaining a configuration of a second conventional example for performing error correction and error checking disclosed in Japanese Patent Application Laid-Open No. H11-55129.

The structure of the error correction and error checking apparatus shown in FIG. 21 employs a structure in which a data bus for the error correction circuit and a data bus for the error check circuit are used in combination.

FIG. 22, FIG. 23, FIG. 24, FIG.
22 are first to fourth conceptual diagrams each showing a schematic diagram of the processing of the error correction and error checking device shown in FIG. 21.

In FIGS. 22 and 23, data for error checking is omitted as 10 columns × 4 rows = 40 for simplicity of explanation.

The error check using the error correction and error check apparatus shown in FIG. 21 is executed in two stages.

In the first stage, data is read from the buffer 34 for error correction in the PI direction, for example.
According to the order of the data array as shown in FIG.
The data is transferred to the ATA syndrome generation circuit 36, and the DATA syndrome is calculated.

The calculated DATA syndrome is stored in the storage element 32. On the other hand, in the first stage, DATA
Apart from the calculation of the syndrome, the ERROR syndrome is calculated in accordance with the order of the data array as shown in FIG. 22 using the error amount detected by the error correction circuit 30 in the PI direction.

In the second stage, the error amount detected by the error correction circuit 32 in the PO direction is further used to determine
The continuation of the ERROR syndrome is calculated according to the order of the data array shown in FIG.

Finally, as shown in FIG. 24, the two syndromes, namely, the DATA syndrome and the ERR
The exclusive OR calculator 35 calculates the exclusive OR with the OR syndrome to calculate the final inspection syndrome. The determination circuit 31 determines the result of the error detection based on the inspection syndrome.

Therefore, since it is not necessary to read data from the data buffer 34 again to generate the inspection syndrome, it is possible to perform the error correction and the error inspection at high speed in parallel.

Further, for example, when the error correction syndrome is calculated by the error correction circuit 32 in the PO direction, for example, when there is no error in the code word of the third column (COL3), the amount of error to be performed next and the error position In response to the process of omitting the detection operation of ERROR, as shown in FIG.
Even at the time of syndrome calculation, for code words having no error, the calculation speed is increased using the offset value.

However, for this offset calculation, E
In the RROR syndrome generation circuit 38, there are a case where the operation is performed row by row in the vertical direction, a case where the processing is shifted from a certain column to an adjacent column, and a case where the processing is shifted to a column skipped from one column. Correspondingly, an arithmetic processing circuit having arithmetic paths for three or more syndromes is required, and there is a problem that the circuit scale increases.

The present invention has been made to solve the above problems, and has as its object to reduce the access time to a storage element without increasing the circuit scale, and to provide an error stop processing. And an error correction device capable of shortening the time required for the error check process by performing the error check process in parallel.

[0036]

According to the present invention, there is provided an error correcting apparatus for correcting data to be corrected including an error correcting code having a product code capable of correcting errors in a first direction and a second direction of a data block. Error correction means for performing error correction processing, the error correction means comprising: first error correction means for correcting a first direction of a product code; and second error correction means for correcting a second direction. And a first storage element capable of storing the data to be corrected, and an error checking means for performing an error check with an error check code to confirm that the correction by the error correction calculation means is not an erroneous correction. The error check code is provided by continuously providing an error check code to data in a first direction of a data block, and the error check means determines the amount of error detected by error correction in the first direction. The first A first logical operation means for calculating a first error check result using the data stored in the storage element, and an error check after the error correction in the first direction according to the first error detection result. First direction error checking means for performing
Using the error amount detected at the time of error correction in the direction of
And a second direction error checking means for performing an error check after error correction in the second direction by calculating the error check result of the first and second error check results.

The error correction device according to the second aspect is the first aspect of the invention.
In addition to the configuration of the error correction device described above, the apparatus further includes a second storage element for receiving and temporarily storing the data to be corrected, wherein the first storage element includes a code read from the second storage element. Stores words.

The error correction device according to the third aspect is the first aspect of the invention.
Or in addition to the configuration of the error correction device described in 2 above, the second direction error checking means uses the amount of error detected at the time of error correction in the second direction for each data lined in the second direction of the data block. It has a partial error checking means for calculating a partial inspection result, and a counting error checking means for calculating a second inspection result by counting the plurality of calculated partial inspection results in the first direction.

The error correction device according to the fourth aspect is the third aspect of the invention.
In addition to the configuration of the error correction device described above, at least the second error correction unit and the first direction error check unit operate in parallel.

The error correction device according to the fifth aspect is the third aspect of the invention.
In addition to the configuration of the error correction device described above, the second direction error checker includes a third storage element that receives and stores the check result of the first direction error checker, and a third storage element that is stored in the third storage element. Second logic operation means for receiving the check result of the one-way error check means and the check result of the total error check means and performing an error check after error correction in the second direction is further included.

The error correction device according to the sixth aspect is the first aspect of the invention.
In addition to the configuration of the error correction device according to any one of the above-described items, the second direction error checker performs an exclusive OR operation on the first and second error check results, thereby obtaining a second error check result. An error check after error correction in the direction is performed.

According to a seventh aspect of the present invention, there is provided an error correction method, comprising the steps of: receiving data to be corrected including an error correction code having a product code capable of correcting errors in a first direction and a second direction of a data block; Performing an error correction process in the direction, receiving the data to be corrected, performing an error correction process in the second direction, receiving the data before the error correction, and detecting the error in the first direction. Calculating a first error check result by sequentially using the error amount; performing an error check after error correction in a first direction according to the first error detection result; A second error check result is calculated using the amount of error detected at the time of error correction, and a logical operation of the first and second error check results is performed, whereby the error check after the error correction in the second direction is performed. The steps of Provided.

The error correction method according to claim 8 is the same as the error correction method according to claim 7.
In addition to the configuration of the error correction method described above, the step of performing the error check after the error correction in the second direction is performed by using an error amount detected at the time of error correction in the second direction. A step of calculating a partial inspection result for each data lined up in the direction; and a step of calculating a second inspection result by totalizing the plurality of calculated partial inspection results in the first direction.

The error correction method according to the ninth aspect provides the error correction method according to the seventh aspect.
Or in the step of performing error checking after error correction in the second direction, in addition to the configuration of the error correcting method described in 8, by performing an exclusive OR operation on the first and second error checking results, An error check after error correction in the second direction is performed.

According to a tenth aspect of the present invention, in addition to the configuration of the error correcting apparatus of the first or second aspect, the second direction error checking means further comprises: A partial error check means for outputting a partial check result for each data lined up in the second direction of the data block based on an operation table indicating a correspondence between a predetermined error amount and a partial check result, A total error checking unit that calculates a second inspection result by totalizing the plurality of partial inspection results obtained in the first direction.

According to an eleventh aspect of the present invention, in addition to the configuration of the error correcting apparatus of the tenth aspect, the partial error checking means further comprises an error correcting unit corresponding to an error amount detected at the time of error correction in the second direction. Receiving the data sequentially over a plurality of steps, and the partial error checking means outputs an exclusive OR operation result of the partial check data based on the error data given in the previous step and the error data given in the current step. OR operation means, table operation means for receiving the output of the exclusive OR operation means, and outputting partial inspection data based on an operation table indicating correspondence between preset error data and partial inspection data, The partial inspection data output from the table operation means is received and held, and in the current step, the partial inspection data in the previous step is sent to the exclusive OR operation means. And a obtain data holding means, the table calculating means, based on the error data given in the last step, outputting the partial inspection results for each data arranged in the second direction of data blocks.

According to a twelfth aspect of the present invention, in addition to the configuration of the error correcting apparatus of the eleventh aspect, the table operation means receives the output of the exclusive OR operation means and divides the table into a predetermined number of groups. Data dividing means, and receiving the output of the data dividing means, respectively, based on an operation table indicating a correspondence between predetermined error data and partial inspection data,
It includes a plurality of sub-table operation means for outputting the partial inspection data, and a partial inspection operation means for receiving the output from the plurality of sub-table operation means and outputting the partial inspection data.

[0048]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] [Configuration of Disk Reproducing Apparatus 1000] FIG. 1 is a schematic block diagram showing the configuration of a disc reproducing apparatus 1000 provided with an error correction and parallel inspection apparatus according to the present invention. is there.

Referring to FIG. 1, drive drive circuit 149
The data read from the disk by the drive 141 driven by the
Is demodulated. The servo circuit 143 includes the signal reading circuit 14
Drive drive circuit 1 based on the signal read by
49 is controlled.

Data from the disk is read by a signal reading circuit 1
After being demodulated at 42, it is transferred to the data buffer 14 in the decoding circuit 147. The transferred data is subjected to a descrambling process after the error correction circuit 145 corrects the error and confirms that there is no error in the error check circuit 146, and the information data is transmitted to the host PC via the interface 148. Will be transferred.

In the following description, an apparatus and method for error correction and parallel checking of a product code corresponding to data recorded on a DVD will be described by taking a DVD as an example, but the present invention is limited to such a case. Without error, as shown in FIG. 18, an error correction product code is arranged for one block of data, and a product code of data for which a predetermined error check code is arranged for each sector in this one block. The present invention is applicable to an error correction and parallel inspection apparatus and method.

[Configuration of Product Code Error Correction and Parallel Checking Apparatus] FIG. 2 is a schematic block diagram for describing the configuration of decoding circuit 147 shown in FIG. FIG. 3 is a conceptual diagram for explaining the operation of the exclusive OR circuit 9 in the decoding circuit.

Hereinafter, the decoding circuit 147 will be described with reference to FIG.
Will be described. In the first step of the processing of the decoding circuit 147, the input data from the signal reading circuit 142 is transferred to the data buffer 14 via the data bus 13.
Is forwarded to Here, it is assumed that, for example, an SDRAM is used as data buffer 14.

In the second step of the processing, the data read from the data buffer 14 is stored in the first direction (PI direction).
Is transferred to the error correction circuit 10. In parallel,
For example, at least one row of data is stored in the storage element 11 for the data block.

In the third step, P
The data array is transferred to the I-direction error check circuit 3 via the exclusive OR circuit 9. Of the data, the data in which an error is detected by the PI error correction circuit 10 are as follows:
An error amount is output from the PI direction error correction circuit 10, and the exclusive OR of these is calculated by the exclusive OR circuit 9, as shown in FIG. Transferred to the circuit 3.

In the fourth step, the inspection result data calculated from the PI direction error check circuit 3 is transferred to the PI direction determination circuit 1.

The inspection result here is, for example, {I (x) mod g (x)} E
It is a calculation result of xor EDC or the like.

The test result data calculated by the PI direction error check circuit 3 is stored in the storage element 2 and is used for determining the PO direction error check result described later.

In the fifth step, the data buffer 14
, The data array is sent to the PO error correction circuit 12, and error correction in the PO direction is performed.

In this embodiment, the PI error correction circuit 10 and the PO error correction circuit 12 are separately provided in order to increase the error correction processing speed.

At this time, the error amount is output from the PO-direction error correction circuit 12 for an error detected, and the data array with the error amount set to 0 for error-free data is stored in the PO-direction error correction circuit. 12 is transferred to the partial error check circuit 8 in the PO direction.

The partial error check circuit 8 calculates the check result for each column and holds the result in the register 7, as will be described later in detail.

When the error correction in the PI direction in the third step is completed, the data buffer 14 can be accessed from the PO error correction circuit 12 via the data bus 13. Step 3
May be started at the time when the error correction in the PI direction in the step is completed.

In the sixth step, the result calculated by the partial error check circuit 8 in the PO direction is called from the register 7, and the total in the row direction of the error check in the PO direction is collected by the PO.
This is performed by the direction totaling error check circuit 6.

The exclusive OR circuit 5 calculates the exclusive OR of the result calculated at a high speed by these circuits and the error check result in the PI direction held in the storage element 2, and outputs the result to the PO direction error. The determination is made by transferring the data to the determination circuit 4.

In the seventh step, as described above, the information data in the data buffer 14 which has been corrected by the product code and which has been shown to have no error as a result of the check is transferred to the host PC in accordance with the request from the host.

The error check in the PI direction and the PO direction includes error correction in the PI direction and the PO direction, respectively.
Since the processing is executed almost in parallel, the processing speed is very high, and the inspection is completed in parallel even after the error correction in both the PI direction and the PO direction. If it is found that there is no abnormality in the inspection result after the error correction is performed, the information data can be immediately transferred to the host.

In the above description, however, a configuration has been described in which error correction of the PI sequence and error correction of the PO sequence are performed once, but the present invention is not limited to such a configuration. The present invention can also be applied to a correction device that performs correction and error correction of a PO sequence twice or more times.

[Details of Error Calculation Method] Next, the details of the error calculation method according to the present invention will be described.

The unit sector shown in FIG.
EDCi, which is formed from the 1-bit data, and is the EDC of the i-th sector using these data, is represented by the following equation.

Hereinafter, bj is 1-bit data shown in FIG.

[0072]

(Equation 1)

That is, there is no error if the remainder (check syndrome) when the polynomial I (x) calculated by the data is divided by the polynomial g (x) is equal to EDCi (x). .

FIG. 4 is a conceptual diagram showing an array of data processing units in error check processing for 16 sectors in the data configuration shown in FIG. 18 excluding parity check data.

In FIG. 4, according to the fact that the data processing unit is 4 bytes (Byte) in each sector, such data of every 4 bytes is represented by i as a sector number, j as a column number, k is a line number, and data_data_
Expressed as ijk. Here, i, j, and k are positive integers, respectively, where 0 ≦ i ≦ 15, 0 ≦ j ≦ 42, and 0 ≦ k ≦ 11.

FIGS. 5 and 6 are first and second conceptual diagrams showing the order of data arrays processed in the error correction and error checking processes described below.

As described above, as shown in FIGS. 5 and 6, the number of data processing units in one sector for performing error checking is 43 × 12 = 516, and each data processing unit data_ijk is 32 bits ( 8 bits x
4).

With such a code, it is basically possible to perform verification in a DVD format, for example. Hereinafter, error correction for a data structure as shown in FIGS. 5 and 6 will be described.

When a polynomial corresponding to each data processing unit data_ijk is represented by I (i, j, k), EDCi for the i-th sector is calculated by defining the following equation.

[0080]

(Equation 2)

Here, bijkm indicates 1-bit data of the m-th bit from the lower order among the bit data corresponding to the data processing unit data_ijk in the data array shown in FIG.

Therefore, {I (x) mod g
(X) If｝ Exor I (i, 42, 11) is 0, it indicates that there is no error in the i-th sector. Here, it is assumed that the symbol Exor is an operation of performing an exclusive OR operation on coefficients of the same degree of two polynomials and forming a polynomial using the result as a coefficient.

Here, the above calculation is modified using a function fpi for the following polynomial Y.

[0084]

(Equation 3)

Using such a function fpi, the above calculation can be executed as the following iterative calculation.

[0086]

(Equation 4)

Therefore, if F (i, 42, 11) is 0, it indicates that there is no error in the i-th sector.

Here, the operation fpi is represented by the arrow 1 in FIG.
This is equivalent to the calculation for the number. These operations can be executed at high speed by tabulating, for example.

Further, the calculation by the above equation (8) for the i-th sector is performed by the function fp for the following polynomial Y:
It can be deformed by using o.

[0090]

(Equation 5)

For example, it can be modified to the following two types of iterative calculations. i) First type of calculation:

[0092]

(Equation 6)

Ii) Second type of calculation:

[0094]

(Equation 7)

Here, the first type of calculation corresponds to the processing performed by the PO direction partial error check circuit 8 shown in FIG.
The calculation of the type corresponds to the processing performed by the PO direction totaling error check circuit 6.

This is because the PO direction partial error checking circuit 8 calculates a partial syndrome using only the column data shown in FIG. 6, and then, based on the result from the PO direction partial error checking circuit 8, This indicates that error checking can be performed by the direction totaling error checking circuit 6 performing the totaling operation.

In this operation, two types of calculation fpi are used.
The circuit can be configured by using only the fpo and fpo.

Therefore, in FIG.
i indicates an arrow operation in the PI direction, and fpo indicates an arrow operation in the PO direction.

If there is no error in a certain column j, G
Since (i, j, 11) does not need to be calculated and its value is 0, it does not require an extra circuit corresponding to three types of syndrome operations as shown in FIG. It becomes possible to do.

[Process Flow of Error Correction and Error Check]
FIG. 7 is a flowchart for explaining the processing flow of the error correction and the error check described above.

Referring to FIG. 7, when the error correction and error checking processes are started (step S100), the value of control variable CNT is initialized to 0 (step S10).
2).

Subsequently, the value of the variable CNT is incremented by 1 (step S104), and the data buffer 1
4 to the PI direction error correction circuit 10 (step S106), and error correction processing in the PI direction is performed based on the calculated syndrome (step S108).

When the error correction in the PI direction is completed, the PI direction error check circuit 3 subsequently performs a PI direction error check (step S110).

As a result of the error check in the PI direction, the result of the error check in the PI direction for all sectors EDCPIi
It is determined whether (i = 0 to 15) is 0 (step S112). If EDCPIi is 0 as a result of the error check in the PI direction for all the sectors, it is determined that all errors have been corrected, and the process ends (step S122).

On the other hand, if EDCPIi is not 0 as a result of error check in the PI direction even for one sector, data is supplied from the data buffer 14 to the PO direction error correction circuit 12 (step S114).

When the error correction in the PO direction is performed (step S116) and the error correction in the PO direction is completed, the PO-direction partial error checking circuit 8 and the PO-direction totaling error checking circuit 6 subsequently output the PO-direction error. An inspection is performed (Step S118).

As a result of the error check in the PO direction, as a result of the error check in the PO direction for all the sectors EDCPOi
(I = 0 to 15) is 0 and the control variable CNT
Is determined to be 2 (step S120).
If EDCPIi is 0 as a result of the error check in the PO direction for all sectors, it is determined that all errors have been corrected, and when the variable CNT is 2, the processing is completed as if the required number of processings have been completed. (Step S122).

On the other hand, if EDCPIi is not 0 and the variable CNT is not 2 as a result of the error check in the PO direction for all sectors, the process returns to step S104 (step S120).

In the above description, the error correction process in the PO direction is performed after the error check in the PI direction is completed. However, after the error correction in the PI direction is completed, the error correction in the PO direction is performed in parallel. Correction processing may be performed.

Although the error correction and the error check are performed twice, the number of times may be one or three or more depending on the operating conditions of the system.

FIG. 8 is a flow chart for explaining the PI direction error check processing in step S110 shown in FIG.

First, when the PI direction error checking process starts (step S200), the value of a sector number variable i (i: a positive integer) indicating a sector number is initialized to 0 (step S202).

Subsequently, the processing shifts to processing loops LB201 to LE201 for performing EDC inspection for 16 sectors. That is, the processing from the processing loops LB201 to LE201 is repeated until the processing for 16 sectors is performed (loops LB201 to LE201).

First, the sector E corresponding to the i-th sector
The value of the DC value variable EDCPIi is initialized to 0, and the value of the row number variable k is also initialized to 0 (step S204). Here, the sector EDC value variable EDCPIi is a variable for performing the calculation shown in Expression (8).

Subsequently, the processing shifts to a processing loop LB202 to LE202 for performing an EDC check in each sector. That is, the processing from the processing loops LB202 to LE202 is repeated until the processing is performed on all data in the sector (loops LB202 to LE20).
2).

First, the value of the column number variable j is initialized to 0 (step S206). Next, the processing shifts to processing loops LB203 to LE203 for performing processing for each row in each sector. That is, the processing loop LB203 to LE
The processing up to 203 is repeated until all the columns of the data processing unit included in the row of one data processing unit are performed (loops LB203 to LE203).

In the processing loops LB203 to LE203, the PI direction error check circuit 3 reads data every 4 bytes in the PI direction and substitutes it for a variable data_ijk (step S208).

Next, based on the above equation (8), the following calculation is performed: EDCPIi = fpi ｛EDCPi｝ Exor data — ijk (12)

Next, the value of the variable j is incremented by 1, and the processing shifts to the next column of the data processing unit (step S212).

Steps S208 to S208 are executed for all the columns of the data processing unit included in the row of one data processing unit.
The process of S212 is repeated (loops LB203 to LE2)
03).

Next, the value of the variable k is incremented by 1, and the processing shifts to the next line of the data processing unit (step S214).

Until the processing on the data in the sector is completed, the processing of steps S206 to S214 is repeated (loops LB202 to LE202).

When the processing of one sector is completed, the variable i
Is incremented by 1 and the process proceeds to the next sector (step S216), and the process returns to step S202 again. Until the processing for all the sectors is completed, the processing from step S202 to step S216 is repeated (loops LB201 to LE201).

When processing for all sectors is completed, PI
The direction error check processing ends (step S218).

FIGS. 9 and 10 are first and second flowcharts for explaining step S118 of the PO direction error checking process shown in FIG.

First, when the PO direction error checking process starts (step S300), the value of the column number variable j is initialized to 0 (step S302).

Subsequently, the processing shifts to processing loops LB301 to LE301 for performing a partial error check corresponding to all columns. That is, the processing loops LB301 to LE3
The processing up to 01 is repeated until the processing is performed for all columns (loops LB301 to LE301).

First, the value of the sector number variable i is initialized to 0 (step S304). Next, processing loops LB302 to LE30 for performing a partial error check corresponding to each column
The process shifts to 2.

First, the value of the sector EDC value variable EDCPOij representing the sector EDC value for each column and the value of the row number variable k are initialized to 0 (step S306). Here, the sector EDC value variable EDCPOij is a variable for performing the first type of calculation shown in Expression (10). However, as described below, in the processing shown in FIG.
The processing is not performed directly using the data shown in (0), but is simplified using only the error amount.

That is, the processing shifts to a processing loop LB303 to LE303 for performing a partial error check for each sector. (Loops LB303 to LE303).

In the processing loops LB303 to LE303, the PO direction partial error check circuit 8 stores the error amount in the position where an error is detected, the data in which 0 is arranged in other positions, and the PO direction data in the PO direction. The data is read every four bytes and assigned to a variable data_ijk (step S308). If no error is detected in the column to be checked, the processing loops LB302 to LE302 can be omitted.

Next, based on the above equation (10), the following equation is calculated: EDCPOij = fpo ｛EDCPOij｝ Exor data_ijk (13)

The value of the row number variable k is incremented by one, and the processing shifts to the next row (step S312).

Steps S308 to S31 until the processing on the data in the j-th column of the i-th sector is completed.
2 is repeated (loops LB303 to LE303).

When the processing of the j-th column of the i-th sector is completed, the value of the variable i is incremented by 1, and the processing shifts to the next sector (step S314).
The process returns to step S306. Until the processing on the j-th column of the fifteenth sector is completed, step S
The processing from step 306 to step S314 is repeated (loops LB302 to LE302).

When the processing on the j-th column of all the sectors is completed, the value of the variable j is incremented by 1, the processing shifts to the next column (step S316), and the process returns to step S304 again. . Until the processing for the 42nd column is completed, the processing from step S304 to step S316 is repeated (loop LB
301-LE301).

Referring to FIG. 10, loops LB301-LB
After the process in E301 ends, the variable i is reset to 0 (step S320).

Subsequently, the processing shifts to a processing loop LB304 to LE304 for performing a counting error check. That is,
The processing from the processing loops LB304 to LE304 is repeated until the processing is performed for all the sectors (loops LB304 to LE304).

Next, the EDC corresponding to the i-th sector
The value of the value variable EDCPOi and the value of the variable j are initialized to 0 (Step S322).

Subsequently, the processing shifts to a processing loop LB305 to LE305 for performing a counting error check corresponding to each sector.

In the processing loops LB305 to LE305, the PO direction totaling error check circuit 6 calculates and substitutes EDCPOi = fpi ｛EDCPOi｝ Exor EDCPOij (14) in the PI direction based on the above equation (11). Is performed (step S324).

Next, the value of the variable j is incremented by one, and the processing shifts to the next column (step S326).

Steps S324 to S326 are repeated (loops LB305 to LE305) until the processing for all columns of the sector being processed is completed.

When the processing for all the columns in the i-th sector is completed, the exclusive-OR operation unit 5 then performs the operation of EDCPOi = EDCPIi Exor EDCPOi (step S328). Thus, the PO direction determination circuit 4 determines whether or not an error exists in the i-th sector.

The value of the control variable i is incremented by 1 (step S330), the process moves to the next sector, and the process returns to step S322. Until the processing of the last sector ends, the processing from step S322 to step S330 is repeated (loop LB3).
04-LE304).

When the processing of the loops LB304 to LE304 is completed, the processing of error correction and inspection is completed, and the flow proceeds to the next processing (processing step S120 in FIG. 7) (step S320).

[Second Embodiment] As described in the first embodiment, a unit sector to be subjected to an error check is formed from 16512 data (bi) shown in FIG. 19, and these data are used. EDCi for i-th sector
Is represented by equations (1) to (3).

In the first embodiment, when calculating the EDCi (x) represented by the equation (1), the equation (9)
By simplifying the operation from the function fpo defined by the formula (13), the PO-directional partial error checking circuit 8 shown in FIG.
Has been configured to perform the calculation represented by

In the following, for the sake of simplicity, the function fp
The processing performed from o is represented by the following equation (15).

[0150]

(Equation 8)

Here, g (x) is a polynomial of degree 32. Therefore, it is possible to execute equation (15) by using a 33-bit arithmetic unit. However, in the second embodiment, in order to further improve the calculation speed, a table of calculation results for 2 ³² values is prepared in advance, and based on this table, the expression (1) is calculated.
The arithmetic processing corresponding to 5) is performed.

As shown in equation (10), J
For example, the expression represented by Expression (6) is substituted for k (x).

FIG. 11 is a schematic block diagram for explaining a configuration of the PO direction partial error check circuit 8 for realizing the operation with such a configuration.

Referring to FIG. 11, the PO direction partial error check circuit 8 includes an exclusive OR operation circuit 82 receiving the output of the PO direction error correction circuit 12, and an exclusive OR operation circuit 82.
And outputs a calculation result represented by the equation (15) based on a table corresponding to 2 ³² kinds of calculation results for 32-bit data as described above.
And a register circuit 86 for receiving and temporarily storing the output of the table conversion circuit 84.

The exclusive OR operation circuit 82 receives I (i, j, k) (k =
1 to 11) are sequentially received, and the result of the exclusive OR operation with the output of the table conversion circuit 84 one step before, which is held in the register 86, is given to the table conversion circuit 84 again.

That is, it is possible to perform an operation corresponding to the equation (10) by a processing loop including the exclusive OR operation circuit 82, the table conversion circuit 84, and the register 86.

FIG. 12 and FIG. 13 show the P values shown in FIG.
10 is a flowchart for explaining the operations performed by the O-direction partial error checking circuit 8, the register 7, and the PO-direction totaling error checking circuit 6, which are shown in FIGS. 9 and 10 of the first embodiment.
It is a figure contrasted with.

The processing shown in FIG. 12 and FIG.
The difference from the processing shown in FIG. 13 is that the data d supplied from the PO
The value of the variable EDCPOij is updated by the table conversion circuit 84 performing a conversion process on the result of the exclusive OR operation of the data_ijk and the data held in the register circuit 86 by the exclusive OR operation circuit 82. And register 8
6 is performed.

The other points are the same as those of the processing shown in FIGS. 9 and 10, and therefore, the same portions are denoted by the same reference characters and description thereof will not be repeated.

With the above configuration, the PO direction partial error check circuit 8 updates the value of the variable EDCPOij based on a table provided in advance, so that the arithmetic processing is speeded up. There is an effect that the error correction time is shortened.

[Third Embodiment] In the second embodiment, the processing performed by the PO-directional partial error checking circuit 8, that is, the processing represented by the equation (15) is generated based on a result calculated in advance. Conversion circuit 84 for performing arithmetic processing by
Has been described.

In the third embodiment, a description will be given of a configuration for performing the arithmetic processing represented by equation (15) at a higher speed.

The configuration of the decoding circuit according to the third embodiment is
The configuration is basically the same as the configuration of the decoding circuit 147 shown in FIG. As will be described below, the configuration of the PO direction partial error check circuit 8 is different.

That is, in the equation (15), the equation Jk
(X) can be decomposed as in the following equation (16).

[0165]

(Equation 9)

That is, Jk (x) is a 7th-order equation Jk-i
It is possible to divide into four using (x).

Using equation (16), equation (15)
Can be modified as in the following equation (17).

[0168]

(Equation 10)

[0169] Thus, in response to each term of equation (17), the table conversion circuit for performing arithmetic processing of PO direction partial error checking on the basis of previously provided this table the table are two ⁸ as described later is 4 And three exclusive OR operators for performing an exclusive OR operation on the outputs from these four table conversion circuits, it is possible to perform the arithmetic processing.

FIG. 14 is a schematic block diagram for explaining the configuration of PO-direction partial error check circuit 8 having such a configuration.

Referring to FIG. 14, the PO direction partial error check circuit 8 of the third embodiment includes an exclusive OR operation circuit 802 receiving data data_ijk from the PO direction error correction circuit 12, and an exclusive OR operation. A data dividing circuit 804 for receiving the output of the circuit 802 and dividing the data into data of every 8 bits;
Receiving data for each bit respectively, based on Table 2 ^eight which are calculated in advance operation corresponding to each term of equation (17), the table conversion circuit for calculating respective 810,81
2, 814 and 816 and table conversion circuits 810 and 8
12, an exclusive OR operation circuit 820 for outputting an exclusive OR operation result, and a table conversion circuit 81
4 and 816, and outputs an exclusive OR operation result. An exclusive OR operation circuit 822 receives the outputs of the exclusive OR operation circuits 820 and 822, and outputs the exclusive OR operation result. An exclusive OR operation circuit 824 for outputting to the register 7 shown in FIG. 2 and a register 826 for receiving and temporarily storing the output of the exclusive OR operation circuit 824 are included.

Exclusive OR operation circuit 802 receives data data_ijk from PO direction error correction circuit 12 and an output from register 826, performs exclusive OR operation, and outputs the result to data division circuit 804. give.

FIGS. 15 and 16 illustrate the processing performed by PO partial error checking circuit 8 of the third embodiment shown in FIG. 14 and register 7 and PO direction totaling error checking circuit 6 shown in FIG. It is a flowchart for the.

Referring to FIGS. 15 and 16, first, P
When the O-direction error checking process is started (step S40)
0), the value of the column number variable j is initialized to 0 (step S402).

Subsequently, the processing shifts to a processing loop LB401 to LE401 for performing a partial error check on all columns. That is, the processing of the processing loops LB401 to LE401 is repeated until the processing is performed for all the columns (loops LB401 to LE401).

First, the value of the sector number variable i is initialized to 0 (step S404). Next, processing loops LB402 to LE for performing a partial error check corresponding to each column
The processing shifts to 402.

First, the value of the sector EGC value variable EDCPOij representing the sector EDC value for each column and the value of the row number variable k are initialized to 0 (step S406). Here, the sector EDC value variable EDCPOij is a variable for performing the calculation represented by Expression (17). However, similarly to the processing shown in FIG. 9, only the data corresponding to the erroneous row is processed by Expression (17).

Subsequently, the processing shifts to processing loops LB403 to LE403 for performing a partial error check for each sector (loops LB403 to LE403).

In the processing loops LB403 to LE403, the PO direction partial error check circuit 8 stores the error amount in the position where the error is detected, the data in which 0 is arranged in other positions, and the data in each PO direction. Read every 4 bytes,
The data division circuit 804 divides this data into 1-byte units from the beginning. Hereinafter, the divided 1-byte data is represented as variables H1 to H4 (step S40).
8). In correspondence with this processing, the table conversion circuits 810 to 816
Are given values corresponding to the variables H1 to H4, respectively.

The table conversion circuit 810 receives the data corresponding to the variable H1 from the data division circuit 804,
The byte is equal to the value of the variable H1, and the remaining three bytes of bit data are converted into 4-byte values corresponding to all 0s, and are converted and output according to the corresponding table (operation table). The data output from the table conversion circuit 810 is represented as a variable HA (step S410). In response to this processing, the output from the table conversion circuit 810 is provided to the exclusive OR operation circuit 820.

The table conversion circuit 812 receives data corresponding to the variable H2 from the data division circuit 804,
The 1-byte data of the byte is equal to the value of the variable H2, and the remaining 3 bytes of bit data are all converted to 4-byte values corresponding to 0, and converted according to the corresponding table (operation table). Output. This table conversion circuit 8
12 is represented by a variable HB (step S4).
12). In response to this processing, the output from the table conversion circuit 812 is provided to the exclusive OR operation circuit 820.

The table conversion circuit 814 receives data corresponding to the variable H3 from the data division circuit 804,
The 1-byte data of the byte is equal to the value of the variable H3, and the remaining 3 bytes of bit data are all converted to 4-byte values corresponding to 0, and converted according to the corresponding table (operation table). Output. This table conversion circuit 8
14 is represented as a variable HC (step S4).
14). In response to this processing, the output from the table conversion circuit 814 is provided to the exclusive OR operation circuit 822.

The table conversion circuit 816 receives the data corresponding to the variable H4 from the data division circuit 804,
The 1-byte data of the byte is equal to the value of this variable H4, and the remaining 3 bytes of bit data are all converted to 4-byte values corresponding to 0, and are converted according to the corresponding table (operation table). Output. This table conversion circuit 8
16 is represented by a variable HD (step S4).
16). In response to this processing, the output from the table conversion circuit 816 is provided to the exclusive OR operation circuit 822.

Subsequently, the sector EDC value variable EDCPOi
The value of j is calculated by the exclusive OR operation circuits 820, 822, and 824 by the processing of the following equation (18) (step S418).

[0185]

[Equation 11]

The value of the row number variable k is incremented by one, and the processing shifts to the next row (step S420).

Steps S408 to S41 until the processing on the data in the j-th column of the i-th sector is completed.
2 is repeated (loops LB403 to LE403).

Referring to FIG. 16, when the processing of the j-th column of the i-th sector is completed, the value of variable i is incremented by 1, the processing shifts to the next sector (step S422), and again. , The process returns to step S406. Until the processing on the j-th column of the 15th sector is completed, the processing from step S406 to step S422 is repeated (loops LB402 to LE40).
2).

When the processing for the j-th column of all the sectors is completed, the value of the variable j is incremented by 1, the processing shifts to the next column (step S424), and the processing returns to step S404 again. . Until the processing for the 42nd column is completed, the processing from step S404 to step S424 is repeated (loop LB
401 to LE401).

After the processing of the loops LB401 to LE401 is completed, subsequently, the variable i is reset to 0 (step S430).

Subsequently, the processing shifts to a processing loop LB404 to LE404 for performing a counting error check. That is,
The processing from the processing loops LB404 to LE404 is repeated until the processing is performed for all the sectors (loops LB404 to LE404).

Next, the EDC corresponding to the i-th sector
The value of the value variable EDCPOi and the value of the variable j are initialized to 0 (Step S432).

Subsequently, the processing shifts to a processing loop LB405 to LE405 for performing a counting error check corresponding to each sector.

In the processing loops LB405 to LE405, the PO-direction totaling error check circuit 6 calculates and substitutes EDCPOi = fpi ｛EDCPOi｝ Exor EDCPOij (14) in the PI direction based on the above equation (11). Is performed (step S434).

Next, the value of the variable j is incremented by one, and the processing shifts to the next column (step S436).

Steps S434 to S436 are repeated (loops LB405 to LE405) until the processing for all columns of the sector being processed is completed.

When the processing for all the columns of the i-th sector is completed, the exclusive-OR operation unit 5 then performs the operation of EDCPOi = EDCPIi Exor EDCPOi (step S438). Thus, the PO direction determination circuit 4 determines whether or not an error exists in the i-th sector.

The value of control variable i is incremented by 1 (step S440), the process moves to the next sector, and the process returns to step S432 again. Until the processing of the last sector ends, the processing from step S432 to step S440 is repeated (loop LB4).
04-LE404).

When the processing of the loops LB404 to LE404 is completed, the processing of error correction and inspection is completed, and the flow proceeds to the next processing (processing step S120 in FIG. 7) (step S442).

With the above processing, the processing of the PO-directional partial error check circuit 8 can be performed.
Since the O-direction partial error check processing is divided into 8-bit units and a table is used and parallel processing is performed, processing can be performed at higher speed.

Here, in general, the function fpo is defined assuming that the original data is n bits and the number of data divisions is m (m
Is a divisor of n), the size of the table is a size corresponding to 2 ^{(n / m)} data, and the number of tables is m. In addition, the number of exclusive OR operators is (m-1)
Individual. However, it is assumed that one arithmetic unit can perform n-bit arithmetic.

Therefore, by using a table conversion circuit that performs calculations based on the divided tables, the circuit scale can be significantly reduced.

Further, according to the present invention, the access time to the storage element is reduced without increasing the storage element and the circuit scale, and the error check processing is performed in parallel with the error correction processing. Can be shortened.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0205]

According to the present invention, the access time to the storage element can be reduced without increasing the storage element and circuit scale, and the error check processing can be performed in parallel with the error correction processing. Can be shortened.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a disk reproducing apparatus 1000 including an error correction and parallel inspection apparatus according to the present invention.

FIG. 2 is a schematic block diagram for describing a configuration of a decoding circuit 147 shown in FIG.

FIG. 3 is a conceptual diagram illustrating an operation of an exclusive OR circuit 9 in a decoding circuit.

FIG. 4 is a conceptual diagram showing an array of data processing units in an error checking process.

FIG. 5 is a first conceptual diagram showing the order of data arrays processed in error correction and error check processing.

FIG. 6 is a second conceptual diagram showing the order of data arrays processed in error correction and error check processing.

FIG. 7 is a flowchart illustrating a processing flow of error correction and error checking.

FIG. 8 is a flowchart for explaining a PI direction error check process in step S110 shown in FIG. 7;

FIG. 9 is a first flowchart for explaining a PO direction error checking process shown in FIG. 7;

FIG. 10 is a second flowchart for explaining the PO direction error check processing shown in FIG. 7;

FIG. 11 is a schematic block diagram for explaining a configuration of a PO direction partial error check circuit 8;

FIG. 12 is a first flowchart for explaining operations performed by the PO direction partial error checking circuit 8, the register 7, and the PO direction totaling error checking circuit 6;

FIG. 13 is a second flowchart for describing the operation performed by the PO direction partial error checking circuit 8, the register 7, and the PO direction totaling error checking circuit 6;

FIG. 14 is a schematic block diagram for explaining a configuration of a PO direction partial error check circuit 8;

FIG. 15 shows a PO direction partial error check circuit 8 and a register 7;
7 is a first flowchart for explaining a process performed by a PO direction totaling error check circuit 6;

FIG. 16 shows a PO direction partial error checking circuit 8 and a register 7;
7 is a second flowchart for explaining the processing performed by the PO direction totaling error checking circuit 6.

FIG. 17 shows a format of a conventional DVD error correction product symbol.

18 is a diagram showing a relationship between an error correction product code and an error check code (EDC) of the DVD shown in FIG.

FIG. 19 is a diagram showing a data array of one sector including an error check code, in which numbers are assigned in descending order from the first bit.

FIG. 20 is a schematic block diagram illustrating a configuration of a first conventional example for performing error correction and error checking on DVD data.

FIG. 21 is a schematic block diagram illustrating a configuration of a second conventional example.

FIG. 22 is a first conceptual diagram showing a schematic diagram of the processing of the error correction and error checking device shown in FIG. 21;

FIG. 23 is a second conceptual diagram showing a schematic diagram of the processing of the error correction and error checking device shown in FIG. 21;

FIG. 24 is a third conceptual diagram showing a schematic diagram of the processing of the error correction and error checking device shown in FIG. 21;

FIG. 25 is a fourth conceptual diagram showing a schematic diagram of the processing of the error correction and error checking device shown in FIG. 21;

[Explanation of symbols]

Reference Signs List 1 PI direction determination circuit, 2 storage element, 3 PI direction error check circuit, 4 PO direction determination circuit, 5, 9 exclusive OR circuit, 6 PO direction total error check circuit, 7 register, 8 PO direction partial error check circuit , 10 PI direction error correction circuit, 11 storage element, 12 PO direction error correction circuit, 13 data bus, 14 data buffer, 82
Exclusive OR operation circuit, 84 table conversion circuit, 86 register, 141 drive, 142 signal reading circuit, 1
43 servo circuit, 144 control circuit, 145 error correction circuit, 146 error check circuit, 147 decoding circuit,
48 interface circuit, 149 drive drive circuit, 802, 820, 822, 824 exclusive OR operation circuit, 804 data division circuit, 810, 812, 8
14,816 Table conversion circuit, 826 registers.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 572 G11B 20/18 572C 572F (72) Inventor Hideki Yamauchi 2-chome Keihanhondori, Moriguchi-shi, Osaka No. 5-5 Sanyo Electric Co., Ltd. F-term (reference) 5B001 AA13 AB02 AC02 AD06 AE02 5J065 AA01 AB01 AC03 AD02 AD13 AE06 AF01 AF03 AG02 AH04 AH05 AH06

Claims (12)

[Claims] 1. A first direction and a second direction of a data block.
Error correction processing means for performing error correction processing on data to be corrected including an error correction code having a product code capable of correcting an error in the direction of the product code, wherein the error correction calculation means corrects a first direction of the product code A first error correction unit that corrects the second direction, a first storage element capable of storing the data to be corrected, and a first error correction unit that corrects the second direction. Error checking means for performing error checking using an error check code to confirm that the correction by the error check is not an erroneous correction, wherein the error check code includes an error check code that is continuous with data in a first direction of the data block. Wherein the error checking means uses the error amount detected by the error correction in the first direction and the data stored in the first storage element to generate a first error. Inspection First logical operation means for calculating a result, first direction error checking means for performing error checking after error correction in a first direction according to the first error detection result, A second error check result is calculated using the amount of error detected at the time of error correction, and a logical operation is performed on the first and second error check results, so that after the error correction in the second direction, And a second-direction error checking means for performing an error check on the error. A second storage element for receiving and temporarily storing the data to be corrected, wherein the first storage element stores a codeword read from the second storage element. The error correction device according to claim 1, wherein 3. The second direction error checking means calculates a partial check result for each data of the data block arranged in a second direction using an error amount detected at the time of error correction in the second direction. 3. The error according to claim 1, further comprising: a partial error checker that performs a second check result by calculating a plurality of the calculated partial check results in a first direction. 4. Correction device. 4. The error correction device according to claim 3, wherein at least said second error correction means and said first direction error check means operate in parallel. 5. The second direction error checker includes: a third storage element that receives and stores a check result of the first direction error checker; and a first direction that is stored in the third storage element. 4. The apparatus according to claim 3, further comprising: a second logical operation unit configured to perform an error check after the error correction in the second direction in response to the check result of the error check unit and the check result of the total error check unit.
Error correction device as described. 6. The second direction error checking means comprises:
6. The error correction device according to claim 1, wherein an error check after the error correction in the second direction is performed by performing an exclusive OR operation on the result of the second error check. . 7. A first direction and a second direction of a data block.
Receiving error-corrected data including an error-correcting code having a product code capable of error-correcting in the first direction and performing error correction processing in the first direction; Performing an error correction process for a direction; calculating a first error check result by sequentially using the data to be corrected before the error correction and an error amount detected by the error correction in the first direction; Performing an error check after error correction in a first direction in accordance with the first error detection result; and performing a second error check using an error amount detected during error correction in the second direction. Calculating a check result and performing a logical operation on the first and second error check results to perform an error check after error correction in the second direction. 8. The step of performing the error check after the error correction in the second direction includes: arranging the data blocks in the second direction of the data block using an error amount detected at the time of the error correction in the second direction. The method according to claim 7, further comprising: calculating a partial inspection result for each data; and calculating a second inspection result by totalizing the plurality of calculated partial inspection results in a first direction. Error correction method. 9. The step of performing an error check after the error correction in the second direction includes performing an exclusive OR operation of the first and second error check results, thereby obtaining the second direction. 9. The error correction method according to claim 7, wherein an error check after error correction is performed. 10. An operation table showing a correspondence between a predetermined error amount and a partial inspection result using an error amount detected at the time of error correction in the second direction. A partial error checker that outputs the partial check result for each data lined up in the second direction of the data block; and aggregating the plurality of calculated partial check results in the first direction, 3. The error correction device according to claim 1, further comprising a counting error check unit that calculates a second check result. 11. The partial error checking means sequentially receives error data corresponding to the amount of error detected at the time of error correction in the second direction over a plurality of steps, wherein the partial error checking means Exclusive OR operation means for outputting an exclusive OR operation result of the partial test data based on the given error data and the error data given in the current step; receiving the output of the exclusive OR operation means, A table operation means for outputting the partial inspection data based on a preset operation table indicating a correspondence between the error data and the partial inspection data; and receiving and holding the partial inspection data output from the table operation means , In the current step, a data holding means for providing the partial test data in the previous step to the exclusive OR operation means, Serial table calculating means, on the basis of the error data given in the last step, the second said data blocks
The error correction device according to claim 10, wherein the partial inspection result is output for each data lined up in the direction. 12. The table operation means receives the output of the exclusive-OR operation means and divides the data into a predetermined number of groups. The table operation means receives the output of the data division means. A plurality of sub-table operation means for outputting the partial inspection data, based on an operation table indicating a correspondence between the error data and the partial inspection data, and receiving the output from the plurality of sub-table operation means, The error correction device according to claim 11, further comprising a partial check operation unit that outputs check data.