JPS63193722A - Error correction method - Google Patents

Abstract

PURPOSE:To improve the capacity of error correction, by performing quadruple erasure correction in a C2 encoder by using a C1 pointer generated in a C1 encoder. CONSTITUTION:The decoding of an error correction code C1(C1 decode) is performed by finding an error location from a syndrome, and an error pointer(C1 pointer) is set for an error symbol impossible to be corrected by the C1 decode. The decoding of an error correction code C2 after re-interleave(C2 decode) is designated as erasure correction based on the C1 pointer, and furthermore, and a state is converted from a first arranging state to a second arranging state by interleave, and the C1 decode is applied again. Thus, since the erasure correction is used, it is possible to improve the capacity of the error correction and to prevent erroneous correction from being performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction method applied to error correction of a reproduction signal of a digital audio disc (so-called compact disc).

[Summary of the invention]

In this invention, the plurality of symbols in the first arrangement state are encoded with the first error correction code C2,
Through interleaving, the first arrangement state is converted to the second arrangement state, and the plurality of symbols in the second arrangement state are encoded with the second error correction code CI. , Decoding of the error correction code CI (C1 decoding) is performed by finding the error location from the syndrome, and an error pointer (
CI pointer) is set, decoding of the error correction code C2 after deinterleaving (C2 decoding) is performed as erasure correction based on the C1 pointer, and the first array state is further converted to the second array state by interleaving,
C1 decoding is done again. In this invention, since erasure correction is used, error correction capability is improved and erroneous corrections are prevented.

[Prior Art] - The error correction code used in compact discs is called a CIRC correction code (cross-interleaved Reed-Solomon code). In the CIRC correction code, (2
8, 24) The Reed-Solomon code (C2 code) is encoded, and then the data arrangement is changed to the first one by interleaving.
For the 28 symbols that are rearranged from the array state to the second array state and are in the second array state, (32, 28)
Encoding is performed using a Reed-Solomon code (CI code).

When decoding a CIRC correction code, C1 decoding is performed, then deinterleaving complementary to interleaving is performed, and then C2 decoding is performed.

As a decoding method of CfRC correction code, Japanese Patent Application Laid-Open No. 57-1
0557, JP 57-10558, JP 57-10559, JP 57-10560, JP 57-10561, JP 57-2
The one described in Publication No. 4143 is known. Furthermore, as a method for decoding Reed-Solomon codes, Japanese Patent Laid-Open No. 57
-25047 publication.

The one described in JP-A-60-197020 is known. In the conventional (IRc correction code decoding method),
In the first stage C1 decoding, double error correction is performed,
In the next stage of C2 decoding, double error correction is performed with reference to the pointer information obtained in C1 decoding.

As one of the methods for decoding error correction codes, erasure correction is known, in which the error location of an error symbol is indicated by known pointer information, and the error symbol is corrected.

Both the C1 code and C2 code described above can correct up to double errors without erasure, and if erasure occurs, can correct up to quadruple errors. Therefore, in order to improve the error correction capability, erasure correction may be performed, and erasure correction is particularly effective against burst errors. On the other hand, in order to perform erasure correction, it is necessary to know the error location in advance from pointer information, and it is also necessary that the reliability of the pointer information is high.

In the conventional CIRC correction code coding method, the C1 decoder performs double error correction, and there is a risk that a triple error may occur at that time, so the C1 pointer is sent to the next stage C2 decoder, Here, error correction is performed using the C1 pointer. It is possible to improve the error correction capability by performing erasure correction with this C2 decoder.

[Problem that the invention seeks to solve]

In the conventional CIRC correction code, as shown in FIG.
A sequence of one code (C1 sequence) consists of two adjacent frames (1
C2 code series (C2 series)
is 28 included in a given frame within 108 frames.
It is formed by symbols. CI compared to C2 series
Since the interleave length of the series is short, problems occur when frames are dropped and frame continuity is lost during fast-forward playback (cue, review), etc. That is, in ±1 frames before and after the discontinuity point, the CI pointer indicates that there is an error, but in other cases, the C1 pointer indicates that there is no error. On the other hand, since the C2 sequence has an interleave length of 108 frames, the 108 frames including the discontinuous point are no longer a correct C2 sequence. For this incorrect C2 sequence, the above 01
If erasure correction is performed using a pointer, the error correction will be incorrect.

Therefore, an object of the present invention is to provide an error correction method that can obtain the maximum correction ability by erasure correction and prevent erroneous correction when performing error correction of a CIRC correction code. .

[Means for solving problems]

In this invention, a first error correction code (C2 code) capable of erasure correction of m-fold error correction and zero-fold error correction is encoded, and a second error correction code (C1 code) capable of multi-error correction is used. In the error correction method of the error correction code used, for multiple symbols in an interleaved state, the C1 code corrects the error symbols of k or less, and corrects the error symbols of at least more than k. Regarding the step of setting an error pointer and the multiple symbols after deinterleaving, C
2 code to perform erasure correction of n or less error symbols indicated by the error pointer; and regarding a plurality of interleaved symbols, perform correction of k or less error symbols by C1 code. Error correction is performed by setting pointers to at least k error symbols.

[Effect]

In the case of (k=n-2)(m-4), up to quadruple errors are corrected by erasure correction in C2 decoding after C1 decoding, so that error correction capability is improved. Since there is a risk of erroneous correction in erasure correction, C1 decoding is then performed to verify the correction result, thereby making it possible to prevent erroneous correction.

〔Example〕

Examples of the present invention will be described below. This explanation is made according to the following items.

a. Basic method of decoding; Reed-Solomon code erasure correction method C; Reed-Solomon code decoding device d; Modification a. Basic method of decoding An embodiment of the present invention will be described with reference to the drawings. . This embodiment is a method of decoding a CIRC correction code used in compact discs. FIG. 1 is a diagram showing the decoding order as a block diagram.

The reproduced signal from the compact disc is EFM demodulated, 32 symbols in one frame are supplied to delay processing stage 1, only even symbols are delayed by one frame, and the delay given by the encoder side delay circuit is canceled. Ru. The 32 symbols from the delay processing stage 1 are supplied to the C1 decoder 2, where the (32, 28) Reed-Solomon code is decoded. The C1 decoder 2 corrects up to two error symbols in the C1 sequence. In the C1 decoder 2, when triple or more errors are detected, a 01 pointer with an error is set for all symbols in the C1 sequence.

The data corrected by the C1 decoder 2 and the error pointer are processed in the deinterleaving stage 3. The deinterleave processing stage 3 performs processing to restore the interleaving performed on the encoder side, and the output of the deinterleave processing stage 3 is supplied to the C2 decoder 4. The 01 pointer of each symbol generated by the C1 decoder 2 is subjected to the same deinterleaving process as the data at the deinterleaving stage 3. Delay processing and deinterleaving are performed using R
This can be done by controlling the address when reading data from AM. The C1 pointer is written in a part of the memory area of the RAM and is subject to the same address control as the data. The C2 decoder 4 uses the C1 pointer to perform erasure correction up to quadruple errors. In this C2 encoder 4, when erasure correction is completed, the C1 pointer is cleared, and pointer information is not transmitted to the second C1 decoding. In this way, by not transmitting the 02 pointer of the first C2 decoding, the memory area of the RAM for storing the first C2 pointer is not used, and the memory capacity is saved.

Data from the C2 decoder 4 is fed to an interleaving stage 5. The interleave processing stage 5 returns the data arrangement to the same arrangement as the arrangement at the time of reproduction.

The output data of the interleave processing stage 5 is supplied to the delay processing stage 6, and one frame (32 symbols) of data is obtained from the delay processing stage 6. Actually, since the data corrected by the C1 decoding processing stage 2 and the C2 decoding processing stage 4 is stored in the RAM, by controlling the read address of this data, the interleaving processing stage 5 and the delay processing stage 6 can be processed.

The 32 symbols of data from the delay processing stage 6 are supplied to the C1 decoder 7. In C1 decoder 7, (32, 28)
The Reed-Solomon code is decoded, and up to double errors are corrected. In the C1 decoder 7, the C1 pointer is set not only when there are three or more errors, but also when double errors are corrected.

The output data from the C1 decoder 7 is supplied to a deinterleave processing stage 8, where it is deinterleaved. The 28 symbols of data from the deinterleave processing stage 8 are supplied to the C2 decoder 9, where the (28,,24) Reed-Solomon code is decoded. The C2 decoder 9 corrects up to double errors by referring to the number and status of C1 pointers. C2'IJ! , the output data from the encoder 9 is supplied to a descramble processing stage 10, where the scramble processing performed on the encoder side is reversed.

The decoding operation performed by the C1 decoder 7 and the C2 decoder 9 is performed by the C1 decoder 7 and the C2 decoder 9 provided in the compact disc playback circuit.
It is said to be the same as the TRC correction code decoder.

As mentioned above, since quadruple erasure correction is performed in the C2 encoder 4 using the Cl pointer generated in the CI encoder 2, the number of error symbols that can be corrected increases, and the error correction ability can be improved. can. Erroneous corrections caused by erasure correction can be eliminated by performing C1 decoding and C2 decoding again, reducing the possibility of erroneous corrections. 2 is a graph for comparing the error correction capabilities of a conventional CTRC correction code decoder and this embodiment.

The horizontal axis in FIG. 2 is the symbol error probability PS before correction, and the line axis is the word error probability pw before correction. In this embodiment, when uncorrectability occurs, it is indicated by ILA, and as can be seen from a comparison with IIB, which indicates when the conventional CTRC correction code decoder becomes uncorrectable, the correction ability is improved. There is. Further, in the case where an erroneous correction occurs in this embodiment, the result is shown as 12A, and compared to 12B when the conventional decoder is unable to make corrections, it is slightly improved by only a short amount of time.

b. Reed-Solomon code erasure correction method In the case of a Reed-Solomon code, erasure correction can be performed by solving the following equation.

Scy ΣX, νY.

However, sea 0 to d-2 n: number of erasures After correction, the Hamming distance of the C2 code is (d=5). For example, if four error symbols are included, the syndrome will be as follows.

The code length of the C2 code is 28, and for received symbols W0 to 27, if there is an error vector of Yl in WO, then WO=vq.

W2. = Special 27. In other words, if there is one error in W7, (X
+ - α'), then So"YI Sl = α'I YI St = αanyI Sl = α37Y1. The j of x, y, is simply an order of errors in the received data.

For example, the received 28 symbols VJ o −W 2
−.

Among them, Wo, Vs, 'ij/+. If there is an error in the four symbols +W+s, then . =w0+y.

So1wW, +Y2 W. =W. +Y.

W+ll=Wls+Ya. (X
l = α'+X2 = α'+X3"'α", Xa
=α18). Therefore, if there are errors in 4 symbols, S0=, Y, + '/, = 'y', +
YaS+=α0YI +α5Y2 +αtoy3+
α1llY4S2=α0Y, +α1°Y2-4-α20
Y3↓α36Y4S, =αOYl +αl5Y2+α3
This is a syndrome in which 0Y, +α54Y4 is obtained.

Error locations XI to X4 are set by CI pointer,
Since it is known, the error vector Y1~
Y4 is required.

(X44X+) (X4+X2) (X3+X4) (X
3+L)(Xi+Xz) (X3+X4)(Xz+X+
) (XZ+X1) (L+X4) (XI+XZ) (
Xl+X, 3) (L+Xa).

The above erasure correction method uses error vectors Y, -Y
, a total of 84 calculations are required (addition: 40 times, multiplication: 40 times, division = 4 times).

An improved erasure correction that can reduce the number of calculations will be described below.

Syndrome Sv (sea 0 to n-1) and error location Xj (j=1 to n) are sequentially subjected to a product-sum operation according to the following rule, and the i-th answer is set as Sr1.

That is, Sr1. =Sν, i−IXL”Sr1.1−
1 (1≦i≦n−1) However, (Sν, .=Sν).

In this way, by finding SO+n-1, Y and l are found.

Similar to the above, a decoding method when erasure correction is performed on four error symbols (that is, n=4) will be described. First, to 3, l ”'Sit x, +3. jSo, 2
= So, + X2 + St, I] S+, z = S
+, + Xz +Sz, +So, a =So, t
Xs ”S+, t are sequentially determined, and finally S(1, 3/(Xa +x+)(Xa +xz)(Xa
+X3) yields Y4. Using this error vector, the original syndrome is corrected to a triple error syndrome. That is, SO+Y4→S0 s, +X4 Y4→5I S2 + Xa ” Y4-3z The following calculation is performed on this modified syndrome to obtain an error vector Y3.

So+z=30. , Xz "S++'+Y3 =
So, z / (X3 ”XI) (Xa + Xt
) Below, in the same way, the syndrome is corrected and Y2 and Yl
seek.

SO+Y3→S0 S+ +X3 Y:l→S.

So, + = SOXI +51 Yz = So+ 1 / (Xz + X +
) So+Y2 →S0 Y + = S.

The proof of the following theorem for finding the above-mentioned error vector Y, will be described below. In other words, Sν. =Sν
(C0~n-1) S v= t-S
S, i−+ Xt ” Sν+l+ 1−1 (i=1~
n-1, Sv1. When calculated, it is. ”...Theorem 1 (Proof) When i=l, left side=Sν1-8ν,. XI +Sν and 5. .

=2. X,'y,X,+2. X, ν1Y.

= i'x, shiY, (X, +X,) Therefore, (left side = right side) If (i=i) is correct, when (i=i+l), S '+ ,,, = S '+ tXt++ +S '
, I+ i=ΣX, νYi (Xt−+ ”X;
) rT (Xk+X,)j army ◆1 = ΣXjνY, (Xl, l +X,) n (xk+x
, ) (Proof) By substituting shi=O, 1=n-1 into the formula of "Theorem 1", we have found Y, .

C. Reed-Solomon code decoding device A Reed-Solomon code decoder has the configuration shown in FIG. 3, for example. In FIG. 3, an external RAM 22 is connected to an internal data bus indicated by 21 via a write register 23 and a read register 24. Further, the internal data bus 21 includes an arithmetic logic (ALU),
A syndrome register 26 and a working RAM are connected. The external RAM 22 stores data to be decoded, such as data reproduced from a compact disc.

The decoder shown in FIG. 3 has a microprogram system configuration, and microinstructions are stored in the microprogram ROM2
8. The microinstruction provides control signals to each control unit via the register 29. A program counter 30 is provided in association with the microprogram ROM 2B.

The internal state of each part is supplied to the judgment circuit 31, and the judgment circuit 3
A jump destination address generating circuit 32 is provided which generates a jump destination address in response to the output signal 1 and supplies this jump destination address to the program counter 30.

In the decoder shown in FIG. 3, a syndrome is calculated by the ALU 25 from the data read from the external RAM 22, and this syndrome is stored in the syndrome register 26. The ALU 25 is configured to be capable of not only syndrome calculations but also product-sum calculations. Further, the working RAM 27 stores error locations determined by the ALU 25 and intermediate calculation results (SV40, etc.).

FIG. 4 shows the configuration of an example of an ALU provided in the ALU 25 for performing erasure correction. Since the erasure correction process is performed by a sum-of-products operation, the ALU shown in Figure 4
has a configuration in which a multiplier and an adder are connected in cascade.

In FIG. 4, lo connected to the internal data bus 21
g ROM 41 is a ROM that outputs an index i (8 bits) when an element cx' (8 bits) on a Galois field is supplied as an address input.log
The output of the ROM 41 is supplied to the adder 42;
The output of the register 43 is supplied to the register 43, the output of the register 43 is supplied to the inverse logROM 44, and the adder 42
will be returned to. The adder 42 performs addition of exponents, that is, multiplication by α.

When the inverse log ROM 44 is supplied with the index i as an address input, it outputs α゛, and this inverse log ROM 44
The output of is stored in register 47. The output of register 47 is supplied to an exclusive OR circuit (mod 2 adder). The output of the exclusive OR circuit 48 is supplied to a register 49, and the output of the register 49 is fed back to the exclusive OR circuit 48 and also supplied to the internal data bus 21. The exclusive OR circuit 48 performs addition on the Galois field.

Further, FIG. 5 shows the configuration of an ALU that can be used for both erasure correction and error correction, and similarly to FIG. 4, logROM 41. Adder 42, register 43
．． Reverse log ROM44. Register 47. Exclusive OR circuit 48. The register 49 constitutes a product-sum calculation circuit. In double error correction of Reed-Solomon codes, in order to solve the error Roque-Silane equation, the transformation P
LA45 is required. Therefore, in the register 43,
The inverse log ROM 44 and the conversion PLA 45 are connected, and their outputs are supplied to the selector 46. selector 4
6 is the inverse l when performing product-sum calculations such as erasure correction.
In a predetermined step when selecting the output of the ogROM 44 and finding the error location during error correction, the change t
Select the output of APLA45.

d. Modification In this invention, C1 decoding and C2 decoding are performed after erasure correction.
Although both decoding is performed, only one of the decoding may be performed.

〔Effect of the invention〕

According to this invention, by performing erasure correction,
Error ability can be improved.

Furthermore, even if an erroneous correction occurs in erasure correction, the erroneous correction can be detected by the next stage of decoding.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the order of correction processing according to an embodiment of the present invention, FIG. 2 is a graph for explaining the error correction ability of this invention, and FIG. 3 is a Reed-Solomon code that can be used in this invention. 4 is a block diagram of an example of an ALU used in a Reed-Solomon code decoder, and FIG. 5 is a block diagram of another example of an ALU used in a Reed-Solomon code decoder. Block diagram, Figure 6 is CIR
It is a route map used for explaining the code sequence of the C correction code. Description of main symbols in the drawings 2.7: C1 decoder, 4, 9: C2 decoder, 3.8: Deinterleave processing stage, 5: Interleave processing stage.

Claims (1)

[Scope of Claims] A first error correction code capable of m-fold error correction and n-fold error erasure correction is encoded with respect to a plurality of symbols in a first arrangement state, and the plurality of symbols are and the arrangement of the first check symbols of the first error correction code is rearranged into a second arrangement state,
In the error correction method for encoding the plurality of symbols in the second arrangement state and the first check symbol with a second error correction code capable of performing k-fold error correction, the second Regarding multiple symbols in an array state,
Correcting the following number of error symbols using the second error correction code, and setting error pointers for at least k or more error symbols; a step of converting to a first array state; and regarding the plurality of symbols in the first array state,
performing the erasure correction of n or less error symbols indicated by the error pointer using the first error correction code; converting the first arrangement state to the second arrangement state; Regarding the plurality of symbols in the second array state,
An error correction method comprising the steps of correcting the following number of error symbols using the second error correction code, and setting a pointer to at least k error symbols. .