JP2570251B2 - Arithmetic circuit of finite field - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a finite field arithmetic circuit applied to an encoder and a decoder for an error correction code.

[Background technology and its problems]

When recording and reproducing digital video signals, digital audio signals, and the like, adjacent codes, Reed-Solomon codes, and the like have been put into practical use as error correction codes. In these correction code encoders, parity data (redundant data) is generated, and in the decoder, a syndrome is generated from a received word including the parity data, and error correction is performed using the syndrome. A finite field arithmetic circuit is used as hardware of the parity generation circuit, the syndrome generation circuit, and the error correction circuit. The finite field is a field having p ^m elements derived from an irreducible polynomial P (x) of degree m. For an error correction code, (p
= 2) is important, and therefore the present invention provides
(P = 2).

A conventional finite field arithmetic circuit used for an encoder and a decoder performs, for example, (α ⁱ ·
In the case of α ^j ), α ⁱ is input to the ROM to obtain an index i, and similarly, α ^j is input to the ROM to obtain an index j.
(I + j) is generated, the index (i + j) is input to the ROM, and a process of converting the index into αi + j is performed. In the operation of the finite field (GF 2 ^m ), addition (subtraction is the same as addition) can be easily achieved by an exclusive OR gate. And a disadvantage that the circuit scale becomes large. In addition, the conventional finite field operation circuit,
A dedicated hardware is configured for each type of generator polynomial or operation, and lacks versatility.

[Object of the invention]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a finite field arithmetic circuit in which the required amount of memories such as ROMs and registers is reduced and the circuit scale is reduced.

Another object of the present invention is to provide a versatile finite field arithmetic circuit capable of configuring encoders and decoders for various error correction codes such as a Hamming code, an adjacent code, and a Reed-Solomon code. It is in.

[Summary of the Invention]

The present invention converts the first input of m bits in which the element of the finite field GF (2 ^m ) is represented by a vector into each element of a matrix representation, and converts each element of the matrix representation and each element of the finite field GF (2 ^m ). There are two arithmetic circuits for multiplying an m-bit second input whose element is represented by a vector and obtaining a multiplied output of the first and second inputs in a vector representation of a finite field GF (2 ^m ). This is a finite field arithmetic circuit in which the outputs of two arithmetic circuits are supplied to the (mod. 2) adder circuit and the output is obtained from the adder circuit.

〔Example〕

To facilitate understanding of one embodiment of the present invention, GF (2 ^m ) will be described below.

First, the relationship between the generator polynomial g (x) and the element α ⁱ on GF (2 ^m ) will be described. As an example, (g (x) = x ⁴ + x +
1). If the coefficients of the generator polynomial g (x) are written in descending power order, they are (1,0,0,1,1). Corresponding to this coefficient, the shift register circuit shown in FIG. 1A having a feedback loop can be constructed. In FIG. 1A, the adder circuit inserted between the first-stage register and the next-stage register is a (mod. 2) adder circuit.

In this shift register circuit, as shown in FIG.
When (1000) is set as an initial value and the shift operation is sequentially performed, the contents of each register change as shown in FIG. 1B. Here, the root of g (x) = 0 is α (= α ¹ )
In other words, from (α ⁴ + α + 1 = 0), (α ⁴ = α +
1). Therefore, the change in the contents of the register shown in FIG. 1B is represented by a power of α as shown below.

α ⁰ : (1000) α ⁸ : (1010) α ¹ : (0100) α ⁹ : (0101) α ² : (0010) α ¹⁰ : (1110) α ³ : (0001) α ¹¹ : (0111) α ⁴ : (1100) α ¹² : (1111) α ⁵ : (0110) α ¹³ : (1011) α ⁶ : (0011) α ¹⁴ : (1001) α ⁷ : (1101) α ¹⁵ : (1000) α ⁴ or more Originally, using the equation of (α ⁴ = α + 1), α
It is represented as a linear combination of ⁰ , α ¹ , α ² , α ³ . That is, α ⁴ = α + 1 α ⁵ = α · α ⁴ = α ² (α + 1) = α ² + α α ⁶ = α ² · α ⁴ = α ² (α + 1) = α ³ + α ² α ⁸ = α ⁴ · α ⁴ = (Α + 1) (α + 1) = α ² +1. Thus, using the vector representation of alpha ⁰ to? ^3, expressed the alpha ⁴ or more, the same as the content shown in Figure 1 B.

Next, the relationship between α and the matrix T will be described.
The adjoint matrix T is given by (g (x) = x ⁴ + x + 1) It is what becomes. If α ⁱ in FIG. 1B is a vertical vector, there is a relationship of T = [α ¹ , α ² , α ³ , α ⁴ ]. T ² When expressed using α ⁱ , T ² = [α ² , α ³ , α ⁴ ,
α ⁵ ]. That is, T ⁱ = [α ⁱ , α ^{i + 1} , α ^{i + 2} , α ^{i + 3} ]. However, (i = 0,1,2, ... 14), i + 1,
i + 2 and i + 3 take values calculated by (mod. 15). In other words, the first column of T ⁱ is the same as the vector representation α ⁱ of α.

Next, (α ⁱ × α ^j = α ^{i + j} ) will be described. Multiplication between vectors is not possible, but multiplication between matrix and vector is possible. Thus, multiplication is possible by converting α ⁱ into a matrix representation T ⁱ . The multiplication of T and α is From this, in the case of (i = 2) or more, T × α ⁱ = T × α × α ^i-1 = α ² × α ^i-1 = α ^{i + 1} and is generally referred to as (Tα ⁱ = α ^{i + 1} ). I understand.
Conversely, it holds the relationship that ^{α 4 = Tα 3 = T 2} α 2 = T 3 α 1 = T 4 α 0 from the relationship. In general, (α ^{i + j} = T ⁱ · α ^j )
Holds. From these considerations, α ⁱ and T ⁱ can be completely identified at the time of multiplication, and to calculate (α ⁱ × α ^j ),
(T ⁱ × α ^j ) may be calculated.

As described above, since T ⁱ = [α ⁱ , α ^{i + 1} , α ^{i + 2} , α ^{i + 3} ], if another vector can be generated from α ⁱ ,
It means that all of the elements of the matrix T ⁱ is divide,
By multiplying this element by α ^j , (α ⁱ × α ^j ) can be multiplied.

Figure 2 is a matrix representation of the alpha ¹ which is vector representation
Circuit for converting the T ^{1 (where, g (x) = x 4} + x + 1) shows a. In a shift register circuit having a feedback loop shown in FIG. 1A, α ⁱ is set in each register and shifted three times, so that α ^{i + 1} , α ^{i + 2} , α
^{i + 3} can be generated sequentially. Therefore, α ^i, for example, α ¹ is externally input to the four registers 1, 2, 3, and 4 in FIG. 2 to connect the input registers by a connection equivalent to performing three shift operations. each element of each matrix T ¹ to the broken line position in the output and the second view can be a simultaneously generated. That is, the output of the registers 1-4 is set to 1
The bits are shifted downward by one bit, and the most significant bit and the least significant bit after this shift are added to adders 22, 23 and 24 of (mod. 2).
Are added.

FIG. 3 shows the configuration of an arithmetic circuit used in an embodiment of the present invention, in which α ⁱ is supplied as input (a ₀ , a ₁ , a ₂ , a ₃ from LSB). The coefficient g ^{i of} the generator polynomial g (x) is supplied to the cascade connection of the registers 5, 6, and 7, and the coefficients g ₃ , g ₂ , and g ₁ are extracted from the registers 5, 6, and 7, respectively. (G (x) = x ⁴ + x
At the time of (+1), (g ₁ = 1, g ₂ = g ₃ = 0). The coefficient g ₁ is
The coefficient g ₂ is supplied to the AND gates 8, 11, and 14, and the coefficient g ₂ is supplied to the AND gates 9, 12, and
Is supplied to 15, the coefficient g ₃ is supplied to the AND gates 10,13,16.

Outputs of the AND gates 8, 9, and 10 are supplied to exclusive OR gates (hereinafter, abbreviated as EXOR gates) 22, 32, and 42 as one of the inputs. EXO output of AND gates 11, 12, and 13
It is supplied to the R gates 22, 33, 43 as one input. A
The outputs of the ND gates 14, 15, 16 are supplied to EXOR gates 24, 34, 44 as one input. The set of three AND gates for each column is commonly supplied with the MSB from each of the previous columns. The three AND gates in each column always output 0 when the coefficient g ⁱ of the generator polynomial is supplied with 0 and feed back data when the coefficient of 1 is supplied.
Supply to EXOR gate. For example, when (g ₁ = 1, g ₂ = g ₃ = 0), the EXOR gates 22, 23, and 24 operate as adders of (mod. 2), and the other EXOR gates simply pass the input. Just let it.

Therefore, the MSB in the previous row and EXOR gates 22, 23, 24 ……,
Each output of 44 constitutes all the elements of the matrix corresponding to inputs a _{0 to} a ₃ . Elements on the other GF (2 ^m ) that are multiplied by the input converted to this matrix representation are the inputs b ₀ , b ₁ ,
_They are supplied as b ₂ and b _{3 and} are taken into the registers 51, 52, 53 and 54. Multiplication of both, ie Let c ₀ , c ₁ , c ₂ , c ₃ be the outputs of

_{c 0 = T 11 b 0 +} T 12 b 1 + T 13 b 2 + T 14 b 3 c 1 = T 21 b 0 + T 22 b 1 + T 23 b 2 + T 24 b 3 c 2 = T 31 b 0 + T 32 b 1 + T ₃₃ b ₂ + T ₃₄ b ₃ c ₃ = T ₄₁ b ₀ + T ₄₂ b ₁ + T ₄₃ b ₂ + T ₄₄ b _{3 The} above-described multiplication for generating the output c ₀ is performed by the AND gate 61,
62, 63, 64, and the addition is performed by EXOR gates 65, 66, 67
Niyotsu and made, the output of the EXOR gate 67 is stored in the register 101 as c _0.

The multiplication for generating the output c ₁ is performed by the AND gate 71,
72, 73, 74, and addition is performed by EXOR gates 75, 76, 77.
Niyotsu and made, the output of the EXOR gate 77 is stored in the register 102 as c _1. Similarly, the output c ₂ had it occurred form the AND gates 81, 82, 83, 84 and EXOR gate 85, 86, and 87 are stored in register 103, AND gates 91, 92, 93, 94 and EXOR gate 95, output c ₃ had it occurred formed in 96 and 97 register 104
Stored in

As described above, the configuration shown in FIG. 3 performs multiplication of two elements expressed as vectors on GF (2 ^m ), generates a multiplication output, and changes the generator polynomial g (x). It is an arithmetic circuit that can perform

FIG. 4 shows an embodiment of the present invention, in which two sets of arithmetic circuits for performing the above-described multiplication are used. That is, the input of 8 bits, a conversion circuit 17 for generating each element of the matrix T ₁ of the (8 × 8), received through the D flip-flops 18 8
One of the operation circuit by a multiplication gate 19 for multiplying the elements from the input A and the conversion circuit 17 of the bit is configured, a conversion circuit 25 for generating each element of the matrix T _2, the multiplexer 27 through the D flip-flops 26 And the multiplication gate 28 for multiplying the output from the conversion circuit 25 and the element from the conversion circuit 25 constitute the other operation circuit.

The outputs of the multiplication gates 19 and 28 are supplied to an adder 29 (mod. 2) composed of EXOR gates. The output of the adder 29 is taken out as an output C via a D flip-flop 30. At the same time, the output of the adder 29 is
Feeded back to 27.

In the embodiment of the present invention, when the multiplexer 27 selects the input B, an output C of C = T ₁ A + T ₂ B is obtained. When the matrix T _{1 is set} to T ⁰ (unit matrix) and T ₂ is set to T, and the multiplexer 27 selects the feedback data, Is obtained.

The arithmetic circuit shown in FIG. 4 can generate parity of various error correction codes or form syndromes of various error correction codes. That is, the original multiplication of the finite field represented by the vector can be performed without using the memory.

Another embodiment of the present invention will be described with reference to FIG. This example uses two sets of arithmetic circuits shown in FIG.
The parity (redundant bit) of error correction code of data (for example, video data) having 8 bits as one symbol is generated and a syndrome is formed. Data is input / output in 8-bit parallel, and 1 bit is input / output. It is configured as a chip IC circuit.

One of the operation circuit, converter circuit 35A for generating an element of the matrix T _1, the multiplication gate 35B, converter 36A for generating the elements of the matrix T _2, the multiplication gate 36B, multiplication gate 35B and 3
The adder 37 to which the output of 6B is supplied (mod. 2), shift registers 55 and 56, D flip-flops 39, 40, 68, 78, 79 and 8
0, composed of multiplexers 38A, 38B, 59.

The other arithmetic circuit, converter circuit 45A for generating an element of the matrix T _3, the multiplication gate 45B, converter 46A for generating the elements of the matrix T _4, the multiplication gate 46B, multiplication gate 45B and 4
The adder 47 to which the output of 6B is supplied (mod. 2), shift registers 57 and 58, D flip-flops 49, 50, 70, 98, 99 and 10
0, constituted by multiplexers 48A, 48B, 60.

The 8-bit parallel input data DTAi is supplied to a multiplexer 59 via a D flip-flop 68, and the 8-bit parallel input data DTBi is supplied to a multiplexer 60 via a D flip-flop 70. These multiplexers 59 and 60 have 8-bit parallel input data DTCi.
Is supplied through a flip-flop 69. The feedback path from the adder 37 to the multiplication gate 35B includes a path including a multiplexer 38A and a D flip-flop 39, and a path including a multiplexer 38B, a D flip-flop 79, a multiplexer 38A and a D flip-flop 39.
The multiplexer 38B is supplied with input data FBPi from outside in addition to the output of the adder 37. Further, the output of the adder 37 is extracted as output data Pi via D flip-flops 78 and 88. The feedback path from the adder 47 to the multiplication gate 46B includes a path including the multiplexer 48A and the D flip-flop 50, and a path including the multiplexer 48B, the D flip-flop 99, the multiplexer 48A and the D flip-flop 50. The multiplexer 48B is supplied with input data FBQi from the outside in addition to the output of the adder 47. Further, the output of the adder 47 is taken out as output data Qi via D flip-flops 98 and 89.

Each element of the matrices T ₁ , T ₂ , T ₃ , T ₄ generated by each of the conversion circuits 35A, 36A, 45A, 46A is represented by a shift register 55, 56, 57, 58.
Is determined by the 8-bit data supplied from. The shift registers 55, 56, 57, 58 can be loaded by either parallel load or serial load (as shown by the broken lines, four shift registers are cascaded). TCK is a clock for the shift registers 55, 56, 57, 58, and TPLD is a signal for designating one of the above two loading methods.

TM1i, TM2i, TM3iTM4i are supplied as parallel inputs of shift registers 55, 56, 57, 58, respectively.
These parallel inputs are simultaneously input to each shift register by one clock of TCK. Also, at the time of serial loading, using the input path of the mode setting data MDT,
Determine each of the matrices T _{1 to} T ₄ (8 bits × 4 = 32
), And the data is loaded into the shift registers 55, 56, 57, 58 one bit at a time by the clock TCK as indicated by the broken line. The mode setting data MDT is loaded into the 14-bit shift register 105 by the clock MDCK, and is input from the shift register 105 to the mode setting circuit 106. As described later, the mode setting data is 14-bit data including data for defining a generator polynomial, data for controlling a multiplexer, and the like.
Control signals are generated from 6 to each circuit.

Further, as a matrix, 0, T ⁰ (unit matrix) is prepared in addition to the matrix value T ^k expressed as a vector.
The selection of these three types of matrices is D flip-flop 41
Through the 8-bit data TSij passed through. TS
Each matrix is controlled by two bits of ij.
For example, according to two bits TS ₁₀ and TS ₁₁ of the data TSij,
Matrix T ₁ is made with either ^0, T 0, T ^k.

One embodiment of the present invention can be applied not only to an error correction encoder but also to a decoder for error detection and error correction. To enable this decryption, (mod.2)
Adder 108, a match detection circuit 122 composed of EXNOR gates, O
R gates 109, 111, 112, 113, AND gate 110, multiplexers 114, 115, 116, 117, select signal forming circuit 118, and D flip-flops 107, 119, 120, 121 are provided. The output of the multiplexer 115 is output via the D flip-flop 119 as the flag FLAG. The output of the multiplexer 117 is output as data DPQi via the D flip-flop 120. The select signal forming circuit 118 generates a select signal for controlling the multiplexer 117.
Control signals OTS ₀ and CTS ₁ are supplied from outside. OR gate
109, 111, and 112 generate one output if at least one (high level) of the input eight bits is one.

The mode setting data MDT is, as shown in FIG. 6, one bit at a time of falling of the clock MDCK.
Incorporated in 5. As shown in FIG. 7, the mode setting data consists of bits G4, G5, G6, M1, M2, PM3 (2 bits),
QM3 (2 bits), M4, M5, M6, EC are loaded in that order.
Three examples of this mode setting data are shown in FIG. In the first example, one circuit shown in FIG. 5 is used to generate parity of adjacent codes. In the second example, two circuits shown in FIG. 5 are used to generate parity of a Reed-Solomon code. The example of the mode setting data shown in the lower part of FIG. 7 is based on the circuit shown in FIG.
In this case, error correction of adjacent codes or Reed-Solomon codes is performed.

Each bit of the mode setting data MDT will be described.
First, the three bits G4, G5, and G6 determine the generator polynomial. 3 generator polynomials when the bit (G4, G5, G6) is the generator polynomial when the _{(100), G 1 (x) = 1} + x 2 + x 3 + x 4 + x 8 The three bits are (010) and (001)
Each of G ₂ (x) and G ₃ (x) is as follows.

G ₂ (x) = 1 + x ² + x ³ + x ⁵ + x ⁸ G ₃ (x) = 1 + x ² + x ³ + x ⁶ + x ⁸ These three types of generator polynomials are all eight-order primitive irreducible polynomials. Is inappropriate for an error correction code.

The two bits M1 and M2 control the multiplexers 59 and 60, respectively, and select the input data of the D flip-flops 40 and 49. When (M1 = 0), the input data DT
When Ci is selected, when (M1 = 1), the input data DTAi is selected, when (M2 = 0), the input data DTCi is selected, and when (M2 = 1), the input data DTBi is selected. Selected.

The two-bit PM3 determines the feedback path of the output of the adder 37, and the two-bit QM3 determines the feedback path of the output of the adder 47. Assuming that each bit of PM3 is PM30 and PM31, these two bits constitute a feedback path as described below.

When (PM30 = 0, PM31 = 0) Adder 37 → multiplexer 38A → D flip-flop 39 When (PM30 = 1, PM31 = 0) Adder 37 → D flip-flop 78 → multiplexer 38B
→ D flip-flop 39 (PM30 = 0, PM31 = 1) Adder 37 → D flip-flop 78 → D flip-flop
79 → multiplexer 38B → multiplexer 38A → D flip-flop 39 (PM30 = 1, PM31 = 1) Adder 37 → D flip-flop 78 → D flip-flop
88 → external shift register (not shown) → D flip-flop 80 → multiplexer 38B → multiplexer 38A → D flip-flop 39 If the two bits of QM3 are QM30 and QM31, multiplexers 48A and 48B are formed by these two bits. Is controlled, and the following feedback system is constructed.

(QM30 = 0, QM31 = 0) Adder 47 → multiplexer 48A → D flip-flop 50 (QM30 = 1, QM31 = 0) Adder 47 → D flip-flop 98 → multiplexer 48B
→ Multiplexer 48A → D flip-flop 50 (QM30 = 0, QM31 = 1) Adder 47 → D flip-flop 98 → D flip-flop
99 → multiplexer 48B → multiplexer 48A → D flip-flop 50 (QM30 = 1, QM31 = 1) Adder 47 → D flip-flop 98 → D flip-flop
89 → external shift register (not shown) → D flip-flop 100 → multiplexer 48B → multiplexer 48A →
D flip-flop 50 These feed-back paths are switched by adder 37 and
The delay element (D flip-flop) inserted when the output of 47 is fed back is switched to one, two, three, four or more stages (determined by the number of external shift registers). This corresponds to the interleave length of the error correction code.

Bit M4 of the mode setting data MDT is
16 and the coincidence detection circuit when (M4 = 0)
When the output of 122 is selected and (M4 = 1), the output of D flip-flop 98 is selected.

The bit M5 is for controlling the multiplexer 114. When (M5 = 0), the output of the OR gate 111 is selected by the multiplexer 114. When (M5 = 1), the output of the OR gate 109 is selected. Selected.

M6 is composed of two bits, M60 and M61, for controlling the multiplexer 115 as follows.

When (M60 = 0, M61 = 0), the output of the AND gate 110 is selected. The flag FLAG at this time is regarded as an error correction completion flag.

When (M60 = 1, M61 = 0), the output of the OR gate 113 is selected. The flag FLAG at this time is an error detection flag.

When (M60 = 0, M61 = 1), the output of the multiplexer 114 is selected.

When (M60 = 1, M61 = 1), the output of the OR gate 112 is selected.

The output of the multiplexer 115 is output via the D flip-flop 119 as the flag FLAG. A decoder is constructed by cascading two arithmetic circuits shown in FIG. In this case, the first-stage arithmetic circuit is used for syndrome generation, and the second-stage arithmetic circuit is used for error position detection and error correction. For syndrome generation, if an error is detected in one of the D flip-flops 78 and 98,
Bit M6 causes multiplexer 115 to select the output of OR gate 113 so that an error detection flag is raised. To use for error correction, bits (M60 = 0, M61 = 0) are set, and an error correction completion flag is output.

One bit EC of the mode setting data is used together with two bits OTS1 and OTS0 supplied from outside to form a select signal for controlling the multiplexer 117. Further, the output (D110) of the AND gate 110 is supplied to the select signal forming circuit 118. With these four bits, the output data DPQi of the multiplexer 117 is as shown in the table below. Here, D107 is the output of D flip-flop 107,
D78 is the output of the D flip-flop 78, D98 is the output of the D flip-flop 98, D108 is the output of the adder 108, and / means either 0 or 1.

In the case of the adjacent code, D107 is the input data DTCi itself, D78 is the output data (parity) Pi, and D98
Is output data (parity) Qi, and D108 is data after error correction.

In one embodiment of the present invention, when two parities of adjacent codes are generated, the 14-bit mode setting data MD is used.
T is set to (010000000 //// 1) as shown in FIG. With the mode setting data MDT, the circuit configuration shown in FIG. 5 can be represented as an equivalent circuit shown in FIG. Figure 10 infra Figure 8 and, in Figure 12, represents the conversion circuit 35A and the multiplier gate 35B as a matrix multiplication circuit 35 of the matrix T _1, Similarly, other matrix T _2, T
_3, with respect to T _4, it is represented as a matrix multiplication circuit 36,45,46.

By the (G4 = 0, G5 = 1 , G6 = 0), the generator polynomial is set to _{(G 2 (x) = 1} + x 2 + x 3 + x 5 + x 8). Further, α ⁻¹ is loaded into the shift register 55,
The shift register 58 is loaded with α. Anything may be loaded into the shift registers 56 and 57. The parity check matrix H which generates the parity P and Q for the five sample data W1 to W5 in such a setting is shown below.

V = [W1W2W3W4W5PQ] received 5 sample data
When its transposed matrix V ^T the product of the parity Chie poke matrix H described above (H · V ^T) parity so becomes zero P, Q are determined. It was but connexion by ^{P = T -5 W1 + T -4} W2 + T -3 W3 + T -2 W4 + T -1 W5 Q = T 5 W1 + T 4 W2 + T 3 W3 + T 2 W4 + TW5, parity P, Q are given.

FIG. 9 is a time chart for generating the parity P, Q. Data processing is performed in synchronization with the clock (time ti) synchronized with the sample data. Five samples of data are supplied as input data DTCi, and this data is generated from D flip-flop 69 as output data D69. Outputs D40 and D49 of D flip-flops 40 and 49, respectively
Is one clock late. The contents of the matrices T _{1 to} T ₄ are as shown in the figure. D flip flop 39,7
The outputs D39 and D78 of 8 are W1, T ^- 1W1 + W2, T ^- 2W1 + T ^- 1W2 + W3, ...
.., And the parity P expressed by the above equation occurs.
Similarly, outputs D50 and D98 of D flip-flops 50 and 98 are W
^{1, TW1 + W2, T 2} W1 + TW2 + W3, ...... and changed, parity Q represented by the above formula occurs. These parities P and Q are
Multiplexers 117 are sequentially selected by the control signal OTSi and added to the output data D107 of the D flip-flop 107, so that the output data DPQi includes the parity P and Q.

The reason why the matrices T ₁ and T ₄ are set to 0 at the clock time t ₂ is to reset the feedback loop in which the parity occurs to zero. At time t ₇ and t _8, the matrix T _2, T ₃ is a 0 is to cut off the undefined data in the input data (indicated by /).

A case in which parity of a Reed-Solomon code is generated by using two arithmetic circuits (having a one-chip IC configuration) shown in FIG. 5 to which the present invention is applied will be described. This 2
One of the two arithmetic circuits is supplied with (100000000 //// 1) 14-bit mode setting data MDT as described in the second row in FIG. Is the seventh
As described in the third line of the figure, (100111
The mode setting data MDT of 14 bits (111 //// 1) is supplied. FIG. 10 shows an equivalent circuit for generating parity of the Reed-Solomon code, 131 is an arithmetic circuit to which the former mode setting data is supplied, and 132 is an arithmetic circuit to which the latter mode setting data is supplied. Circuit.

By (G4 = 1, G5 = 0 , G6 = 0) to generator polynomial is set to _{(G 1 (x) = 1} + x 2 + x 3 + x 4 + x 8). Further, regarding the arithmetic circuit 131, the shift register 55
Then, α ⁻¹ is loaded, and α is loaded into the shift register 58. Anything may be loaded into the shift registers 56 and 57. As for the arithmetic circuit 132, the shift register 5
5 is loaded with α ²⁰⁷ , the shift register 56 is loaded with α ²⁰⁵ , the shift register 57 is loaded with α ²⁰⁵ , and the shift register 58 is loaded with α ²⁰⁷ .

As described above, the parity check matrix H when the generator polynomial is set is shown below.

Here, when the ^{KP = T -6 W1 + T -5} W2 + T -4 W3 + T -3 W4 + T -2 W5 KQ = T 6 W1 + T 5 W2 + T 4 W3 + T 3 W4 + T 2 W5, 2 two parities P, Q are satisfy the following equation Is what you do.

KP + T ^-1 P + Q = 0 KQ + TP + Q = 0 Solving this for parity P and Q, P = (T + T ^-1 ) ^-1 (KP + KQ) Q = (T + T ^-1 ) ^-1 (TKP + T ^-1 KQ) Among them, the first-stage arithmetic circuit 131 to which input data is supplied generates KP and KQ represented by the previous equation, and the second-stage arithmetic circuit 132 generates a parity from this KP and KQ.
P and Q are generated. FIG. 11 is a time chart when generating the parity P and Q of the Reed-Solomon code. The upper half of FIG. 11 is a time chart for explaining the operation of the arithmetic circuit 131, and the lower half thereof is an arithmetic circuit. It is a time chart of the operation explanation of 132.

Output D Output D78 and D flip flop 98 of the D flip flop 78 at time t ₈ the clock in the Fig. 11
Reference numeral 98 is as shown below in the same manner as in the case of the parity P and Q of the adjacent codes described above.

^{KP 1 = T -5 W1 + T} -4 W2 + ...... + T -1 W5 KQ 1 = T 5 W1 + T 4 W2 + ...... + T 1 W5 also, until time t _8, the matrix multiplication circuit 35, along with being a T ^-1 , matrix multiplication circuit 46, since there is a T ^1, at time t ^9, change to the next data.

KP 2 = T ^-6 W1 + T ^-5 W2 + T ^-4 W3 + T ^-3 W4 + T ^-2 W5 KQ 2 = T ⁶ W1 + T ⁵ W2 + T ⁴ W3 + T ³ W4 + T ² W5 That is, the data KP and
KQ. These data KP 1, KP 2, KQ 1 and KQ 2 are supplied to the operation circuit 132 at the next stage. Also, the input data is output to the next-stage arithmetic circuit 132 via the D flip-flop 120.

The data KP 1 and KP 2 are supplied to the matrix multiplying circuit 36 via D flip-flops 68 and 40 and to the matrix multiplying circuit 46 via D flip-flops 100 and 50. The data KQ 1 and KQ 2 are supplied to the matrix multiplying circuit 35 via D flip-flops 80 and 39 and to the matrix multiplying circuit 45 via D flip-flops 70 and 49. Matrix T ₁ and T ₄ of these matrix multiplication circuits 35 and 46 is always set as _{T 1 = T 4 = (T} + T -1) -1 · T = T 207. Matrix T ₂ and T ₃ of the matrix multiplication circuits 36 and 45 is always set as _{T 2 = T 3 = (T} + T -1) -1 · T -1 = T 205. By setting the matrix in this manner, the parity P, Q is calculated as shown by the following equation.

P = (T + T ⁻¹ ) ⁻¹ (KP + KQ) = (T + T ⁻¹ ) ⁻¹ · T ⁻¹ · T KP + (T + T ⁻¹ ) ⁻¹ · T · T ⁻¹ KQ = (T + T ⁻¹ ) ⁻¹ · T ^-1 · KP 1 + (T + T ^-1 ) ^-1 · T · KQ 1 Q = (T + T ^-1 ) ^-1 (T KP + T KQ) = (T + T ^-1 ) ^-1 · T · KP 2 + (T + T) ^-1 ) ^-1 · T ⁻¹ · KQ _{2 In} FIG. 11, data KP 1 and KQ 1 are
Since the input 2 and KQ 2 More above, parity P is generated at time t ₁₂ from the D flip-flop 78, at the next time T _13, parity from D flip-flops 98 Q
Occurs. Then, as shown in FIG. 11, the control signal CT
Si is switched and parity P
And Q are added to the data, and the D flip-flop
The output data D120 of 120 is data including these parities.

A case where error correction of a Reed-Solomon code is performed using two arithmetic circuits shown in FIG. 5 to which the present invention is applied will be described. One of the two arithmetic circuits has a seventh
As described in the fourth column in the figure, (100000000 /
/ 101) mode setting data MDT is supplied, and to the other side, (1001100001/0
01) The mode setting data MDT is supplied. FIG.
An equivalent circuit when a Reed-Solomon code error correction circuit is configured is shown. Reference numeral 141 denotes an arithmetic circuit to which the former mode setting data is supplied, and 142 denotes an arithmetic circuit to which the latter mode setting data is supplied.

G ₁ (x) is set as the generator polynomial. Arithmetic circuit 141
For, α ⁻¹ is loaded into the shift register 55,
Α is loaded into the shift register 58. Shift register
Regarding 56 and 57, there is no need to set the data to be loaded. As for the arithmetic circuit 142, α
^-1 is loaded, alpha ⁶ in the shift register 56 is loaded, alpha ^-6 is loaded into the shift register 57, alpha is loaded into the shift register 58.

Error correction is based on the syndrome SP, SQ
, The detection of error correction using the syndromes SP and SQ, and the correction of error data. The arithmetic circuit 141 calculates the syndromes SP and SQ, and the arithmetic circuit 142 detects an error position and corrects error data. The time chart of the arithmetic circuit 141 is shown in FIG. 13A, and the time chart of the arithmetic circuit 142 is shown in FIG. 13B.

As shown in FIG. 13A, the received data is input to the arithmetic circuit 141 and appears from the output D69 of the D flip-flop 69. .., W5, P, Q, the syndromes SP, SQ corresponding to the two parities are generated by the following equations.

SP = T ^-6 W1 + T ^-5 W2 + T ^-4 W3 + T ^-3 W4 + T ^-2 W5 + T ^-1 P + Q SQ = T ⁶ W1 + T ⁵ W2 + T ⁴ W3 + T ³ W4 + T ² W5 + TP + Q To generate this syndrome, the matrix T ₁ is T ^-1 and the matrix is T ₄ and is T, multiplied by these matrix data, is performed by performing the accumulation. The syndrome SP is obtained as output data D78 of the D flip-flop 78, and the syndrome SQ is obtained as the output data D78 of the D flip-flop 98.
Obtained as D98. The received data is supplied via a D flip-flop 120 to an arithmetic circuit 142 at the next stage via an external six-stage shift register 143 for delaying one block.

Since the mode setting data M6 is (10), the multiplexer 115 selects the output of the OR gate 113,
The output D119 of the D flip-flop 119 is output to the outside. It is OR gate 109 whether the syndrome SP is 0 or not.
And whether the syndrome SQ is 0
It is detected by the OR gate 111. If there is no error in the received data, (SP = SQ = 0), and the output of the OR gate 113 also becomes 0. However, if there is an error in the received data, the syndrome SP or SQ does not become 0, and the output of the OR gate 113 becomes 1. Therefore, output D119 is
This is an error flag indicating the presence / absence of an error in the received data. The arithmetic circuit 142 receives the syndromes SP and SQ,
Find the error location and error pattern ei. At this time,
Instead of using the syndromes SP and SQ as they are, they are transformed as shown in the following equation.

SP ′ = T ⁶ SP SQ ′ = T ⁻⁶ SQ T ⁻¹ and T ^{1 respectively for} the syndromes SP ′ and SQ ′ after this deformation.
Are sequentially multiplied, (T ⁻¹ ) ⁱ SP ′ = (T ¹ ) ⁱ SQ ′ = ei holds, whereby the error position i and the error pattern ei are obtained. The reason why the syndromes SP and SQ are multiplied in advance by T ⁶ and T ^{-6 is} to enable error positions to be sequentially detected without changing the time series of the received data. If the code is not a Reed-Solomon code but an adjacent code, instead of T ^-6 and T ⁶ ,
T ^-5, the T ⁵ may be multiplied to each syndrome.

As shown in FIG. 13B, the data from the arithmetic operation circuit 141 appears as outputs D60, D70, D69 of the D flip-flops 68, 70, 69, and further passes through the D flip-flops 90, 40, 49 to form the D flip-flops. The syndrome SP included in the output D40 of 40 is input to the matrix multiplication circuit 36, and the syndrome SQ included in the output D49 of the D flip-flop 49 is input to the matrix multiplication circuit 45. Matrix multiplication circuit
Matrix T ₂ of the 36 is a T ^6, the matrix T ₃ matrix multiplication circuit 45 is a T ^-6. Therefore, the outputs D78 and D39 of the D flip-flops 78 and 39 are SP'T- ¹ SP ', T
^-2 SP ', ..., T ^-6 SP', and the outputs D98, D50 of the D flip-flops 98,50 are SQ ', T ¹ SQ', T ² S
Q ′,..., T ⁶ SQ ′.

Output data D6 of D flip-flops 69, 90 and 107 respectively
9, D90 and D107 are received data from the preceding operation circuit 141, which are delayed by one clock. output data
D69 is because it is Yotsute 1 block delay shift register 143 at time t _11, the syndrome SP, the input timing of the SQ, the input timing of the first sample data of the data delay is simultaneous.

In FIG. 13B, the sample data W2 of the received data
And the assumption that there is an error pattern e2, the was but ^{connexion, SP = T -5 e2 SQ =} T 5 e2 ^{becomes, SP '= T 6 SP =} Te2 SQ' = T -6 SQ = T -1 e2 from the output D144 of the comparison circuit 144 at ^{T -1 SP '= TSQ' =} e2 become time t ₁₄ becomes 1 from 0.

This comparison circuit 144 corresponds to the coincidence detection circuit 12 shown in FIG.
2, an AND gate 110, a multiplexer 115, a select signal forming circuit 118, and the like. When the above equation holds, the outputs of the match detection circuit 122 are all 1 and the output of the AND gate 110 is 1. The output of the D flip-flop 98 at the time t _14, the error pattern e2
The error pattern e2 is supplied to the adder 108 via the multiplexer 116. On the other hand, since the data received from the D flip-flop 107 is supplied to the adder 108, the adder 108 performs error correction of (W2 + e2) = (W2 + TSQ). Since the error-corrected sample data is selected by the multiplexer 117, the output data of the D flip-flop 120 and the error-corrected received data are obtained. The data D119 selected by the multiplexer 115 and output from the D flip-flop 119
(FLAG) indicates the completion of error correction.

[Application example]

By using the six arithmetic circuits shown in FIG. 5 to which the present invention is applied, an encoder or a decoder of an adjacent code or Reed-Solomon code having four parities and capable of correcting two symbol errors is configured. You can also.

〔The invention's effect〕

According to the present invention, the original multiplication of a finite field represented by a vector can be performed without using a memory, and the circuit scale can be reduced. This invention has excellent versatility,
An encoder or a decoder for a plurality of types of codes such as an adjacent code and a Reed-Solomon code can be formed, which is suitable for an IC circuit.

[Brief description of the drawings]

FIG. 1 is a schematic diagram used to explain the relationship between an element on a finite field and a matrix expression, FIG. 2 is a connection diagram of a conversion circuit for converting data expressed in a vector into each element of a matrix expression,
FIG. 3 is a block diagram of an example of an arithmetic circuit which can be used in one embodiment of the present invention, FIG. 4 is a block diagram of one embodiment of the present invention, and FIG. 5 is a block diagram of another embodiment of the present invention. FIGS. 6, 6 and 7 are waveform diagrams and schematic diagrams used to describe mode setting data in this embodiment, and FIGS. 8 and 9 constitute an encoder of adjacent codes according to this embodiment. Block diagrams and time charts used to explain the time,
FIGS. 10 and 11 are a block diagram and a time chart used for describing an encoder for a Reed-Solomon code according to this embodiment, and FIGS. 12, 13A and 13B are diagrams of this embodiment. Reed-Solomon code (or adjacent code) as usual
FIG. 2 is a block diagram and a time chart used for explanation when configuring the decoder of FIG. 1,2,3,4 …… Register to store one input data, 51,5
2,53,54 …… Register that stores the other input data, 101,1
02,103,104 …… Register for storing output data, 17,25,35
A, 36A, 45A, 46A ... A conversion circuit for generating each element of the matrix, 19, 28, 35B, 36B, 45B, 46B ... Multiplication gates, 27, 38A,
38B, 48A, 48B, 59, 60, 114, 115, 116, 117... Multiplexer, 29, 37, 47, 108 (mod. 2) adder, 122.

Claims (1)

(57) [Claims] 1. A selecting means for selecting one of m-bit input data and feedback data in which an element of a finite field GF (2 ^m ) is represented by a vector based on a selection signal determined by operation contents, The input data for generating the matrix of
A state in which each element of the first matrix is converted based on a coefficient of a generator polynomial of the first matrix element, first conversion means that can be set to any state of 0 or a unit matrix, First operation means for performing a matrix operation on the output data of the selection means and input data for generating a second matrix;
A state in which each element of the second matrix is converted based on the coefficients of the generator polynomial, a second conversion means that can be set to any state of 0 and a unit matrix, A second multiplying means for performing a matrix operation with the elements of the second matrix; an addition operation of an output of the first multiplication means and an output of the second multiplication means; A finite field arithmetic circuit comprising an adding means for giving the feedback data to the selecting means.