KR930005439B1 - Reed solomon encoding circuit of optical recording and reproducing system - Google Patents

Abstract

The circuit simplifys encoding process by using PROM and miniaturizes an encoding system by reducing the numbers of registers and exclusive OR gates. The circuit also alters the contents of the PROM easily. It includes a PROM (904) for multiplying operation of each stage of the RS encoder, the 1st/2nd registers (906/907) for reading/abstracting Q1 data according to buffer-read-signal (BRDSEC) and Q1/Q2 read-signal (Q1RD/Q2RD), the 3rd register (908) for reading/abstracting P data, a MUX (909) for selecting/generating Q1 or Q2 data according to FIRST control signal, and the 2nd buffer (913) for generating zero data (ZERO).

Description

RS encoding circuit of optical record reproduction system

1 is a block diagram of a conventional error correction circuit.

2 is a conventional C1 (32, 28) RS encoding circuit diagram

3 is a conventional C2 (28, 24) RS encoding circuit diagram.

4 is a conventional RS encoding calculation result table.

5 is an GF (2 ⁸ ) alpha operation table.

6 is a block diagram of a conventional CIRC encoder.

7 shows an encoding circuit according to the invention.

8 is an operation waveform diagram of each part according to the present invention.

9 is a list table diagram of a pyrom according to the present invention.

* Explanation of symbols for main parts of the drawings

901,902,911: 11-13 Latch 903,905,910: 1-3 Adder

904: Pyrom 906-908: 1-3 Register

909 MUX 912-913 buffer 1-2

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a Read Solomon (RS) encoder in an optical recording / reproducing apparatus. In particular, the present invention relates to a PROM for encoding (28, 24) RS codes and (32, 28) RS codes used in compact discs. The present invention relates to an RS encoding circuit that can easily change the coefficients of the generated polynomial using.

In general, a compact disc system uses an error correction system based on a CIRC (Cross Interleave Read Solomon Code) method to correct an error due to scratches or dust on a disc. This CIRC type error correction system can correct long burst errors by performing cross interleaving by giving different delays of symbols between Reed Solomon encoding circuits with powerful random error correction capability. . The circuit for correcting such errors is shown in FIG. 1 and the operation thereof is omitted since it is described in detail in Patent Application No. 90-12212.

FIG. 2 is a conventional C1 (32, 28) RS encoding circuit diagram, and FIG. 3 is a conventional C2 (28, 24) RS encoding circuit diagram, wherein the RS code used here is an error correction for performing operations in units of bytes. Code is a kind of BCH code. Therefore, the operation of the conventional RS encoder for error correction will be described with reference to FIGS.

When there is an information message, you can express it as a polynomial.

D (x) = d _k-1 ㆍ X ^k-1 + d _k-2 X ^k-2 + ······· + d ₀ x ⁰

Where x is a dummy variable

This polynomial is generated by a generator polynomial such as

Divide by to get the quotient and the remaining R (x).

D (x) ÷ G (x) = Q (x)... R (x)

If this is expressed mathematically, it is as following Formula (2).

D (x) x ^3-k = G (x) G (x) + R (x), where nk is the order of the generated polynomial

That is, C (x) = D (x) x ^nk + R (x) = Q (x) G (x)... … … … … … … (2)

In other words, the message with the remainder divided by the generator polynomial into the information message is called codeword C (x), and the sender transmits this message.

The receiver will receive data r (x) mixed with errors when this message is sent over the transport channel. If this is expressed mathematically, it is as following Formula (3).

r (x) = C (x) + E (x)... … … … … … … … … … … … … … … … (3)

Substituting the root of the generator polynomial into α ¹ ,

r (α ¹ ) = C (α ¹ ) + E (α ¹ ) = Q (α ¹ ) .C1 (α ¹ ) + E (α ¹ )

That is, r (α ¹ ) = E (α ¹ ).

This is called Syndrom, and if the Syndrom value is all 0, it means that no error occurred. If it is not 0, it indicates that an error occurred during the transmission process. In order to correct an error, an error location and an error value must be known, so two variables, that is, a syndrome value, are required to correct an error.

That is, in the case of one error correction, two syndromes r (α ⁰ ) and r (α ¹ ) are required, and G (x) = (x + xα ⁰ ) (x + α ¹ ).

2가지를 사용하고 있다Currently, compact discs use two error-correcting codes, or four parity-generating codes. The generator polynomial

I use two things

This is called the C2 (28, 24) RS code and the C1 (32, 28) RS code.

In other words, the C2 (28, 24) RS codes are assigned to 28 pieces of codewords with 4 pieces of parity attached to 24 pieces of data. The C1 (32, 28) RS code has four parities of 32 datawords in 28 datasets. Here, the generated polynomial and the general encoder circuit are shown in FIG. 2 and FIG.

In addition, the C2 RS encoder of FIG. 3 separates the two encoders in consideration of the data sequence encoded as shown in FIG. 1 to obtain the final result as an Exclusive Boa circuit.

01=01H, 0F

08=07H, 1B

09=12H로 된다.Therefore, as shown in Fig. 4, the data in the P encoding circuit is 01, 08, 09... If inputted in order, the deflip-flop (FF1) value of FIG. 2 is 00H, 00

01 = 01H, 0F

08 = 07H, 1B

09 = 12H.

4 is a value obtained by simulating the final result obtained by continuously inputting data from 0 to 23 up to 108 frames in one frame in the error correction block diagram of the CD system of FIG.

The feedback value thus obtained is stored in each register (P ₀ , P ₁ , P ₂ , P ₃ ) by adding the value passed through the multiplier (M1-M4) and the value stored in the order immediately below.

That is, P (3) value is 0F + 08 = 07 when feedback value is 08 for data input.

P (3) = Feedback Xα ⁷⁵ + All P (2)

36=2D

36=1B가 된다.= 07Xα ⁷⁵

36 = 2D

36 = 1B.

At this time, the 07Xα ⁷⁵ value should be performed by the GF (2 ⁸ ) operation, which can be performed by referring to the GF (2 ⁸ ) table of FIG. In other words, multiplication is performed by checking the power of 07 to restore the hexa value after exponential multiplication. For example, in the case of 07Xα ⁷⁵ , it can be seen that 07 = α ₁ ⁹⁸ in the α ⁿ table of hexa (Hexa) value in FIG. 5B.

Thus, it can be seen that α ₁ ⁹⁸ X α ⁷⁵ = α ^273-255 = α ¹⁸ = 2D is an α ¹⁸ → 2D hexadecimal table in FIG. 5A. In this way, the multiplication is converted into an exponential form, and after exponential addition, if this value is greater than 256, it is subtracted by 255 so that it can be found in the alpha table.

6 is a block diagram of a CIRC encoder that has been previously filed. The controller 100 inputs a system clock (8.643MHZ) to provide a signal required for the system, and inputs audio data to a control signal of the controller 100. A buffer 200 for loading data onto a data bus, an offset counter 300 for inputting a symbol clock output from the controller 100 and counting an offset value within one frame, and from the controller 100. A frame counter 400 for counting one frame unit by counting by the output frame clock, a counting output offset value of the offset counter 300, and a select value under control of the controller 100. Frame count 500 for determining the amount of delayed frames for encoding on the basis of the current frame by inputting? And counting outputs from the offset counter 300. An offset table 600 for inputting a set value and a select value controlled by the controller 100 to generate an offset address in one frame, a frame counting value of the frame counter 400, and the frame table ( An adder 700 for generating a frame address by adding the frame table value selected at 500), a RAM 800 temporarily storing audio data and encoded parity data, and data read from the RAM 800; Encoder 900 for inputting data in synchronization with the data latch clock and under control of the controller 100 to load data on the data bus by ECC logic generating parity and the ECCOUT signal controlled by the controller 100. The first latch 1000 latches and outputs the encoded data in the RAM 800 in synchronization with the EFM latch clock in the data section. The latch according to the synchronization data to the EFM encoding is completed in the parity latch clock interval consists of the second latch 1100 to the inverting output.

When C1 and C2 encoding is performed in the CIRC block diagram, that is, when the conventional circuit diagram such as 2-3 is used when decorating ECC logic, the size of the system is increased by using many exclusive ora gates and registers. There was this.

Accordingly, an object of the present invention is to provide an RS encoding circuit which can be miniaturized by greatly reducing the registers and exclusive orages required in each calculation process by using PROM for C1 and C2 encoding.

Another object of the present invention is to implement a multiplier for multiplying the coefficients of the generated polynomial of the encoder by using a PROM, RS encoding for compact discs as well as RS encoding that can easily change the contents of the PROM even when using other generated polynomials. In providing a circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

에 의해 저장하고, 최상위차수와 최하위차수를 선택하기 위한 버퍼리드 신호(BRDSEC)와 Q2리드 신호에 의해 Q2데에타를 독출하는 제2레지스터부(907)와, 상기 제2가산기(905)에서 가산된 P데이타를 입력하여 최상위 비트 최하위 비트를 선택하기위한 버퍼라이트 선택신호(BWRSEC)와 P라이트 신호에 의해 저장하고, 최상위비트와 최하위 비트를 선택하기위한 버퍼리드 선택신호(BRDSEC)와 P리드신호

에 의해 P데이타를 독출하는 제3레지스터부(908)와, 상기 제2-3레지스터부(906-907)에서 독출된 Q1, Q2데이타를 입력하여 Q데이타 리드 신호

에 의해 인에이블되고 First 제어신호에 의해 Q1, Q2 데이타를 선택출력하는 MUX(909)와, 상기 2-3레지스터(906-907)에서 독출된 Q1, Q2패리티 데이타를 입력하여 가산하는 제3가산기(910)와, 상기 제3가산기(910)에서 가산된 Q1, Q2패리티 데이타를 입력하여 Q데이타 라이트 제어신호

에 의해 래치시키는 제13래치(911)와, 상기 제13래치(911)의 Q패리티 데이타와 제3레지스터부(908)에서 출력된 P패리티 데이타를 입력하여 ECC출력 제어 신호에 의해 선택적으로 출력하는 제1버퍼(912)와, 상기 제12래치(902)와 제2가산기(905)에 연결되어 초기 클리어시나 최하위 차수 연산시 또는 패리티 데이타 쉬프트시에 제로데이타 제어신호에 의해 제로데이타를 발생하는 제2버퍼(913)로 구성된다.7 is an encoder circuit diagram according to the present invention, including the eleventh latch 901 for selectively inputting P, Q1, and Q2 data to latch in synchronization with the data latch clock, and the highest order P, Q1, Q2. 12th latch 902 for selectively inputting data and latching the data latch clock in synchronization with the data latch clock, and data latched at the eleventh latch 901 and data latched at the twelfth latch 902 are added. A buffer light selection signal for selecting the highest order and the lowest order by inputting a first adder 903 and a feedback value of the first adder 903 respectively to detect feedback values of respective P, Q1 and Q2 data ( C (x) = D (x) x ^{n × k} + P (x) = Q (x) G (x) is satisfied by the data selection signal (DESELECT) for selecting P, Q1, and Q2 data. PROM (PROM) 904 for multiplying each stage of the RS encoder for multiplication and multiply operation in the PROM 904 Input the second adder 905 for adding the P, Q1, and Q2 data of the previous state to each mode, and the Q1 data added by the second adder 905; And a first data which is stored by the buffer write signal (BWRSEC) and the Q1 write signal for selecting the lowest order and the Q1 data is read by the buffer lead signal (BRDSEC) and the Q1 lead signal for selecting the highest order and the lowest order. A buffer write signal (BWRSEC) and a Q2 write signal for selecting the highest order and the lowest order by inputting the register section 906 and the Q2 data added by the second adder 905.

A second register unit 907 for storing Q2 data by the buffer read signal BRDSEC and the Q2 lead signal for selecting the highest order and the lowest order, and the second adder 905 Input the P data added from and store the buffer write selection signal (BWRSEC) and P write signal for selecting the most significant bit and the least significant bit, and the buffer lead selection signal (BRDSEC) and P for selecting the most significant bit and least significant bit. Lead signal

Q data read signal by inputting the third register portion 908 to read P data by the second data and the Q1 and Q2 data read out from the 2-3 register portions 906-907.

MUX 909 enabled by the first control signal and selectively outputting the Q1 and Q2 data by the first control signal, and a third adder for inputting and adding the Q1 and Q2 parity data read out from the 2-3 registers 906-907. 910 and the Q data write control signal by inputting the Q1 and Q2 parity data added by the third adder 910.

The 13th latch 911 latched by the latch, the Q parity data of the 13th latch 911 and the P parity data output from the third register unit 908 to be selectively output by the ECC output control signal. A zero data connected to the first buffer 912, the twelfth latch 902, and the second adder 905 to generate zero data by a zero data control signal at the time of initial clear, lowest order calculation, or parity data shift; It consists of two buffers 913.

When explaining the present invention based on the above configuration.

First, the 1-3 register sections 906-908 have 4 bytes of memory and have an input address and an output address.

Therefore, each of the 1-3 register units 906 to 908 performs the same operation as that of four registers in the conventional encoder of FIG. That is, the 1-3 register units 906 to 908 may select register input / output functions from P0 to P3 by an address for selecting each register unit.

In addition, the operation of the encoder according to the present invention is operated sequentially by the control signal of the controller 100 of FIG. Therefore, the audio data is first read from the external audio interface circuit and written to the RAM 800 of FIG. 6, and then the encoded data from the RAM 800 is read and sent to the external EFM circuit. Will perform.

Now, when the operation of each step of the Q1 encoding is described, the first latch 901 for inputting data to be Q1 encoded from the RAM 800 is latched in synchronization with the data latch clock signal.

At the same time, the second latch 902 for inputting data reading Q1 (3) data of the most significant register of the first register 906 latches Q1 (3) Data in synchronization with the data latch clock signal. The latched data of the 11th-12th latch 902 is added and output by the first adder 903.

The data added and output by the first adder 903 is input to the pyrom 904, from which the Q1 (2) data of the first register unit 906 is read and the second data is obtained from the feedback data obtained by the first adder 903. In addition to multiplying the α ⁷⁵ multiplier in FIG. 1, the result is stored in the buffer Q1 (3) of the first register 906. In this case, the multiplier PROM includes a first multiplier for determining the type of data including the coefficients α ⁷⁵ , α ²⁴ , α ⁷⁸ , α ^{6 to be} multiplied by the buffer write signal BWRSEC, and Q1, Q2, and P by the data selection signal DSElect. It consists of a table like 9 degrees.

Therefore, a value obtained by multiplying the previous order data value and the feedback value is added by the second adder 905 and stored in the high order buffer of the first register unit 906. And since the term of the last order has no low order value to be added, it is calculated by adding zero data generated in the second buffer 913.

As described above, the calculation of the Q1 data is performed, and the Q2 data is also stored in the second register unit 907 in the same manner as the above-described Q1 data.

신호에 의해 Q1이나 Q2데이타가 선택되어 Q데이타 리드신호(QWR)에 의해 MUX(909)에서 선택출력되어 피드백된다.At this time, previous Q1 and Q2 data fed back to ECCBUS during Q1 and Q2 encoding period are

Q1 or Q2 data is selected by the signal, and the MUX 909 is selectively outputted and fed back by the Q data read signal QWR.

에 의해 ECC버스로 피드백시켜 연산을 수행하게 된다.On the other hand, P data is calculated in the same manner as the data of Q1 and Q2 described above, and P data stored in the third register unit 90 is converted into P data read signal.

By feeding back to the ECC bus to perform the operation.

As described above, the operation is performed to store the Q1 and Q2 parity data and the P parity data in the 1-3 register units 906-908.

The P parity data stored in the third register 908 is buffered and output from the first buffer 912 by an ECC output signal ECCOUT. Also, the Q1 and Q2 parity data stored in the 1-2 register units 906-907 are added by the third adder 910. The signal added by the third adder 910 is applied to the thirteenth latch 911 and latched out by the Q data write signal QWR.

The latch output signal from the 13th latch 911 is applied to the first buffer 912 to buffer the output by the ECC output signal RCCOUT.

Such an operation is performed on each control signal generated by the controller 100 of FIG. 6, and a timing diagram of each control signal is shown in FIG. 8.

As described above, in the error correction system of the compact disc, the RS encoder is implemented using pyrom, so that the hardware can be miniaturized and the coefficient of the generated polynomial can be freely changed during RS encoding.

Claims (1)

In an encoding circuit of an optical recording / reproducing apparatus, an eleventh latch 901 for selectively inputting P, Q1, and Q2 data to latch in synchronization with a data latch clock, and the highest order P, Q1, and Q2 data. Is selectively inputted to latch the data latch clock in synchronization with the twelfth latch 902 and the latched data from the eleventh latch 901 and the latched output from the twelfth latch 902, respectively. A buffer write selection signal (BWRSEC) for selecting the highest order and the lowest order by inputting a feedback value of the first adder 903 and the first adder 903 respectively to detect feedback values of P, Q1, and Q2 data RS encoder to satisfy C (x) = D (x) x ^nk + P (x) = Q (x) QG (x) by the data selection signal (DSELECT) for selecting P, Q1 and Q2 data. PROM (PROM) 904 for multiplying each stage of < RTI ID = 0.0 >,< / RTI > The second-order adder 905 for adding the P, Q1, and Q2 data of each order according to each mode, and the Q1 data added by the second adder 905 to input the highest order. And the buffer read signal (BWRSEC) and Q2 write signal (Q1WR) for selecting the lowest order and the buffer read signal (BRDSEC) and Q1 lead signal for selecting the highest and lowest order.

The first register 906 for reading Q1 data and the Q2 data added by the second adder 905 to select the highest and lowest order buffer light signals (BWRSEC) and Q2 lights. Buffer lead signal BRDSEC and Q2 lead signal for storing by the signal Q2WR and selecting the highest order and the lowest order

The second register unit 907 for reading the Q1 data and the P data added by the second adder 905 to select the lowest order of the highest order and the buffer write selection signal (BWRSEC) signal

Buffer read select signal (BRDSEC) and P-lead signal for storing by

Inputs the third register 908 for reading P data and the Q1 and Q2 data read out from the second and third registers 906-907, thereby providing a Q data read signal.

MUX 909 enabled by the first control signal and selectively output by the first control signal, and a third adder 910 for inputting and adding Q1 and Q2 parity data read out from the second register 906-907; The Q data write control signal is input by inputting the Q1 and Q2 parity data added by the third adder 910.

The 13th latch 911 latched by the second latch, and the Q parity data of the 13th latch 911 and the P parity data output from the third register unit 908 to be input.

A zero data control signal connected to the first buffer 912, the twelfth latch 902, and the second adder 905, which are selectively outputted by the controller;

And a second buffer (913) for generating zero data by means of the encoding circuit.

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