KR910009094B1 - Galois field arithmetic unit - Google Patents

Abstract

No content.

Description

[Name of invention]

Galois Computing Equipment

[Brief Description of Drawings]

Figure 1a is a block diagram showing a first embodiment according to the present invention,

FIG. 1B is a flowchart showing the operation of the first computing means utilized in the first embodiment of FIG. 1A,

FIG. 1C is a flowchart showing the operation of the second computing means, the third computing means and the fourth computing means adopted in the first embodiment of FIG. 1A,

1d and 1e are flow charts showing the operations of the fifth and sixth computing means adopted in the first embodiment of FIG. 1a,

Figure 2a is a block diagram showing a second embodiment according to the present invention,

FIG. 2B is a flowchart showing the operation of the first computing means and the seventh computing means adopted in the second embodiment of FIG. 2A,

FIG. 2C is a flowchart showing the operation of the second computing means, the third computing means and the fourth computing means adopted in the second embodiment of FIG. 2A,

FIG. 2D is a flowchart showing the operation of the fifth and eighth calculation means adopted in the second embodiment of FIG. 2A,

3 is a circuit diagram showing a syndrome generating circuit.

Detailed description of the invention

[Technical Field]

The present invention is used to record and reproduce data through a medium such as an optical disk, and even for a code system having a large minimum distance or a hamming distance, for example, The present invention relates to a common error detection and correction device that can efficiently perform an accurate correction for an error whose location is not known using an external pointer and an erasure correction for an error whose location is known.

[Background]

In recent years, data recording and reproducing apparatuses utilizing optical discs have been actively developed. Compared with a magnetic disk, an optical disk memory can store a larger amount of data, but such a recording medium has a problem that a high raw error rate is involved.

Therefore, in order to solve the problems associated with such an optical disc memory, a check code is added to the information code as data at the time of a recording operation, and the codeword recorded as an error detection and correction code on the optical disc. It is generally known to form a code word so that an error in the information code is detected and corrected using a check code added during the reproduction operation.

As such error detection and correction code, Reed solomon code, which has a hamming distance (or minimum distance) set to about 17, that is, d = 17, is drawing attention.

In the case of using the lead-solomon code, since parity computation is performed by encoding data as an encoding operation, data is written to the medium together with parity, and thus the data from the medium is used. After decompressing, perform decoding operation on the data, such as syndrome computation, error number calculation, error location polynomial coefficient calculation, error location operation, and error value operation. Run in a sequential manner.

In this case, for a typical correction for a position unknown error, the number of correctable errors is (d-1) / 2, and in the case of an erase correction for a position known error, the number of correctable errors is d- 1 In addition, if L error positions are known and an unknown position exists, errors where the maximum number (t) of unknown error positions (t) is t = (dL-1) 2 + L are known to L error positions. Can be corrected with errors.

Meanwhile, Ji. G. David Forne Jr. is used to obtain a modified syndrome (Tk) in his book `` On Deceding BHC Codes '', IEEE Trans.IT-11, pages 549 to 557, 1965. Introduced the calculation method of i and L, but the algorithm to get the error value is quite complicated. An example of an algorithm is described in section A of page 553, which calculates the coefficients of an error location polynomial along with an error location obtained by using a pointer by obtaining an unknown error location based on a modified syndrome. Next, by obtaining an error value for an unknown error position, an error value corresponding to the error position specified by the pointer is obtained.

In general, since recursive or repetitive operations are easily applied to the erasing algorithm, when frequent product cods are used, error detection is performed by combining codes having short distances using one of the combined codes. Erase correction is performed using the other of the combined codes, and it is easier to perform the erase correction after obtaining the error position even for long distances. As described above, a method of obtaining an error value when an error in which an error location is known and an error in which an error location is unknown has been presented in a book. However, it is known that since the minimum distance or hamming distance of the code increases, the amount of calculation greatly increases, so that realtime correction cannot be performed in practice. In addition, even if hardware for increasing the operation speed is provided, the circuit amount is increased too much, which causes a problem that the practicality is lowered.

[Detailed Description of the Invention]

Therefore, an object of the present invention is to provide a galoi-based computing device which solves the above problems by performing the calculation at high speed and minimizing the amount of hardware.

In order to achieve the above object, according to the present invention, S ₀ consists of elements belonging to the galoi system GF (2 ^r ), and for error correction of a linear code having a hamming distance d, S _0. To a modified syndrome T _k (T ₀ ... D _d-20L ) by using the syndrome of S _d-2 and L known error positions (X ₀ to X _L-1 ). Use the procedure in David von II's book to calculate the point of unknown error.

σ_i,j×S_i를 활용하여 중간결과 p_j를 얻고, 통상적 교정시와 같은 교정 신드롬을 활용하여 에러치를 연산함으로써 중간치(Y_L,L…Y_L+t-1,L)를 얻으며, 이러한 에러치의 중간치와, 포인터가 지정하는 에러위치(X_i)와, 중간결과(P_j)를 활용하여, Y_i,j=

Y_i,j+1/(X_i+X_j)를 연산한다.From the calculated σ _{i, j} , p _j =

The intermediate result p _j is obtained by using σ _{i, j} × S _i, and the intermediate value (Y _{L, L} … Y _{L + t-1, L} ) is obtained by calculating an error value by using the same calibration syndrome as in the case of normal calibration. Using the intermediate value of these error values, the error position (X _i ) specified by the pointer, and the intermediate result (P _j ), Y _{i, j} =

_Calculate Y _{i, j + 1} / (X _i + X _j ).

Subsequently, obtained by assuming that Y _{i, j + 1} / (X _i + X _j ) = Y _{i, j} in the equation for obtaining Y _{j-1, j-1} when _j-1 . By substituting the operation result of the right side and the operation result (Y _{j, j} ) of the left side, the error value Y ₀ . Y _L-1 ... Obtain Y _{L-1 + j} .

According to the present invention, when encoding or decoding the Reed-Solomon code by using the above procedure, the syndrome for the codeword is calculated, and then a predetermined error position and pointer indicated by one point for one error are calculated. Iterative arithmetic operations including sequential multiplication, division, and addition of the Galois system are performed on the known error positions, and error corrections including encoding or erasing of check codes are performed.

Since the number of operations of such a procedure is significantly reduced compared with the conventional method, such a procedure can be utilized when real-time arithmetic processing is required, and the amount of circuit which enables the arithmetic processing can be considerably hidden. do

Best Mode for Carrying Out the Invention

Referring now to the drawings, a gallon based computing device according to an embodiment of the present invention will be described.

1A is a block diagram of a first embodiment of the present invention. FIG. 1B is a flowchart showing the operation of the first computing means utilized in the first embodiment of FIG. 1A. 1C is a flowchart showing the operation of the second computing means, the third computing means and the fourth computing means adopted in the first embodiment in FIG. 1A. 1D and 1E are flowcharts showing the operation of the fifth calculating means adopted in the first embodiment of FIG. 1A. In Fig. 1A, reference numeral 52 denotes a syndrome generating circuit, and reference numeral 53 denotes a codeword memory circuit.

Reference numeral 54 denotes a Galois-based calculation circuit which executes Galois calculations at high speed utilizing a microprogram. In addition, the signal detection circuit inherent in the optical disk drive detects a dropout for the error position specified by the pointer. The error position is written into the codeword memory circuit 54 via the input / output bus in a vector representation with the value of the error position counter operating in accordance with the code recording format during decoding.

3 is a circuit diagram showing the syndrome generating circuit in detail.

The circuit of FIG. 3 includes a logical multiplication circuit (1), an input switching switch logic circuit (2), and a 0-th 8-bit recording circuit to a 5-th 8-bit recording circuit that emit a total 8-bit output signal. (3 to 8), the 15-th 8-bit recording circuit 18, the 0-th switch logic logic to the fifth switch logic logic 19 to 24, the 15th switch logic circuit 34, and α ⁰ to α ⁵ galoi-based multiplication circuits 35 to 40. Reference numeral 51 denotes a Galois addition circuit (exclusive OR logic sum gate circuit).

In FIG. 3, the sixth to fourteenth circuit components are omitted. Next, the operation of the syndrome generating circuit will be described.

In this embodiment, the operation is performed within the range of GF 2 ⁸ . First, the received word sent from the decoder circuit is sent to and stored in the codeword memory circuit 53 for the decoding operation.

The received word is then sent from the codeword memory circuit 53 to the syndrome generating circuit 52. Prior to this, the initial value setting operation by the logical product gate circuit 1 and the input changeover switch logic circuit 2 is executed, so that the contents of the 8-bit recording circuits 3 to 18 are zero.

Next, the received word of n symbols from the decode circuit accumulated in the codeword memory circuit 53 is input to the logical multiplication circuit 1 via the data terminal.

The AND gate circuit 1 is operated when data is supplied from the data terminal. The output signals of the AND gate circuit 1 are sent to the Galois addition circuit 51 (exclusive OR logic unit), and at the same time, the input changeover switch circuit 2 is switched so that the AND signal from the AND gate circuit 1 Output signals are added to the multiplication result values fed back from the galoi system multiplication circuits 35 to 50, thereby completing the input operation for the n symbols.

Next, the contents of the 8-bit recording circuits 3 to 18 are selected through the switch-switch logic circuits 19 to 34 to obtain syndromes S ₀ to S ₁₅ .

In the present embodiment, since the lead-solomon code whose hamming distance d is d = 17 is adopted, the number of syndromes is d-2, that is, 15 symbols. The syndromes S ₀ to S ₁₅ are supplied to the gallo-based computation circuit 54. The galley calculation circuit 54 includes first to sixth calculation means. The first calculating means receives the known error number of positions X ₀ to X _L-1 from the codeword memory circuit 53 as a pointer, calculates σ _{i, j} and stores the result of the calculation. The value of _{i, j} is used to obtain the modified syndrome T _k and the error value Y _{j, o} during the operation.

The operation of the first computing means is shown in detail as the flowchart of FIG. 1b.

In the second calculating means, the modified syndrome T _k is calculated based on the value of σ _{i, j} obtained from the first calculating means and the syndrome protruding from the syndrome generating circuit 52. The operation of this second computing means is shown in detail in part 55 of the flowchart of FIG. 1C.

In the third calculation means, the error position polynomial σ _t (z) and the error calculation polynomial η _t (z) are obtained from the calibration syndrome determined by the second calculation means. The operation of this third calculating means is shown in the flowchart 56 of FIG. 1C. Further, the fourth calculating means is used to obtain the unknown error position number X _L ... X _{L + t-1} from the error position polynomial σ _t (z) determined by the third calculating means, and this operation is performed in FIG. Corresponds to part 57 of the flowchart.

The fifth calculating means substitutes the error positions obtained by the fourth calculating means into the error calculation polynomial η _t (z) to obtain an intermediate value of the error values (Y _{L, L} ... Y _{L, L + t-1} ). Operation corresponds to portion 58 of the flow chart of FIG. 1B.

The sixth calculating means is used to calculate the error value Y _{i, o} from the intermediate value of the error value and σ _{i, j} obtained by the first calculating means by the fifth calculating means, and the operation of the sixth calculating means 1d and 1e are shown.

Parts 59 of the flowchart of FIG. 1E and portions 59 of the flowchart of FIG. 1D show the processing of the error values Y _{i, o} by 1/2, respectively. Reference numeral 60 denotes a flowchart portion for performing a final error correction. During such arithmetic processing, error position numbers are converted from vector corresponding values to power values, and an address inherent in the codeword memory circuit 53 is added to an error value calculated to read an error symbol, and then the codeword memory circuit It is written to the same position of 53.

The operation of the first embodiment of the present Galois computing device configured as described above will be described in detail with reference to FIGS. 1A to 1E and 3. Here, it is assumed that there are a total of nine error values for a desired error value Y _{j, o} as errors of J = 8 to 6 for an unknown error position and j = 5 to 0 errors for a known error position. Let's do it.

j

L이고, j

i

0이며, 하기식의 우변상 아래에 쓴 기호가 다르지 않으면 이에 대응하는 변수는 0이라는 조건하에서, σ_i,j=1라고 가정하면, σ_i,j=σ_i,j-1×X_j-1+σ_i-1,j-1에서j는 0부터 L까지 가변하고, 각각의 j 및 i값이 상기 조건하에서 가변할때, 순차적으로 연산처리를 실행함으로써, 결과 σ_i,j를 기억시킨다.About J0

j

L, j

i

Assuming that σ _{i, j} = 1, σ _{i, j} = σ _{i, j-1} × X _{j- J in 1} + σ _{i-1, j-1} varies from 0 to L, and when the respective j and i values vary under the above conditions, the operation is executed sequentially to store the result σ _{i, j} .

For this reason _, when calculating σ _{i, j ,} it is necessary to adopt the values of σ _ij-1 and σ _{i-1D, j-1} obtained in the previous calculation process, and these sigma _{i, j} cannot calculate the error value. Because it is necessary.

σ_i,j×S_k+1의 변형된 신드롬에 대한 연산을 실시하고, 변형된 신드롬(T_k)를 미지의 에러위치수에 대한 에러의 통상적 에러교정시의 신드롬과 동일하게 취급함으로써, 유클리드디코딩알고리듬(Euclid decoding algorithm)을 통하여 미지의 에러위치수들에 대응되는 t개의 에러들용 에러위치 다항식 σ_t(z)과 에러치중 중간치의 에러산정 다항식 η_t(z)을 얻는다.Next, T _k = for k values in the range of 0 to d-2-L, based on σ _{i, j} and syndrome obtained as above.

By performing the operation on the modified syndrome of sigma _{i, j} × S _{k + 1} and treating the modified syndrome T _k in the same way as the syndrome at the time of normal error correction of the error for the unknown error position number, Euclid Through the decoding decoding algorithm, the error position polynomial σ _t (z) for t errors corresponding to the unknown error position numbers and the error estimation polynomial η _t (z) of the intermediate values are obtained.

Next, the error position is obtained through the Chien's algorithm, and then the number of error positions from the error position polynomial is added to the error position polynomial σ _t (z) and the error estimation polynomial η _t (z). By assigning and calculating, the error value is determined from the flowchart 59 by obtaining the intermediate value Y _{L + t-1, L} ... Y _{L, L.}

Of the above calculations, the expression for each value utilizes the following.

here,

here,

here

here,

here,

here,

Here, the intermediate value of the 0-th error value (Y _0,0 ) is obtained, and other error values, that is, the 1-th error value to the 8-th error value are obtained simultaneously as in the following equation.

σ_i,j×S_i라고 가정한다. 상기한 바와 같이, Y_j,0를 얻기 위해서, L-1로부터 0까지의 j범위에서 Y_j,j의 연산을 실행한다.Often in these operations, P _j =

Assume σ _{i, j} × S _i . As described above, in order to obtain Y _{j, 0} , the calculation of Y _{j, j} is performed in the j range from L-1 to 0.

Y_i,j+1/(X_i+X_j)+

×σ_i,j×S_i에 따라 실행하는 경우, Y_i,j+1의 연산결과, 즉 최대치 L-1에서 0까지의 j범위에서 Y_j,j에 대한 이전의 연산처리중 j+1에 대응한 Y_i,j=Y_i,j+1/(X_i+Y_j)를 활용해야 한다.In order to obtain an error value, the Y _{j, j} operation is performed in the same manner as in the operation of sigma _{i, j} , that is, Y _{i, j} =

Y _{i, j + 1} / (X _i + X _j ) +

When executing according to × σ _{i, j} × S _i , the result of the calculation of Y _{i, j + 1} , i.e., j + 1 during the previous calculation process for Y _{j, j} in the j range from the maximum value L-1 to 0 Corresponding to Y _{i, j} = Y _{i, j + 1} / (X _i + Y _j ).

After calculating the next Y _{i, j + 1} / (X _i + Y _j ), the result is stored in memory in any case so that the contents of that memory can be protruded when the update value is rewritten during subsequent processing. .

It is convenient for the above calculation process to be a sequential operation. The new result of Y _{j, j} obtained as above is also written to memory.

The error value when j = 0 obtained as a result of the above repetitive operation, that is, Y _j, ^± is stored in the memory.

In the operation for obtaining an error value, the previously determined sigma _{i, j} are again projected and used for the calculation.

In the calculation of Y _{j, j} , it is often effective to obtain a product of 1 / (X _i + Y _j ) by utilizing a reproduction ROM. With reference to the following drawings, a galoi system as a second embodiment according to the present invention will be described. Figure 2a is a block diagram of a second embodiment according to the present invention. FIG. 2B is a flowchart showing operations of the first and seventh computing means in the second embodiment, and FIG. 2C is a flowchart showing the operations of the second computing means, the third computing means and the fourth computing means in the second embodiment. As a flowchart, in principle, it is the same as the flowchart of FIG. 1C, but the part 55 of the flowchart of FIG. 2C is not executed because the operation on the calibration syndrome T ₀ has already been completed. FIG. 2D is a flowchart showing the operation of the fifth calculating means and the eighth calculating means in the second embodiment.

In Fig. 2A, reference numeral 52 denotes a syndrome generating circuit, which is the same as that shown in Fig. 3, and reference numeral 53 denotes a codeword memory circuit. Reference numeral 62 denotes a Galois-based calculation circuit which executes Galois-based calculations at high speed utilizing a microprogram.

In FIG. 2B, the first calculation means and the seventh calculation means are combined to utilize σ _{i, j} in the first calculation means and are held in the recorder, and then multiply by S _i to correct for the intermediate value P _j . Compute and store the syndrome T ₀ .

Also, in FIG. 2C, a calibration syndrome (T ₁ ,..., T _dL-2 ) is obtained by a method similar to that utilized in FIG. 1C, and then an Euclidean decoding method indicated by reference numeral 56 is executed to perform an unknown. An error position polynomial (σ _t (Z)) corresponding to t errors with respect to the number of error positions of? And an error scatter polynomial (η _t (Z)) with respect to the intermediate value of the error values are obtained.

Next, by executing part 58 of the flowchart in FIG. 2D, the error positions determined through the Chien's algorithm 57 are used to determine the error position polynomial (σ _t (Z)) and the error estimation polynomial (η _t ( Z)), the intermediate values (Y _{L + t-1, L} ... Y _{L, L} ) for the error values are obtained, and the error values are determined using the portion 61 of the flowchart.

In part 61 of FIG. _{2, the} error value Y _{j, o} is finally calculated from the stored error position numbers and the intermediate value P _j by utilizing the seventh calculation means of FIG.

With reference to FIGS. 2A to 2D and FIG. 3, the calculation method utilized in the second embodiment of the galoi-based computing device configured as described above will be described. For the error values Y _{j, o} , there are nine error values corresponding to errors in the case of J = 8 to 6, which do not know the error position, and errors in the case of J = 5 to 0, which knows the error position. Let's assume. In the equation for each error value as in the first embodiment for obtaining Y _{j, o} , the calculation of Y _{j, j} for the range of j from L-1 to 0 is executed, but before this operation, It is effective to obtain the P _j-1 value from the intermediate value P ₀ .

That is, when the obtained P _j by setting the operational expression of the σ _{i, j} to the _{σ i, j = σ i,} j-1 × X j-1 + σ i-, 1-1, σ i, j , and a syndrome ( S _i ) is obtained and the following operation is executed.

σ_i,j×S_I That is, P _j =

σ _{i, j} × S _I

The intermediate value (P _j ) obtained as above is stored in another location in memory. Here, the L-th intermediate value is determined as follows.

Subsequently, the following _equations are calculated by obtaining the intermediate values Y _{L + t-1, L} ... Y _{L, L of} the modified syndromes and the error values remaining in the same manner as in the first embodiment.

In this case, similarly to the method of the first embodiment, Y _{i, j + 1,} i.e., arithmetic result of the preceding arithmetic operation _, in Y _{j, j} in the j range from the maximum value L-1 to 0 as follows. To utilize.

By the sequential arithmetic operation, when a calculation result when j = 0 is obtained, the target error value, that is, Y _{j, o} is stored in the memory. If the error position numbers are known by using a means other than the above, erasure correction can be effectively performed by substituting such error position numbers in the calculation, and the error correction can be performed within the range where the code distance can be tolerated. This can be done systematically through. As an operation during this procedure, an operation of multiplying 1.5 × L ² + t ² is required.

In the first embodiment according to the present invention, the product of 0 elements can be omitted by assuming that the result is 0 elements, and the case of multiplication of 1 is the same. It is also natural to substitute a value for performing condition determination, for example, adopting a zero element at the midpoint of the operation instead of the initial value setting operation. In addition, when executing operations sequentially, the operation may be executed by using some result values held in a device such as a register. Further, such an operation can be performed using a conventional microprocessor, and since the multiplication of the galoi system is usually performed using a log table, the algorithm according to the present invention is particularly effective in such an operation.

In the case of the parity operation during the encoding operation and the syndrome operation, a considerably high speed operation process is required. Therefore, even in the case where such an operation process is executed by software, hardware capable of performing many cases of operations in parallel is employed. Even if high-speed processing is required, using a microprogramming scheme to perform arithmetic operations including error correction in software at a speed that is close to the speed of hardware, that is, pure hardware-based operations. It is also possible not to execute the process.

The received information word is c ′ _n-1 , c ′ _n-2 ,... , C _'d-1 accurate, but to generate, after a c corresponding to d-1 parity words to be erased' _d-1, c '... _d-3 If a zero element error occurs at c ′ ₀ , the decoding operation performed by inputting the zero element under the assumption that the error position numbers indicate the parity position is the same as that of performing the encoding operation on the information word. In other words, if the erasure correction can be performed at high speed using a microprogram, the encoding operation can be executed at the same speed.

In this case, when the checkword is to be supplied to the syndrome generating circuit in FIG. 3, only the zero element is required after setting the logical multiplication circuit 1 to an operation state. In this case, it is assumed that the unknown error number t is 0 and the known error number L is d-1. In this way, if only the syndrome calculation circuit can be complemented with corresponding hardware, the encoding circuit can be omitted.

[Industry utilization]

As described above, according to the present invention, by utilizing the syndrome generating circuit and the codeword memory circuit attached to the code error detecting and correcting apparatus, it is possible to execute normal calibration and erase calibration at high speed. As a result, since the decoding operation through a recording medium with a high error rate such as an optical disk device requiring high speed operation and high performance can be actually executed, an advantageous effect can be achieved.

Claims (2)

The Galoisian operation unit attached to the data transfer unit utilizes a codeword made of error-corrected linear codes with a Hamming distance (d) including elements belonging to the Galois system (GF (2 ^r )). And a syndrome generating circuit for generating a syndrome in the range of S ₀ to S _{d-2 in} receiving the received codewords and error position numbers as input: for L known error number _numbers from X ₀ to X _L-1 . Error Position Polynomial σ _{i, j} = σ _{i, j-1} × X _j-1 + σ _{i-1, j-1}

j

L, j

i

A first calculation means obtained by assuming that σ _{j, j} = 1 under the condition of 0, and that the written symbols on the right side of the equation do not differ from each other, that the variables corresponding to the written symbols are 0; By using σ _{i, j} obtained and the syndrome generated from the syndrome generating circuit, T _k =

a second operation means for calculating a modified syndrome for k in the range from 0 to d-2-L in accordance with σ _{i, j} × S _{k + 1} and: using a modified syndrome T _k as a syndrome, Calculate the error-position polynomial coefficients for t errors corresponding to the error-position number of Third computing means and: fourth computing means for calculating utilizing error method algorithms such as Chien's method to obtain error location numbers from an error location polynomial corresponding to an unknown error; a fifth open to t one by inputting the error position teeth in the error location polynomial and an error estimation polynomial corresponding to the error of the image, computing a median value intended errors in the range from Y _{L, L} from Y _{L + t-1} Means: with respect to the intended L + t of the base and all the error values (Y _{j, o)} on the number of error location of the image that, while the variable j from 0 to L-1 i

Under the condition of _j, Y _{j, j} =

Y _{i, j + 1} / (X _i + X _j ) +

After calculating Y _{j, j} according to xσ _{i, j} × S _i , to obtain Y _{j-1, j-1} for _j-1 , Y _{i, j + 1} / (X _i + X _j ) = Y _{i, j} in terms of the right side of the formula and the operation result, by substituting the left side of the operation result (Y _{j, j)} in the above formula, the final error value _{(Y 0,0 ... Y L-1,0} ... Y _And a sixth calculating means for executing the calculation until _{L-1 + t, 0} ) is obtained. Codewords consisting of error correction selection codes with a hamming distance (d) are composed of elements of the Galois system (GF (2 ^r )), utilized for data transmission, and receive receive codewords and error position numbers as inputs. A gallon calculation apparatus attached to a data transmission device, comprising: a syndrome generating circuit for generating syndromes in the range of S ₀ to S _d-2 : for L known error _numbers from X ₀ to X _L-1 Error position polynomial σ _{i, j} = σ _{i, j-1} × X _j-1 + σ _{i-1, j-1} , 0

j

L, j

i

Under the condition of 0, if σ _{j, j} = 1, and if the symbol written on the right side of the equation is not different, the corresponding variable is assumed to be 0, and the first operation means for obtaining the coefficient of the polynomial: 0

j

L, j

i

When σ _{i, j} is obtained through the arithmetic operation on j by the first calculation means under the condition of 0, syndrome (S _i ) and P _j =

The intermediate result (P _j ) obtained from σ _{i, j} × S _i is stored, and j = L and J

i

Set P _L to T ₀ =

a seventh operation means for storing the correction syndrome T ₀ obtained for k = 0 by replacing sigma _{i, L} × S _i : generated by the sigma generation circuit and σ _{i, j} obtained from the first operation means. Utilizing second syndrome to calculate modified syndrome (T _k ) for k in the range 0 to d-2-L in accordance with T _k = σ _{i, L} × S _{k + i} ; the syndrome utilizing (t _k), Euclidean di Koh coding method for obtaining the coefficients of the error estimation polynomial of the value one to the one t of errors the error position polynomial for corresponding to the number of the error location of the unknown coefficients and, intended error median and A third operation means for calculating using the same error correction algorithm, and a fourth operation means for calculating using error method algorithms such as Chien's method to obtain error position numbers from the error position polynomial related to an unknown error; T values obtained by the fourth calculating means By substituting the position teeth of the error location polynomial and an error estimation polynomial associated with the error of the unknown Y _L, fifth arithmetic means for calculating a median value _L to Y _{L + t-1} range intentional errors: intended L + t that Y _{j, j} = while varying j from L-1 to 0 to obtain all error values (Y _{j, 0} ) for the number of known and unknown error positions

_{Y i, j + 1 / (} X i + X j) + by computing the Y _{j, j} in accordance with P _j, and then to order to obtain the Y _{j-1, j-1} to j-1 terms Y _{i, j +1} / (X _i + X _j ) = Y _{i, j} is substituted for the result of the calculation on the right side and the result of the calculation on the left side (Y _{j, j} ) into the equation, resulting in the final error value (Y _0,0 . And an eighth calculating means for executing the calculation until Y _L-1,0 ..., Y _{L-1 + t, 0} ) is obtained.

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