JP2752510B2 - Error correction decoder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoder for correcting errors in digital information.

[Conventional technology]

FIG. 6 is a block diagram showing a conventional error-correcting decoder shown in, for example, a document (Yamagishi, Imai, "One Construction Method of BCH Code Using ROM", IEICE, Vol.J63-D PP.1034-1041). It is a figure, wherein 1 is an information input terminal of an error correction decoder,
2 is an information output terminal of the error correction decoder, 3 is a buffer register for storing an _n- bit received word vector x = (x ₀ , x ₁ ,..., X _n-1 ), and 4 is a received word vector x syndromes S ₁ and the syndrome S ₃ syndrome generating circuit for calculating a, 5a, respectively 5b the syndrome generating circuit 4 from
The syndrome registers 15a and 15b for latching the syndromes S ₁ and S ₃ calculated in the above are RO for converting the syndrome of the vector representation latched by the syndrome registers 5a and 5b into the syndrome of the exponential representation, respectively.
Cube circuit M, 16 is to calculate the S ₁ ³ to the output S ₁ of the ROM 15a,
17 by dividing the output S ₁ ³ cubed circuit 16 at the output S ₃ of the ROM 15b S ₁ ³
/ Divider circuit for calculating the S _3, 18a, 18b 2 quadratic equation regarding each ^{Y Y 2 + Y + (1} + S 1 3 / S 3) = 0 of the solution Y _1, ROM for converting Y _2, 19a, 19b are Output of ROM18a, 18b respectively
To _{Y 1, Y 2, X 1} = S 1 · Y 1, X 2 = S 1 · Y 2 error position X ₁ of the received word by computing the multiplication circuit for obtaining the X _2, 20 is the received word This is a correction circuit for correcting an error.

 Next, the operation will be described.

An n-bit received word vector x = (x ₀ , x ₁ ,..., x _n-1 ) enters from the information input terminal 1 and is stored in the buffer register 3. Next, the received word read from the buffer register 3 is output to the syndrome generation circuit 4 in the syndrome S _1.
And S ₃ are calculated, respectively syndrome register 5a, 5
latched by b. Then, the syndromes S ₁ and S ₃ in the vector expression latched in the syndrome registers 5a and 5b by the ROMs 15a and 15b are respectively converted into exponential expressions. Then S ₁ ³ is calculated by the third power circuit 16, S ₁ ³ in the division circuit 17
/ S ₃ is calculated. Here, for the error position X, X = S ₁ Y
An error locator polynomial by placing is expressed as ^{Y 2 + Y + (1 +} S 1 3 / S 3) = 0, the solution Y _1, Y ₂ of the quadratic equation for this Y ROM 18
In a and 18b, it is obtained by searching from the output of the division circuit 17. And the error position X by the multiplication circuits 19a and 19b
₁ and X ₂ are obtained from X ₁ = S ₁ · Y ₁ and X ₂ = S ₁ · Y ₂ , respectively. On the other hand, the received word is read from the buffer register 3 to the correction circuit 20, the bit corresponding to the output of the multiplying circuits 19a and 19b is inverted, and the received word whose error has been corrected is output to the information output terminal 2. The operations used here are all operations on Galois fields.

[Problems to be solved by the invention]

Since the conventional error correction decoder is configured as described above, an error position must be obtained by a look-up operation using a ROM, and there is a problem that the time required for error correction increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain an error correction decoder capable of performing error correction at high speed.

[Means for solving the problem]

The error correction decoder according to the present invention provides the first 1
Using two shift registers, in which the syndrome data when the bit is incorrect is stored as an initial value, in parallel, a syndrome is generated when one bit is incorrectly input, and the syndrome is already obtained. The logical addition with the syndrome of the received word is performed, and as a result, if error data having an error of 1 bit or less is output, the corresponding bit is corrected.

[Action]

The error correction decoder according to the present invention generates a pseudo 1-bit error syndrome using a shift register, and performs a logical addition to the syndrome data of the received word. When the position coincides with the error position of the received word, a one-bit error or error-free syndrome data is output at the output, whereby the error position is specified and the error can be corrected.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an information input terminal of the error correction decoder, 2 is an information output terminal of the error correction decoder, and 3 is an n-bit received word vector x = (x ₀ , x ₁ ,..., X _n-1). ) Is stored in a buffer register, 4a, 4b is a syndrome generation circuit that calculates the syndromes S ₁ and S ₃ for each received word x, and 5a and 5b are calculated by the syndrome generation circuits 4a and 4b, respectively. The syndrome register 6 for latching the syndromes S ₁ and S ₃ that have been set, outputs 0 only when the outputs of the syndrome registers 5a and 5b are all 0,
In other cases, the check circuits I and 7a and 7b which output 1 respectively store the syndrome data S _{i, 1} , S _{i, 3} when only the first bit of the received word x is incorrect as an initial value, and perform synchronization. shift register error location of the received word contents is shifted by signal changes syndrome data when moved 1 bit to the right, 8a, 8b calculates the exclusive OR of the input, respectively, S _'1, S " XOR circuit to output ₃ 9
Cube circuit for calculating _a ³ 'S and cubed ₁ on Galois field' S is 24 converts the S _"3 as represented by the same base as the base which S ₁ is represented, which the _'basis conversion circuit for outputting as _3, 10 S' S XOR circuit for calculating the ₁ ³ S _'3, 11
Outputs a 1 only when all the input bits are 0, and outputs a 0 otherwise.
AND circuit, 13 is an XOR circuit for correcting errors in the received word,
A control circuit 14 controls the entire error correction decoder.

 Next, the operation will be described.

Here, (511,493,5) BCH code and Galois field GF (2 ⁹ )
The minimum polynomials of the above α and α ³ are expressed as M ₁ (x) =
x ⁹ + x ⁴ +1 and M ₃ (x) = x ⁹ + x ⁶ + x ⁴ + x ³ +1.

First, a received word is read from the information input terminal 1 into the syndrome generation circuits 4a and 4b, and S ₁ and S ₃ are calculated, respectively.
The syndrome generation circuits 4a and 4b are composed of a sequence representing the minimum polynomials M ₁ (x) and M ₃ (x) as shown by 4a and 4b in FIG. 2, respectively. At this time, the received word is stored in the buffer register 3 at the same time.

When the syndromes S ₁ and S ₃ are calculated by the syndrome generation circuits 4a and 4b, respectively, the syndrome registers 5a and 5b
Latch. The latched data is retained while correcting the error in the received word. On the other hand, in the shift registers 7a and 7b, the syndrome data (000100001) and (0
01101001). Note that shift registers 7a and 7
b is the minimum polynomial M as shown by 7a and 7b in FIG. 3, respectively.
₁ (x), Reciprocal polynomials of M ₃ (x) ₁ (x), ₃ (x)
The contents of the register are changed to syndrome data when the next one bit is incorrect every time one bit is shifted.

Next, the data of the syndrome register 5a of data S ₁ and the shift register 7a of the data S _{i, 1} of the exclusive OR and syndrome register 5b data S ₃ and the shift register 7b S
XOR circuits 8a and 8b calculate exclusive OR of _{i and 3} , respectively,
S _{' "for 1} 1, S .S to output _3' S 3 square circuit 9 is converted into ₃ '.S ₁ ³ are _computed" S basal converter 24 for _3'. The cubic circuit 9 is composed of an AND circuit and an XOR circuit to calculate the relational expression in FIG. The basis conversion circuit 24 is constituted by an XOR circuit for calculating the relational expression of FIG. 4 (b). Then, X 'circuit S'
₁ ³ S _'3 is calculated.

The output of the AND circuit 12 is as follows depending on the conditions of S ₁ , S ′ ₁ , S ′ ₃ .

When S ₁ = S ₃ = 0, the output of the inspection circuit I6 becomes 0,
The output of the AND circuit becomes 0.

When S ₁ ≠ 0 or S ₃ ≠ 0, the output of the inspection circuit I6 is 1
Becomes In this case ^{_{S '1 3 S' 3 =}} 0 if the test circuit 11
Outputs 1; otherwise, it outputs 0. That AND circuit 12 outputs 1 when S _'1 ³ S' 3 _{= 0} (error 2 bits or 1 bit), otherwise (error 3 bits or more) outputs 0. When the output of the AND circuit 12 is 1, the bit of the received word corresponding to the contents of the shift registers 7a and 7b is regarded as erroneous, and the XOR circuit 13 corrects the error.

Next, the buffer register 3 is controlled by a signal from the control circuit 14.
Is shifted by one bit, and at the same time, the shift registers 7a and 7b are also shifted by one bit, and the same operation as described above is performed, and the result is output to the information output terminal 2. The operations performed here are all operations on Galois fields.

In the above-described embodiment, the configuration in which the basis conversion circuit 24 is provided at the subsequent stage of the XOR circuit 8b and the output of the XOR circuit 8b is basis-converted has been described, but the present invention is not limited to such a configuration. A base conversion unit may be provided at a stage subsequent to the syndrome generation circuit 4b and the shift register 7b, or may have a base conversion function inside the syndrome generation circuit 4b and the shift register 7. An effect similar to that of the embodiment is obtained.

In the above embodiment, the syndrome of a one-bit error is artificially generated for each bit of the received word and the logical addition is performed, so that the error correction is performed for each bit of the received word. The addition of a one-bit error may be performed as shown in the second embodiment of the present invention in FIG. That is, in FIG. 5, the shift registers 21a and 21b
Is loaded with the syndrome data when the m-th bit is incorrect by one bit from the beginning of the received word. The gate circuit 22 arranged in (m-1) stages in parallel receives the first (m)
-1) Syndrome data is generated when one bit from the first bit to the first bit is incorrect, the syndrome when a pseudo error is added is calculated, and the syndrome data is passed in parallel to m bits through the check circuit III23. Then, the shift registers 21a and 21b are shifted to m bits by the synchronous clock, and all bits of the received word are output to the information output terminal 2. Inspection circuit II
I23 is a portion surrounded by a dotted line in FIG.

〔The invention's effect〕

As described above, according to the present invention, syndrome data in which a 1-bit error is pseudo-generated in a received word is calculated by using a shift register, so that the apparatus can be simplified, and the error can be easily corrected. This has the effect of obtaining something that can be corrected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an error correction decoder according to an embodiment of the present invention, FIG. 2 is a block diagram specifically showing a syndrome generating circuit in the present invention, and FIG. 3 is a shift register according to the present invention. Block diagram,
FIG. 4 (a) is a diagram specifically showing a calculation process by a cubic circuit in the present invention, FIG. 4 (b) is a diagram specifically showing a calculation process by a base conversion circuit in the present invention, and FIG. FIG. 6 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram showing a conventional error correction decoder. In the figure, 1 is an information input terminal, 2 is an information output terminal, 3
Is a buffer register, 4, 4a, 4b are syndrome generation circuits, 5a, 5b are syndrome registers, 6 is an inspection circuit I, 7
a and 7b are shift registers, 8a and 8b are XOR circuits, 9 is a cubic circuit, 10 is an XOR circuit, 11 is an inspection circuit II, 12 is an AND circuit, and 13 is
XOR circuit, 14 is a control circuit, 15a and 15b are ROM, 16 is a cubic circuit, 17 is a division circuit, 18a and 18b are ROM, 19 and 19b are multiplication circuits,
20 is a correction circuit, 21a and 21b are shift registers, 22 is a gate circuit, 23 is an inspection circuit III, and 24 is a basis conversion circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichiro Wakasugi 50-23 Kita-Shirakawa-Oguracho, Sakyo-ku, Kyoto-shi, Kyoto (56) References JP-A-1-289322 (JP, A) JP-A-3-117923 ( JP, A) Patent 2636432 (JP, B2)

Claims (2)

(57) [Claims] 1. A 2-way BCH 2 double error correction decoder of the code, the received word vector of n bits _{x = (x 0, x 1} , ..., x n-1) and the storage device for storing syndrome S ₁ a syndrome generation circuit arranged in parallel to calculate the S _3, respectively, a syndrome register for each latch calculated S _1, S ₃ with the syndrome generating circuit, only one bit of the head of the received word is incorrect Shift registers arranged in parallel to store the syndrome data as initial values _, and exclusive logic of outputs S ₁ , S _{3 of the} syndrome registers and outputs S _{i, 1} , S _{i, 3} of the shift registers Sum S ' ₁ = S ₁ S
_{i, 1} , S ″ ₃ = S ₃ SOR, XOR circuits arranged in parallel to calculate S _{i, 3} , and S ″ ₃ converted to be represented by the same basis as S ₁ is represented 'a basis conversion circuit that outputs a _3, S' S 3 that outputs S _'1 ³ formed by the third power of ₁ on Galois field
A circuit multiplication, a test circuit output of the syndrome register to check whether all zeros, the output S of the third power circuit _'1 ³ and output S of the basis conversion circuit _3' of the exclusive OR S ' ₁ ³ S _'3 and addition circuit for calculating the output S of the adder circuit' error correction, characterized in that a test circuit to check whether all bits of ₁ ³ S _'3 is 0 Decoder. 2. A method according to claim 1 in which the basis conversion circuit is characterized in that the syndrome generating circuit, or the next stage that for calculating the S _3, are provided in the shift register or the subsequent stage thereof of the S ₃ side An error correction decoder as described.