JPH09162753A - Decoding system for code word - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time required for arithmetic operation of a syndrome relating to the case of decoding a code word which is able to correct a t- multiple error for a series consisting of 255 sets consecutive symbols each in 8-bit structure being an element on an extended Galois field. SOLUTION: A prescribed number from a symbol series of a code word, for example, two partial series consisting of symbols extracted by two each are generated, and a partial arithmetic means 10 is provided to each partial series and a partial syndrome with respect to each partial series is calculated simultaneously in parallel, an overall arithmetic means 20 combines two partial syndromes to integrate the result into a syndrome Sp relating to the code word, then repetitive arithmetic operations of 255 times having been required by a conventional system is reduced to 128 times. Then the syndrome arithmetic time is reduced to a half.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the presence / absence of an error in decoding or decoding a code word which is a symbol sequence including an error correction code, particularly a code word using a so-called Reed-Solomon code (hereinafter referred to as RS code). The present invention relates to a codeword decoding method for detecting an error and correcting an error as necessary.

[0002]

2. Description of the Related Art In various fields handling digital information or data, it is well known that information is based on information theory in order to detect and correct errors that are likely to occur during transmission or reading from a storage medium. It is general that an error correction code is added and encoded in the form of a code word containing both of them, and this code word is always treated as a unit even when decoding it after transmission or reading. For example, the above R
The code word using the S code is a so-called extended Galois field GF
(2 ^m ) n symbols with m-bits as elements on
(n = 2 ^m −1), which is an arrayed sequence, and is usually 8 with m = 8.
Bit-structured symbols, that is, each 1-byte data
It is a series of 255 symbols.

In a codeword using this RS code, t
To make it possible to correct double errors in byte units, 2t of n symbols are assigned to the error correction code, and the net amount of information in the codeword is n-2t bytes. At the time of encoding, let α ^p (p = p = p = ^p ) be the primitive element of the extended Galois field GF (2 ^m ).
A generator polynomial having 2t roots represented by 0,1 to 2t-1) is used, and the codeword polynomial W (x) = ΣWix ⁱ is divisible by this generator polynomial. However, Σ is
i represents the addition within the range of i = n-1 to 0, Wi is the i-th symbol of the codeword, and x is a pseudo variable.

When this code word is received and decoded, a syndrome Sp = W indicating a kind of medical condition of the received code word is first set by inserting α ^p into the variable x of the code word polynomial W (x).
Find (α ^p ). Codeword polynomial W when encoded
Since (x) is divisible by the generator polynomial having the root α ^p , it can be seen that the syndrome Si is 0 if there is no error in the received codeword, and an error has occurred otherwise. Syndrome according to FIG. 3 Sp = W (α ^p ) = ΣWiα ^pi
The conventional procedure for obtaining

The memory 1 shown in the upper left portion of FIG. 3 stores n symbols Wi constituting the received code word, and receives the address AD which is sequentially decremented according to the pulse DP from the address designating circuit 8 The symbols Wi starting from i = n-1 are sequentially placed on the bit bus 3. Syndrome arithmetic circuits 4 are provided for sequentially receiving the symbols Wi from the bus 3 to obtain the syndromes S0, S1 to Sp and the like. When detecting and correcting the above-mentioned t-fold error, 2t of these syndrome calculation means 4 are provided to obtain the syndrome Sp in the range of p = 0 to 2t-1.

The arithmetic means 4 for the syndrome S0 is composed of an adder circuit 5 and a register 6 each having an 8-bit structure. The adder circuit 5 receives the 8-bit symbol Wi from the bus 4 and outputs it to the 8-bit register 6 bit. Although it is added to the memory content of each bit, since it is Mod2 whose addition is modulo 2, it is composed of 8 exclusive or gates. The register 6 is cleared at the start of the operation of the arithmetic circuit 4, and the addition result is read from the addition circuit 5 in response to the latch pulse LP synchronized with the above-described decrement pulse DP. Syndrome SO is a symbol
Since it is a simple sum ΣWi of Wi, it is sufficient to take it out from the register 6 after the addition of the last symbol W0 is completed.

In addition to the adder circuit 5 and the register 6, the multiplication circuit 7 is incorporated in the arithmetic means 4 for the syndrome S1 and thereafter,
The content stored in the register 6 is multiplied by the primitive element α in the case of the syndrome S1 and by α ^p in the case of the syndrome Sp, and the addition circuit 5
Output. The operation of the calculating means 4 will be described with respect to the syndrome Sp. When the first symbol W _n-1 is received after the memory contents of the register 6 are cleared, this symbol W _n-1 is read into the register 6 in response to the latch pulse LP. .
When receiving the next symbol W _n-2 , the adding circuit 5 adds the output α ^p W _n-1 of the multiplying circuit 7 to it, so that the register 6
Stores α ^p W _n-1 + W _n-2 . After that, similarly, the stored content of the register 6 after receiving the last W ₀ is α ^{p (n-1)}
Since W _n-1 + α ^{p (n-2)} W _{n-2 to} α W ₁ + W ₀ = ΣWiα ^pi = Sp, this can be taken out as a p-th order syndrome.

If all of the 2t syndromes Sp (p = 0 to 2t-1) are 0, there is no error, but if not, it is necessary to correct the error. For that purpose, first, the error position and the value of the error. From these syndromes Sp. Therefore, the error position is represented by an error locator α ^j, where the number in the code word of the errored symbol is j (j = 0 to t-1), and the reciprocal α ^-j is the root of the error position polynomial of degree t. make. Then the wrong value is
If the error polynomial Ej is E (x) = ΣEjx ^j , the syndrome is known as Peterson's method, Bahrenkamp-Mazzi method, and Euclidean method using Sp = E (α ^p ) = ΣEj α ^pj. The error locator α
^{Find j} and then find the error value Ej. After the error locator α ^j and the error value Ej are known, the error of the jth symbol Wj is corrected by adding the error value Ej, and the decoding of the code word is completed.

[0009]

It is desirable to incorporate a decoding function into an integrated circuit device so that the decoding of the code word described above can be easily applied to various purposes. Since it becomes very large, it must be a VLSI, and pipeline processing using a stonic algorithm has been considered to simplify its configuration (for example, Trans. On Computers, Vol. C-34, N
o.5, May 1985, p.383-403 and IEICE Transactions, 198
6/3, Vol.J69-A, No.3, p.420-428). But,
In the prior art, the point that a considerable amount of time is required for the calculation for the decoding operation, especially the calculation of the syndrome, is the biggest problem in practical use.

In the conventional system as shown in FIG. 3, for example, when the code word is composed of 255 symbols of 8 bits, the arithmetic means 4 for the syndrome Sp multiplies the storage content of the register 6 by α ^p by the multiplication circuit 7. Moreover, since it is necessary to repeat the product-sum operation of adding the symbol Wi to the multiplication result by the adder circuit 255 times, even if a plurality of operation means 4 are provided as shown in FIG. Only the calculation takes a considerable amount of time. Moreover, since the calculation of the syndrome is the first step in the series of operations for decoding as described above, it is not suitable for pipeline processing, and once the received codeword is loaded into the memory 1 of FIG. Since it has to be taken out one by one and given to the computing means 4, the time required for a large number of accesses to the memory 1 is an obstacle to increasing the decoding speed.

In view of such circumstances, it is an object of the present invention to reduce the time required for the syndrome calculation when decoding a codeword.

[0012]

According to the present invention, the above object is achieved by decoding each predetermined number of symbols from a sequence when decoding a code word as a symbol sequence to create a partial sequence of symbols and generate each partial sequence. Partial calculation means is provided in
It is achieved by simultaneously performing partial operations of the syndromes related to a plurality of partial sequences by these partial operation means, and combining a plurality of partial operation results by the integrated operation means to calculate the syndromes related to the code word. The decoding method of the present invention uses an RS code as a code word, and is particularly suitable when the symbol is, for example, an 8-bit element on an extended Galois field.

When the method of the present invention is implemented, the symbols of the symbol series are simultaneously placed on the bus on which the codeword to be decoded is placed from the memory by the number corresponding to the partial operation means, and each partial operation means is loaded with these symbols. It is very advantageous to read from the memory in parallel in order to shorten the access time to the memory. For example, two 8-bit symbols are simultaneously placed on a 16-bit bus, and two partial operation means are provided correspondingly to each of them, and a partial sequence consisting of an even-numbered symbol and an odd-numbered symbol in the symbol sequence. It is better to share the partial operation of the syndrome regarding.

It is sufficient to use a symbol addition circuit and a multiplication circuit for the addition result as the partial calculation means used in the present invention, and repeatedly add each symbol of the partial sequence to the multiplication result of the multiplication circuit by the addition circuit. It is advantageous that all of the plurality of partial calculation means have the same configuration. Further, a multiplication circuit for the calculation result of the partial calculation means and an addition circuit for the multiplication result are used as the integrated calculation means, and the multiplication circuit is provided corresponding to the partial calculation means except for one specific multiplication means. It suffices to add the result and the operation result of the specific partial operation means and integrate them into the syndrome of the code word. Further, a linear feedback shift register is used for the multiplication circuits used in these partial operation means and integrated operation means, and the number of shift operations for the multiplication operation is set according to the order of the syndrome to be obtained for the code word. This is advantageous, and in this mode, apart from the 0th-order syndrome which originally requires no multiplication circuit, the partial arithmetic means and the integrated arithmetic means can all have the same circuit configuration.

The method of the present invention can also be applied to the error correction stage. In this case, two error correction means are provided, and while the error correction means that should give the error value based on the error position and the error value obtained from the syndrome are selected according to the error position, the error occurred in the symbol in which the error occurred. It is better to add the value of and correct it. As the error correction means, a selection circuit, an addition circuit, and a register for storing the addition result are used. The selection circuit sequentially supplies the addition circuit with an error value and a symbol value while adding to the stored contents of the register. Then, the corrected symbol can be taken out from the register. Further, switching means for receiving the error position and the error value is used to switch or select the error correction means which should give the error value depending on whether the number of the symbol in the code word indicated by the error position in which the error has occurred is even or odd. It is better to let them do it.

According to the present invention, the syndrome is represented by a polynomial as described in the section of the prior art, that is, a form of sum of a plurality of terms or a form of sum of product terms, and the result of the sum is rearranged in the addition order of the terms. Paying attention to the same point, the symbol sequence is divided into a plurality of partial sequences, and by performing partial operations related to them in parallel or at the same time, the time required for the operation of the syndrome is shortened, and these partial sequences are By creating symbols by extracting a predetermined number of symbols from a codeword symbol sequence, partial operations for all subsequences can be performed smoothly and in a similar manner in synchronization with the reading of symbols from memory. Is. In addition,
If the number of symbols in the codeword is not divisible by the number of subsequences, a symbol whose content is 0 is added as appropriate to make the number of symbols in the subsequences uniform, so that the partial operation can proceed smoothly and accurately. This will be described more specifically as follows.

As described in the section of the prior art, the syndrome
Sp is generally a polynomial of the sum of products Sp = Σα ^ip W _i (i = 0
~ N-1), and in the present invention, n symbols W of the code word
_A predetermined number of symbols are extracted from the _i series and divided into r partial series, and the partial syndrome Spj (j = 0 to r-1) regarding each partial series is spj in the same form as above by the partial calculation means. = Σ ^r α ^pi W _{i + j} polynomial. However,
Σ ^r represents the sum when the variable i is changed by r as 0, r, 2r ... im. Further, the maximum value im of the variable i is obtained when the symbol number n of the codeword is divisible by the number r of subsequences.
If it is nr, otherwise it is n-r + 1, and the symbol W _{i + j} whose subscript i + j exceeds n-1 is set to 0. In the present invention, these partial syndromes Spj are simultaneously calculated in parallel by the r partial calculation means as described above.

After the calculation of the syndrome Spj of the subsequence, the syndrome of the codeword is calculated by the integrated calculation means.
Integrate into Sp. Since a certain number of symbols are extracted from the codeword symbol sequence to form a partial sequence, the partial syndrome Spj is a polynomial Sp having the same product sum form as above.
= Σα ^jp Spj can easily calculate the syndrome Sp in a short time. Therefore, in the present invention, the operation time of the syndrome Sp can be shortened to about 1 / r of the conventional time by the parallel operation of the partial syndrome Spj, and the memory access time can also be shortened to 1 / r by the parallel reading of a plurality of symbols.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a codeword decoding system according to the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to syndrome calculation, and FIG. 2 shows an embodiment in which it is applied to error correction. In these embodiments, the code word is a polynomial W (x) = Σx ⁱ W _{i in} which n = 255 8-bit symbols that are elements of the extended Galois field GF (2 ⁸ ) are arranged.
(However, Σ represents the sum of i = 0 to n-1) is defined as a sequence of symbols W _i by an RS code capable of correcting an error of t-fold, and the syndrome Sp (p = 0 to 2t-1) is At the time of calculation, the symbol sequence is divided into two subsequences each having a symbol extracted every other symbol, that is, an even-numbered symbol and an odd-numbered symbol.

A memory 1 shown in the upper left portion of FIG. 1 stores a series of symbols W _i of the received code word W (x), and is an address AD which is sequentially switched from the address designating circuit 2 according to a decrement pulse DP. The designated symbols are to be placed on the bus 3 from now on. In this embodiment, the bus 3 is divided into 2 sub-sequences at the same time corresponding to dividing the symbol sequence into two partial sequences.
A 16-bit bus capable of carrying eight 8-bit symbols is used to carry symbol pairs (W ₀ W ₁ ), (W ₂ W ₃ ), etc. Incidentally, when the W _n-1 symbol pair n is less than 255 even number including, for example, 254 and _{(W n-2 W n-} 1), when the odd as in this embodiment (W _n-1 It should be 0).

In the drawing, the partial arithmetic means 10 for the syndromes S0, S1 and Sp for receiving such a symbol pair from the bus 3 and the integrated arithmetic means 20 are shown surrounded by a chain line. The partial arithmetic means 10 is provided with one pair for each syndrome, and gives partial sequences including even-numbered and odd-numbered symbols on the upper and lower sides of the figure, respectively. By the way, the syndrome Sp is Sp = Σα ^pi W _{i because} it is sufficient to put α ^{p in} the variable x of the polynomial W (x) = Σx ⁱ W _i of the code word, and this is divided into even-numbered and odd-numbered symbols and arranged Then, Sp = Σ ² α ^pi W _i + α ^p Σ ² α ^pi W _{i + 1} . Σ ² represents a sum obtained by changing the variable i by 2 such as 0, 2, 4, and the first term relates to even-numbered symbols and the second term relates to odd-numbered symbols. Then Spe = Σ ² α ^pi W _i , Spo = Σ
Putting ² α ^pi W _{i + 1} , the above equation becomes Sp = Spe + α ^p Spo. The upper and lower partial computing means 10 are for computing these partial syndromes Spe and Spo, and these are integrated computing means.
20 to be integrated into Syndrome Sp.

As described above, since the partial syndromes Spe and Spo are represented by the same equation except that the symbols are even-numbered or odd-numbered, the two partial arithmetic means 10 can have the same configuration. The same applies to the case of dividing into arbitrary r partial sequences as long as a predetermined number of symbols are extracted from a codeword symbol sequence. In the case of the syndrome S0, the partial operation means 10 is composed of only the adder circuit 11 and the register 12 because the partial syndromes Spe and Spo to be operated are very simple Σ ² W _i and Σ ² W _{i + 1} , respectively. Then, the symbol received from the bus 3 is added to the stored contents of the register 12 by the adder circuit 11, and the latch command LP1 is given to the register 12 to store the addition result. The register 12 in this embodiment is 8
It is a bit register, and the addition circuit is composed of 8 modulo 2 OR gates, because the addition is a mod 2 modulo addition.

In the case of the syndrome Sp in which p is not 0, the multiplication circuit 13 is incorporated in the partial operation means 10 in addition to the above-mentioned addition circuit 11 and register 12, and the content stored in the register 12 is α.
^{The result} is multiplied by ^2p and then given to the adder circuit 11. Σ ² above
Since alpha ^pi W _i and Σ ² α ^pi W i _{+ 1} of the sigma ² the variable i is changed by 2, it is possible to calculate the partial syndrome Spe and Spo by the multiplication of the alpha ^2p by multiplier circuit 13. A linear feedback shift register (hereinafter referred to as LFSR) is used as the multiplication circuit 13 so that the content stored in the register 12 is read according to the read command RP1 and the content is shifted according to the clock so that the primitive element α can be multiplied. Is advantageous.

As is well known, in this embodiment, the LFSR shifts the stored contents of each stage of the 8-stage shift register in accordance with a clock as usual, and at the same time, stores the stored contents of the final stage. By feeding back to the content of the stage corresponding to the primitive polynomial of (1), the multiplication is performed by α, and at the same time, the remainder obtained by dividing the polynomial of the multiplication result by the primitive polynomial is automatically obtained. In the embodiment shown in FIG. 1, the LFSR is used in the multiplication circuit 13, and the syndrome
In the case of S1, two clocks C2 are given to multiply by α ^2, and in the case of syndrome Sp, 2p clocks C2p are given to multiply by α ^2p . In this way, in the embodiment shown in FIG. 1, the desired syndrome Sp
If the order p is 1 or more, the same circuit configuration can be used, except that the number of clocks to be given to the LFSR used for the multiplication circuit 13 as the partial arithmetic circuit 10 differs depending on the order p.

The integrated calculation means 20 is the calculation result of the partial calculation means 10. In this embodiment, two partial syndromes Spe and
Integrate Spo into syndrome Sp by an operation including addition. In the case of the 0th-order syndrome S0, it is sufficient to simply add these, so the above-mentioned Σ ² W _i and Σ ² W _{i + 1} are added by the adder circuit 21 consisting of eight exclusive OR gates, and then the register is added. The latch command LP2 is given to 22 and the result is stored as the syndrome S0. In the case of the first-order or higher-order syndrome Sp, the multiplication circuit 23 is provided in the integrated calculation means 20, the partial syndrome Spo is read according to the read command RP2 and multiplied by α ^p , and the addition circuit 21 makes the multiplication result the partial syndrome. Spe is added and then stored in the register 22. The multiplication circuit 23 is also preferably LFSR, and in the case of the syndrome Sp, p clocks Cp are given to this and multiplied by α ^p . As a result, the integrated arithmetic means 20 for syndromes other than the 0th order has the same circuit configuration.

In the embodiment of FIG. 1 configured as described above, the register 12 in the partial arithmetic means 10 and the register 22 in the integrated arithmetic means 20 are first cleared and then decoded from the memory 1 to the 16-bit bus 3. Code word W (x) = Σx ⁱ W _i
For example, the last W in the sequence of each 8-bit symbol W _i of
Starting with the symbol pair containing _n-1 and loading one by one,
Receiving this sequentially, the two partial operation means 10 for each syndrome Sp are operated in parallel to operate the partial syndromes Spe and Spo at the same time, and the integrated operation means 20 are also operated all at the same time to operate the two partial syndromes Spe. Integrate Spo into syndrome Sp. The syndrome Sp as the calculation result can be read from the register 22 of each integrated calculation means 20 at any time.

As described above, in the method of the present invention, the symbol sequence of the codeword is divided into two, generally r, partial sequences, and the partial syndromes related thereto are calculated by a plurality of partial calculation means.
Allocate to 10 and calculate at the same time. It is necessary to integrate a plurality of partial syndromes into the syndrome concerning the code word by the integrated calculation means 20, but the calculation time required for this may be much shorter than that of the partial calculation means 10. Therefore, the time required for the calculation of the syndrome according to the present invention. Can be shortened to about one half of the conventional one, generally one-rth. Furthermore, since two symbols, generally r symbols, can be read collectively from the memory 1, the memory access time can also be shortened to half of the conventional memory access period, generally to one rth, in the method of the present invention.

When the symbol sequence is divided into partial sequences in which r is 3 or more, the integrated operation means 20 multiplies r-1 partial syndromes and adds them r-1 times to obtain codewords. However, the time required for multiple multiplications is not much different from the time required for one multiplication, and even if the number of additions increases, each addition time using exclusive OR gates must be integrated. Since it is short, a slight increase in the calculation time of the integrated calculation means 20 can be sufficiently compensated by the effect of shortening the operation time of the partial calculation means 10. The memory access time becomes shorter as r becomes larger, and if r is 4,
The access time can be reduced to 1/4 using the 32-bit bus.

Further, in the embodiment of FIG. 1, in order to make the circuit configurations of the partial arithmetic means 10 and the integrated arithmetic means 20 the same regardless of the order p of the syndrome Sp other than 0, their multiplication circuits 13 and
Although an LFSR was used for 23, the LFSR that operates by repeatedly receiving a clock as described above requires extra time to control its sequence. Therefore, it is necessary to change the circuit configuration according to the order p, but the multiplication circuits 13 and 23 If it is composed of only logic gates, the time required for calculation can be further shortened. In this case, the multiplication circuits 13 and 23 have a multi-stage configuration,
For example, it can be configured only by an addition element by an exclusive OR gate.

In the embodiment shown in FIG. 2, the present invention is applied to the correction of an error occurring in a symbol of a received codeword. Syndrome Sp (p = 0 to 2t- obtained as described in FIG.
1) based on the above-mentioned Peterson method or Bahrenkamp
Using the Mazzi method or Euclidean method, the error position, that is, the number i of the t symbols in the symbol sequence where the error occurred and the value Ei of the error are obtained and stored in the memory 1a shown in the upper right part of the figure. It is assumed that The memory 1a may be the same as the memory 1 shown in the lower right part of the figure, but is shown separately for convenience of illustration, and the 16-bit bus 3a
The error position i and the error value Ei are fetched one by one into the registers 3b and 3c via.

In the embodiment of FIG. 2, the error correction means 30 is set to 1
A pair is provided for each of the selection circuit 31, the addition circuit 32, and the register 33.
And the buffer circuit 34, the error correction means 30 on the right side is used when the error position i is even, and the left side error correction means 30 is used when the error position i is odd. The switching means 40 shown on the upper side is for selecting the left and right error correction means 30 for performing the error correction operation according to the error position i stored in the register 3b.

Further, an address designating circuit 2 and an auxiliary designating circuit 2a are provided in association with the memory 1 which stores the code word symbol sequence as it is at the time of reception, and the register 3b stores the error position in the auxiliary designating circuit 2a. An address designating circuit 2 for designating i and converting it to a relative address ADr of the memory 1 and receiving it
Then, it is converted into an absolute address AD and then given to the memory 1. In response to this, the symbol pair including the error-generated symbol Wi is loaded from the memory 1 onto the 16-bit bus 3.

The switching means 40 is composed of, for example, AND gates as shown in the figure, and eight AND gates are used for each of the right and left AND gates 41 and 42 which are simply shown in the frame. The switching means 40 receives the least significant bit of the error position i of 8 bits from the register 3b, and when the error position i is even and the least significant bit is 0, the right AND gate group 41 is enabled and the register 3c is activated. An 8-bit error value Ei is given to the right error correction means 30, and conversely, when the error position i is an odd number, the left AND gate group 42 is enabled to enable the error value.
Ei is given to the error correction means 30 on the left side.
Further, the selection circuit 31 of the error correction means 30 selects either the error value Ei received from the switching means 40 or the symbol received from the bus 3 according to the designation by the logical value of the selection command Sc, and the addition circuit below it. 32, the right and left select circuits 31 receive the even and odd symbols of the symbol pair on bus 3, respectively.

When correcting an error, first, the error correction means 30
After clearing the register 33, the selection circuit 31 causes the selection circuit 31 to select, for example, the error value Ei. As a result, the error value Ei is given from the selection circuit 31 to the right or left addition circuit 32 according to whether the error position i is even or odd.
A latch command LP3 is given to the register 32 to read it from the adder circuit 32 and store it. Of course, 0 is stored in the register 33 of the error correction means 30 which has not received the error value Ei. Next, the logical value of the selection command Sc is switched and the symbol on the bus 3 is given to the addition circuit 32 via the selection circuit 31 to be added to the stored contents of the register 33, and further the latch command LP3 is given to the register 33 to perform this addition. Remember the result of. Thereby, in the register 33, the symbol corrected by the addition is stored in the one receiving the error value Ei, and the original symbol is stored in the register 33 as it is,
For example, it is loaded on the bus 3 via the buffer circuit 34 which is a bus driver and read by the memory 1.

The present invention is not limited to the embodiments described above, and the present invention can be implemented in various modes. For example, although the codewords are all RS codes in the embodiment, the present invention is closely related to the BCH code (Bose-Chaudhuri-Hocquenghem).
The order of the syndrome to be calculated is slightly different for codewords using (code) etc., but the same can be applied. Further, although all symbols are 8 bits, the present invention can be applied even if the symbols have arbitrary plural bits or single bit configuration.

[0036]

As described above, in the decoding method of the present invention, the syndrome of the codeword is represented by a polynomial in the form of the sum of a plurality of terms or the sum of products, and even if the addition order of terms is recombined, the calculation result of the syndrome is Focusing on the point that does not change, when decoding a code word that is a sequence of symbols, a predetermined number of symbols are extracted from the sequence to create a partial sequence, and partial calculation means is provided for each partial sequence to relate to a plurality of partial sequences. The following effects can be obtained by simultaneously executing the partial syndrome calculations and combining a plurality of partial syndromes by the integration calculating means to integrate them into the codeword-related syndrome.

(A) The symbol sequence of the code word is divided into two, generally r, partial sequences, and the partial arithmetic means provided for each partial sequence causes the partial syndrome operations relating to them to proceed in parallel. By reducing the number of repetitive calculations required for each sub-calculation, the time required for the calculation of the syndrome can be reduced to about one half of the conventional time, and generally to one rth.
Can be shortened.

(B) By extracting a predetermined number of symbols from the symbol sequence of the codeword to create a partial sequence, and performing partial operations on a plurality of partial sequences simultaneously in synchronization with the reading of the symbols from the memory, The time required to access the memory can be shortened to one half of the conventional one, generally one rth, and further, the calculation of multiple partial syndromes can all proceed in the same way, and easily by the integrated calculation means. Can be integrated into the codeword syndrome.

As described above, the method of the present invention solves the conventional problem that it takes time to calculate the syndrome and to access the memory with a simple structure, and makes the integrated circuit device used for decoding the code word practical. It can make a significant contribution. It should be noted that the mode in which the symbols constituting the code word by the Reed-Solomon code is the 8-bit element on the extended Galois field is an application form of the present invention having the highest practical utility value, and the symbol sequences are even-numbered and odd-numbered. The mode of dividing the symbol into two partial sequences is advantageous in that it can be easily implemented. In addition to the above-described effect of shortening the access time, a processor such as 16 There is an advantage that the code word can be decoded using the bit internal bus as it is.

Further, a linear feedback shift register is used in an embodiment in which a plurality of partial operation means have the same circuit configuration, and a multiplication circuit incorporated in the partial operation means and the integrated operation means, and the number of shifts during the multiplication operation is determined by the syndrome. The embodiment in which the partial arithmetic means other than the 0th-order syndrome and the integrated arithmetic means are all configured to have the same circuit configuration by setting according to the order has the effect of easily configuring the arithmetic circuit of the syndrome.

When the present invention is applied to error correction, a pair of error correction means is provided and an error value is received based on the position in the code word of the symbol including the error and the error value obtained from the syndrome. The mode of adding and correcting the error value while switching the correction means according to the error position has an advantage that the error correction can be efficiently advanced by using an internal bus such as a microprocessor. A mode in which a correction circuit is incorporated by sequentially providing an error value and an error-containing symbol to an adder circuit and a switching means for receiving an error position and an error value are used to determine whether the error-containing symbol is an even number or an odd number. Any of the modes in which the error correction means that gives an error value according to the above is selected has the effect of simplifying the circuit configuration of the error correction means.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment in which a codeword decoding method according to the present invention is applied to a syndrome calculation.

FIG. 2 is a circuit diagram showing an embodiment in which the system of the present invention is applied to error correction.

FIG. 3 is a circuit diagram of a syndrome arithmetic circuit in a conventional decoding system.

[Explanation of symbols]

 1 Memory for storing symbol sequence of received codeword 1a Memory for storing error position and error value 2 Addressing circuit for memory 2a Sub addressing circuit for memory 3,3a Bus 3b Register for error position 3c Error Registers for storing values 10 Partial calculation means 11 Addition circuit for partial calculation means 12 Register for partial calculation means 13 Multiplication circuit for partial calculation means 20 Integrated calculation means 21 Addition circuit for integrated calculation means 22 Integrated calculation means Register 23 Multiplication circuit for integrated operation means 30 Error correction means 31 Selection circuit for error correction means 32 Adder circuit for error correction means 33 Register for error correction means 34 Buffer circuit for error correction means 40 Switch for error correction Circuit 41,42 AND gate for switching circuit S0 0th-order syndrome S1 1st-order syndrome Sp p-third syndrome

Claims (12)

[Claims] 1. When obtaining a syndrome relating to a codeword, which is a series of symbols arranged in order to decode the codeword,
A partial operation means is provided for each of a plurality of partial series of symbols extracted from a predetermined number of symbols from a symbol series, and partial operations of the syndrome related to the partial series are simultaneously advanced, and then a plurality of partial operation results are obtained by the integrated operation means. A codeword decoding method characterized in that the syndromes for codewords are calculated by combining. 2. The system according to claim 1, wherein symbols of a symbol sequence are simultaneously placed on a bus for a codeword to be decoded by a number corresponding to partial operation means, and each partial operation means receives these symbols from the bus. A codeword decoding method characterized by being read in parallel. 3. The system according to claim 1, wherein each partial operation means includes a symbol addition circuit and a multiplication circuit for the addition result, and the addition circuit causes each multiplication result of the multiplication circuit to be included in each partial sequence. A codeword decoding method characterized in that a syndrome for each partial sequence is calculated by sequentially and repeatedly adding symbols. 4. A code word decoding system according to claim 3, wherein all of the plurality of partial arithmetic means have the same circuit configuration. 5. The method according to claim 1, wherein a multiplication circuit for the calculation result of the partial calculation means and an addition circuit for the multiplication result are used as the integrated calculation means, and a multiplication circuit is provided for the partial calculation means except one. And its multiplication result and 1
A codeword decoding method, characterized in that the syndrome of a codeword is obtained by adding the calculation results of a plurality of partial calculation means. 6. The method according to claim 3 or 5,
A code word decoding method characterized in that a linear feedback shift register is used as a multiplication circuit, and the number of shift operations for the multiplication operation is set according to the order of the syndrome to be obtained for the code word. 7. The code word decoding method according to claim 6, wherein the partial arithmetic means for the non-zero-order syndromes and the integrated arithmetic means have the same circuit configuration. 8. The code word according to claim 1, wherein two partial operation means are provided so as to share partial operations for even-numbered symbols and odd-numbered symbols of a symbol sequence, respectively. Decryption method. 9. The method according to claim 1, wherein a Reed-Solomon code is used for the code word, and the symbols forming the code word are elements of 8-bit structure on the extended Galois field. Codeword decoding method. 10. The method according to claim 1, wherein two error correction means are provided and an error value is to be given based on the position of the error-containing symbol in the code word and the error value obtained from the syndrome. A codeword decoding method characterized in that a symbol containing an error is corrected by adding an error value while switching the correcting means according to an error position. 11. The system according to claim 10, wherein a selection circuit, an addition circuit and a register for storing the addition result are used as the error correction means, and the selection circuit switches the error value and the symbol value to the addition circuit. A code word decoding method characterized in that corrected symbols are taken out from the register after being sequentially added and added to the stored contents of the register. 12. A system according to claim 10, wherein a switching means for receiving an error position and an error value is used, and the number of a symbol having an error in a code word indicated by the error position is even or odd. A codeword decoding method characterized in that an error correction means for giving an error value is selected.