JP3260095B2 - Error correction code and error detection code decoder and decoding method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction of a BCH code, a CRC code and the like in a receiving side apparatus of an information bit sequence transmission system typified by a mobile communication system such as a digital automobile telephone system or a portable telephone system. The present invention relates to a code and an error detection code decoder.

[0002]

2. Description of the Related Art Error correction and error detection encoders and decoders are used in mobile communication systems such as digital automobile telephone systems and mobile telephone systems, and for writing to and reading from recording media such as optical disks. Used in systems and the like. In the case of error correction and error detection codes used in mobile communication systems, signals transmitted and received in mobile communication systems consist of control signals and non-control signals, and both transmission and reception delay times need to be reduced as much as possible. In addition, high-speed encoding and decoding processes are required and control signals are also required to have high reliability.

[0003] Further, in the case of an error correction and error detection code used for a recording medium, when the recording medium is a read-only medium, high-speed decoding is required, and for a writable and readable medium, encoding and decoding are performed. High-speed processing is required for both of the conversion processing.

An error correction / detection code used in a mobile communication system includes an inner code such as a CR for error detection.
C (Cyclic Redundancy Chec)
k) A code is converted to an outer code using a BCH (B
oose ChaudhuriHocquenghem)
It is common to apply a code.

[0005] The processing in the basic encoder / decoder is as follows.
It is as follows. After the transmitting side performs an error detection encoding process using a CRC code on the information bit sequence,
Error correction coding by H code (by this processing,
(The CRC code is an inner code and the BCH code is an outer code.) The signal is transmitted to a transmission path, and the receiving side applies BCH error correction decoding to the code sequence transmitted from the transmission path, and the result is obtained. A final decoding result is obtained by further performing an error detection check on the decoding result using a CRC code.

On the other hand, in the case of an error correction / detection code used for a recording medium, the inner code has a CR for the purpose of error detection.
The C code is replaced with an outer code RS (Ree) for the purpose of error correction.
(dSolomon) code is generally applied. Further, the processing in the basic encoder / decoder is performed in the same manner as in the mobile communication system. However, a method for speeding up the decoding processing by performing the error correction decoding processing and the error detection decoding processing in parallel, As for the arithmetic processing, a method for speeding up the decoding processing by obtaining a solution from a ROM storing a modular arithmetic conversion table in which the modular arithmetic processing result is registered, and realizing data of a plurality of formats with the same circuit configuration A method for doing so has been devised.

A processing method in an encoder and a decoder for performing error correction and error detection in a mobile communication system is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 6-188882. Hereinafter, the configuration and operation of the error correction and error detection encoder and decoder will be described with reference to FIG.

FIG. 10 is a block diagram of a conventional encoder and decoder disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-188882. 10, 1001 is an encoder, 1002 is a decoder, and 1003 is a wireless transmission unit. The error detection code described in this conventional example is a CRC code, and the error correction code is a BCH code. However, the BCH code is used for both random error correction and burst error correction, and at the time of decoding, the random error correction and the burst error correction are decoded in parallel. Further, in this conventional example, transmission is performed using interleaving.

Next, the configuration of the encoder 1001 will be described. Reference numeral 1011 denotes a CRC code unit that receives an information bit sequence and generates and adds a CRC code for error detection. 1012 divides the information bit sequence to which the CRC code from the CRC code unit 1011 is added into a plurality of information blocks. The dividing unit 1013 receives the information block from the dividing unit 1012 and generates and adds a BCH code for the purpose of error correction. The BCH code unit 1014 receives the BCH code and the CRC code from the BCH coding unit 1013. An interleaving unit that combines the information blocks and outputs it to the wireless transmission unit 1003 using interleaving.

Next, the configuration of the decoder 1002 will be described. Reference numeral 1021 denotes a de-interleaving / dividing unit that deinterleaves the interleaved information from the wireless transmission unit 103 and divides the information into a plurality of information blocks.
22 is a random error correction decoding unit that corrects and decodes a random error of the information block to which the BCH code is added,
Reference numeral 1023 denotes a burst error correction decoding unit that corrects and decodes a burst error of an information block to which a BCH code has been added, and 1024 combines the divided information blocks from the random error correction decoding unit 1022 or the burst error correction decoding unit 1023. The synthesizing unit 1025 is a synthesizing unit 1024
A CRC error detection decoding unit 1026 that performs a CRC error detection on the information to which the CRC code has been added is a selection unit.

Next, the operation of the conventional encoder / decoder shown in FIG. 10 will be described. First, in the encoder 1001, C
RC code section 1011 receives an information bit sequence, CRC-codes this information bit sequence (hereinafter referred to as A sequence) to generate redundant bits used for error detection coding, and is composed of A sequence and redundant bits. Generate and output the B sequence. Next, the dividing unit 1012 outputs the CRC code 1011
When the B sequence is received, the B sequence is divided into k (k is a natural number) (three in FIG. 10) information blocks.
An i (i = 1 to 3) sequence is generated and output.

Next, the BCH encoding unit 1013
Each of the divided Bi (i = 1 to 3) sequences from B12 is subjected to BCH encoding to generate a Ci (i = 1 to 3) sequence. Interleaving section 1014 is BCH encoding section 1
Interleave the BCH-encoded Ci sequence from 013 to generate a D sequence for wireless transmission and output it to the transmission path. In this way, the encoder 1 generates a D sequence for wireless transmission from the A sequence as information bits. This D sequence is converted into an E sequence by the wireless transmission unit 1003 and output to the transmission path.

Next, in the decoder 1002, the E-sequence from the transmission path is deinterleaved / divided by the
Is input, and the E sequence is deinterleaved, and BC
It is divided into k Ei sequences corresponding to H code decoding. The random error correction decoding unit 1022 performs random error correction decoding on each of the individual Ei sequences to generate a Fi sequence. Also, burst error correction decoding section 1023
Generates a Hi sequence by performing burst error correction decoding on each of the individual Ei sequences.

The synthesizing unit 10 as final decoding means
Reference numeral 24 denotes the Fi from the random error correction decoding unit 1022.
The Ik sequence is synthesized from the sequence and the Hi sequence from the burst error correction decoding unit 1023, subjected to error correction decoding processing, and then delivered to the CRC error detection decoding unit 1025. The CRC error detection / decoding unit 1025 includes a combining unit 1024
When the Ik sequence is received from, the CRC error of the Ik sequence is detected and decoded. In addition, the selection unit 1026 outputs the I.D.
After removing the CRC redundant bits from the k-sequence, the sequence from which the redundant bits have been removed is used as a decoding result by the decoder 100.
Output from 2.

An error correction and error detection encoder and decoder using the above-described method have been devised.

Further, for example, Japanese Patent Application Laid-Open No. 63-257966
Japanese Patent Application Laid-Open Publication No. H11-15764 discloses a method for speeding up the decoding process by performing an error correction decoding process and an error detection decoding process in parallel when decoding a recording medium. FIG. 11 is a data array diagram showing an array of data used by an encoder and a decoder in the conventional decoding process disclosed in Japanese Patent Application Laid-Open No. 63-257966. FIG. FIG. 13 is a block diagram of a digital modulator including a conventional encoder shown in FIG. 13, and FIG. 13 is a block diagram of a digital demodulator including a decoder according to the conventional example shown in FIG.

In FIG. 12, reference numeral 1201 denotes a buffer memory, 1202 denotes an error correction circuit, 1203 denotes a cumulative addition circuit, 1204 denotes a CRC generator, 1205 denotes a digital modulation circuit, 1206 denotes a recording medium, 1207 denotes a host computer, and 1208 denotes an interface. It is.

In FIG. 13, reference numeral 1301 denotes a buffer memory, 1302 denotes an error correction circuit, 1303 denotes a cumulative addition circuit, 1304 denotes a CRC checker, 1305 denotes a digital demodulation circuit, 1306 denotes a recording medium, and FIG. It is the same as 1206. Reference numeral 1307 denotes a host computer, and 1308 denotes an interface.

The configuration and operation of the conventional error correction and error detection decoder will be described below with reference to FIGS. Data read from the recording medium 1306 is demodulated by the digital demodulation circuit 1305 shown in FIG. 13 and stored in the buffer memory 1301 so as to form the same sector format as that shown in FIG. At the same time, the demodulated data is input to a cumulative addition circuit 1303 as shown in the following equation, and XOR cumulative addition is performed.

[0020]

(Equation 1)

These Ij strikes are stored in the buffer memory 1301. Next, from the buffer memory 1301, the D scene, j
(I.e., each horizontal row in FIG. 11) and the error correction parity E scene, k are read out, and the error correction circuit 1302
The error size (pattern) and error position are calculated by the calculation, then error data is read from the buffer memory address corresponding to the error position, and the error size is XOR-added to the error data. , Error correction is executed.

After that, the data is read out from the Ij buffer memory 1301 corresponding to the error position, the magnitude of the error is XOR-added thereto, the CRC operation data is corrected, and the original data is corrected. Is stored again at the address. This operation is repeated i times for each i (one horizontal line). Finally, Ij ij = 103-0), C3, C2,
The data is read out in the order of C and C0, input to the CRC checker, and checked for errors.

As described above, a method has been devised in which the CRC error detection decoding processing is completed in a short time after the error correction processing is completed.

Further, for example, Japanese Patent Application Laid-Open No. 4-47813 discloses a method for increasing the speed in decoding an error correction code on a recording medium. In this conventional example, a Reed-Solomon encoder has hardware for realizing multiplication processing on a Galois field GF (2 to the fourth power), and the hardware performs multiplication on a Galois field GF (2 to the fourth power). ROM for storing a multiplication conversion table in which processing results are registered, and address generation for generating an address for directly accessing the multiplication addition table based on a multiplier and a multiplicand indicated as half-byte information on a Galois field GF (2 to the fourth power) A method has been devised that includes a circuit and obtains the solution of the multiplication on the basis of the multiplier and the multiplicand.

Further, for example, Japanese Unexamined Patent Publication No. Hei 6-39720 discloses a method for realizing error correction encoding and decoding processing for data of a plurality of signal formats on a recording medium with the same circuit configuration. In this conventional example, video signals having different data formats (NTS
In order to use the error correction circuit of C and PAL) in common, the error correction circuit is used for the signal format having a large data amount and the signal format having a small data amount is used among the two shared signal formats. The encoder system adds a dummy bit (0) to the insufficient data area in advance, performs error correction coding, performs recording with the exception of a dummy bit portion generated only with dummy data, and performs decoding at the time of decoding. A method of supplementing and decoding the predetermined dummy data has been devised.

[0026]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. Hei 6-18886.
The conventional error detection code and error correction code decoding device disclosed in Japanese Patent Application Laid-Open Publication No. H06-15764 performs a remainder operation process for decoding the error correction code, and then performs error correction using the result of the remainder operation process. Then, a remainder calculation process for decoding the error detection code is performed based on the error correction result. As described above, since the processing is sequential processing instead of parallel processing, there is a problem that processing time is required.

In the conventional error correction code decoding apparatus disclosed in Japanese Patent Laid-Open No. 4-47813, error correction decoding is performed by providing a ROM for storing a residue calculation conversion table in which the result of the remainder calculation is registered. In order to obtain a correct error detection code, there is a problem in that after performing error correction decoding, a remainder operation process for decoding the error detection code must be performed again. Was.

In the conventional error correction code decoding apparatus disclosed in Japanese Patent Application Laid-Open No. 63-257966, dummy bits are added to handle a plurality of formats. There is a problem that error detection at the time is not addressed.

In a conventional error correction code decoding apparatus, if a data format has a plurality of error detection inner codes having different formats within the same error correction outer code, the number of different formats is the same. Has to be provided with a decoding circuit for error detection codes.

The present invention has been made to solve such a problem, and in a broadband mobile communication system, a small-scale decoding is performed to speed up the processing of decoding a BCH code and a CRC code. It is intended to be realized by a circuit.

[0031]

An error correction code and error detection code decoder according to a first aspect of the present invention provides a BCH (Bose Chaudh) for performing a remainder operation on an information bit sequence.
uri Hocquenghem remainder operation circuit, and a CRC (Cyclic Redu) for performing a remainder operation on the information bit sequence differently from the BCH remainder operation circuit.
a residue operation circuit, and the BC
An error correction determination circuit that outputs an error position based on an output from an H residue arithmetic circuit, and a CRC error detection determination that performs a remainder operation on a part of the BCH remainder at the error position obtained from the error correction determination circuit Circuit and, of the remainder output by the CRC remainder operation circuit for the information bit sequence, a part at the error position is corrected based on the result of the remainder operation performed by the CRC error detection determination circuit. the result includes a CRC error detecting means for outputting a CRC error detection result, BCH
Error position in remainder operation result obtained from remainder operation circuit
Table storing the CRC remainder operation result for the part
And the remainder from the BCH remainder operation circuit.
An algorithm that directly accesses the table based on the result of extra computation
Address generation circuit for generating the address.
You.

In the decoder for error correction code and error detection code according to the second invention, the address generated by the address generation circuit uses the remainder from the BCH remainder operation circuit as it is.

An error correction code and error detection code decoder according to a third aspect of the present invention is an error correction code and error detection code decoder for decoding a source signal having a predetermined length. An information sequence encoded by adding dummy data (0) to the bit sequence as a short source signal so as to have the predetermined length is received or read out via a transmission line by a wireless line or a recording medium. Is performed, the error correction determination circuit that performs error determination on the remainder output that is the result calculated by the BCH remainder calculation circuit outputs the error position as the error position even when the error position is the virtual information bit sequence. is there.

The fourth error correction code and error detection code of a decoder according to the invention, for each information bit sequence formed by dividing the information bit sequence is subjected to each different CRC error detection coding, the different CRC error for each detection code, and CRC remainder calculation circuit, and ingredients Bei a CRC error detection judging circuit for performing a modulo operation on the error position obtained from the error correction determination circuit performs the remainder calculation for the information bit sequence CRC
The result of addition of the output from the remainder operation circuit and the output from the CRC remainder operation circuit that performs the remainder operation on the error position is output as a CRC error detection result for each CRC error detection code.

The method of decoding error correction code and error detection code according to the fifth invention performs a modulo operation on the information bit sequence BCH (Bose Chaudhuri Hoc
and a CRC (Cyclic Redundancy) for performing a remainder operation on the information bit sequence different from the BCH remainder operation step.
Check) a residue operation step, an error correction determination step of outputting an error position based on an output from the BCH residue operation step, and a part of the BCH residue at an error position obtained from the error correction determination step. C which performs remainder operation
An RC error detection determining step, and of the remainder at the error position of the remainder output by the remainder operation of the CRC remainder operation circuit on the information bit sequence,
A CRC error detection step of outputting, as a CRC error detection result, a result corrected by the C error detection determination step based on the result of the remainder operation.
Error part of the remainder operation result obtained from
A table for outputting a CRC remainder operation result;
The table based on the remainder calculation result from the remainder calculation step
Address generator that generates addresses that directly access
It is provided with a process.

In the decoding method of the error correction code and the error detection code according to the sixth invention, the address generated by the address generation step uses the remainder from the BCH remainder operation step as it is.

According to a seventh aspect of the present invention, in the method for decoding an error correction code and an error detection code for decoding a source signal having a predetermined length, the error correction code and the error detection code may be decoded more than the predetermined length. An information sequence encoded by adding dummy data (0) to the bit sequence as a short source signal so as to have the predetermined length is received or read out via a transmission line by a wireless line or a recording medium. Is performed, the error correction determination step of performing error determination on the remainder output that is the result of the calculation in the BCH remainder calculation step is to output the error position as the error position even when the error position is the virtual information bit sequence. is there.

The method of decoding the eighth error correction code and error detection code according to the invention, for each information bit sequence formed by dividing the information bit sequence is subjected to each different CRC error detection coding, the different CRC error for each detection code, and CRC remainder calculation step, and immediately <br/> Bei a CRC error detection determination step of performing a remainder operation on the resulting error location from the error correction determination step, the remainder operation for the information bit sequence CR
The addition result of the output from the C remainder calculation step and the output of the CRC remainder calculation step for performing the remainder calculation on the error position is output as a CRC error detection result for each CRC error detection code.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing one embodiment of a circuit for decoding an error correction code and an error detection code according to the present invention, and FIG. 2 shows the operation of the error correction code and error detection code decoding circuit shown in FIG. It is a flowchart. FIG. 3 is a data array diagram showing the structure of input data to the decoding circuit shown in FIG.
This indicates that the information section includes a CRC redundant bit and a BCH redundant bit. An embodiment of the BCH and CRC decoder according to the present invention will be described below with reference to FIGS. 1, 2 and 3.

In FIG . 1, reference numeral 101 denotes a BCH remainder operation circuit for performing a BCH remainder operation on input data; 102, a syndrome operation circuit for calculating an error position based on the operation result from the BCH remainder operation circuit 101; RO having a table indicating the relationship between the error position output from the arithmetic circuit and the remainder of the CRC remainder operation result
M is a CRC remainder operation circuit at an error position that outputs a CRC remainder operation result from an error position.

Further, 104 FIFO buffer for temporarily storing the input data, 105 is a write counter that creates a write address of the FIFO buffer, the read counter to create a read address of the FIFO buffer 106, 107 a syndrome calculating circuit 102 , And data from the read counter 106. If the two data match, the comparator outputs 1; otherwise, it outputs 0. The comparator 108 modulates the input data by a CRC generating polynomial to perform a remainder operation. , A CRC remainder operation circuit that outputs the remainder (0: remainder 0, 1: other than remainder 0), and 109 and 110 are XOR operation circuits that perform an XOR operation on two input data.

Next, will be described with reference to FIG. 2 the operation of the BCH and CRC decoder shown in FIG. The data input to the BCH and CRC decoders are
The data is input to the IFO buffer 104, and the data obtained by removing the BCH redundant bits is input to the CRC remainder operation circuit 108. The BCH remainder operation circuit 101 converts the input data into BCH
A remainder operation is performed using the generator polynomial, and the remainder is output. The output result is input to a syndrome operation circuit 102 that calculates an error position of input data.

[0043] In addition, FIFO buffer 107 you store the input data. At the time of writing, the write counter 105 is incremented, and at the time of reading, the read counter 106 is incremented.

The syndrome operation circuit 102 calculates an error position based on the remainder from the BCH remainder operation circuit 101. The comparator 107 inputs the error position from the syndrome operation circuit 102, outputs “1” when the error position matches the value of the read counter, and writes it to the FIFO buffer 104 via the XOR operation circuit 109. And output the data. When the read counter 106 from the FIFO buffer 104 matches the error position input to the comparator 107, that is, the input data written in the FIFO buffer 104 starts reading at the timing when the error position is detected by the comparator 107, The XOR operation circuit 109 inverts a certain bit, and outputs error-corrected data.

The input data input to the CRC remainder operation circuit 108 is subjected to a remainder operation using a CRC generating polynomial, and the remainder (0 or 1) is output. On the other hand, the error position calculated by the syndrome operation circuit 102 is the CRC at the error position.
The remainder is input to the remainder operation circuit 103. C at the error position
The RC remainder operation circuit 103 outputs a remainder (0 or 1) obtained by performing a remainder operation on the data in which only the bit corresponding to the error position is set to 1 based on the input error position by using a CRC generation polynomial. Input to the XOR operation circuit 110. The XOR operation circuit 110 performs an XOR operation on the previously obtained output result of the CRC remainder operation circuit 108 and the CRC remainder operation result at the error position, and outputs the result as an error detection result.

In this embodiment, the syndrome calculation circuit 102 calculates the error position. However, the RO having a table indicating the relationship between the BCH remainder calculation result and the error position is used.
M may be replaced by the syndrome operation circuit 102.

[0047] According to this embodiment, not only performed in parallel and BCH remainder calculation and CRC remainder calculation for the information bit sequence, the error detection result from the CRC remainder calculation result for the error location in the ROM table , The CRC remainder calculation for the error correction position can be performed in a short time, and the time difference between the error correction decoding processing and the error detection decoding processing can be shortened. Therefore, there is an effect that the speed of decoding the BCH code and the CRC code can be increased.

[0048] Embodiment 2. FIG. 4 is a block diagram showing another embodiment of the error correction code and error detection code decoding circuit according to the present invention. FIG. 5 shows the operation of the error correction code and error detection code decoding circuit shown in FIG. It is a flowchart which shows.

In FIG . 4, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. 401 is an error correction ROM corresponding to the output from the BCH remainder operation circuit 101 based on the output.
And an address generation circuit 402 for generating the respective addresses of the CRC remainder calculation result ROM 103 at the error position, and an error correction ROM 402 for outputting an error position corresponding to the address from the address generation circuit 401.

The address generation circuit 401 generates, based on the output from the BCH remainder operation circuit 101, the addresses of the error correction ROM 402 corresponding to the output and the CRC remainder operation result ROM 103 at the error position. The error correction ROM 402 has a table indicating the correspondence between the address and the error position, and the CRC remainder operation result ROM at the error position also outputs the remainder of the CRC remainder operation of the data using the address and the error position.

Next, it will be described with reference to the flowchart of FIG. 5 the operation of the decoder shown in FIG. The data input to the BCH and CRC decoder are transmitted to the BCH remainder operation circuit 101 and the FIFO.
The data is input to the buffer 104 and the CRC remainder operation circuit 108
Is input with data from which the BCH redundant bits shown in FIG. 3 have been removed. The BCH remainder operation circuit 101 performs a remainder operation on the input data using a generator polynomial and outputs the remainder, and the output result is input to the address generation circuit 401.

The address generation circuit 401 outputs an address corresponding to the remainder input from the BCH remainder operation circuit 101. This address is input to the error correction ROM 402 and the CRC remainder result ROM 103 at the error correction position. The error position written at the address is read by the error correction ROM 402 and input to the comparator 107. When the read counter 106 from the FIFO buffer 104 matches the error position input to the comparator 107, that is, at the timing when the comparator 107 detects the error position, the reading of the input data written in the FIFO buffer 104 is started, and the error is detected. Bit with XO
The R operation circuit 109 outputs data that has been subjected to error correction by inversion.

The input data input to the CRC remainder operation circuit 108 is subjected to a remainder operation using a CRC generator polynomial, and the remainder (0 or 1) is output. On the other hand, the address generation circuit 401 uses the address corresponding to the remainder output from the BCH remainder operation circuit 101 to calculate the CRC remainder operation at the error position written at the address in the CRC remainder operation ROM 103 at the error position. Read the result. XO
The R operation circuit 110 outputs a corrected correct error detection result by XORing the CRC remainder operation result at the error position with the output result of the CRC remainder operation circuit obtained in advance.

[0054] According to this embodiment, an effect that the error detection result from the CRC remainder calculation result for the error position to directly output by the table in the ROM, a in a short time an error detection decoding process .

In this embodiment, the address generation circuit calculates the address in the ROM from the output result of the BCH remainder operation circuit, but a table in which the output result of the BCH remainder operation circuit itself is used as an address is stored in the ROM. May be configured. In this case, the address generated by the address generation circuit uses the remainder from the BCH remainder operation circuit as it is, so that the address generation circuit can be omitted, not only reducing the circuit scale but also reducing the processing delay and increasing the speed. This has the effect that it can be achieved.

[0056] In addition, B with a multiple-bit error correction capability
When the CH code is used, a plurality of error positions are generated, so that a structure having a plurality of ROMs for one remainder may be adopted.

[0057] Embodiment 3. FIG. 6 is an explanatory diagram showing positions of dummy bits and errors in an error correction code and error detection code decoder according to the present invention, and FIG. 7 shows BCH and C in this embodiment.
It is a flowchart which shows operation | movement of RC decoding processing. FIG.
1 is used in this embodiment as well. Hereinafter, this embodiment will be described with reference to FIGS. 4, 6, and 7. FIG.

When a plurality of data formats having different data lengths are encoded or decoded by the same encoder and decoder as shown in FIG . Is configured to correspond to the data having the maximum data length. When the encoder and the decoder configured as described above encode data having a data length less than the maximum data length, bits that are shorter than the maximum data length of the data are replaced with dummy bits (0). When the BCH code is further encoded, dummy bits are deleted from the data, the calculated CRC redundant bits and BCH redundant bits are added, and then output or recorded on a transmission path. Write to media.

Meanwhile, the decoder as shown in Figure 7 assumes that the maximum data length of the input data is input, into the decoding process. As shown in FIG. 7, the data input to the BCH and CRC decoders is regarded as the input of the maximum information length, and only the input data is supplied to the decoder in the reset state by the BCH remainder operation circuit 101 and the FIFO buffer. 104
, And the data from which the BCH redundant bits have been removed is input to the CRC remainder operation circuit 108. Since the BCH remainder operation circuit 101 inputs the input data shorter than the maximum information length from the reset state and performs the remainder operation using the generator polynomial after the completion of the input, the portion where the maximum information length is insufficient is “0”. The remainder is output assuming that the maximum information length is input, and the remainder as the output result is input to the address generation circuit 401.

The address generation circuit 401 generates an address corresponding to the input remainder and outputs the address to the CRC remainder calculation result ROM and the error correction ROM at the error correction position. The error correction ROM 402 reads an error position written at the address based on the address from the address generation circuit 401 and inputs the read error position to the comparator 107. The input data written in the FIFO buffer 104 starts to be read at the timing when the error position is input to the comparator 107, and the read counter 106 from the FIFO buffer 104 and the bit where the error position input to the comparator 107 matches, that is, Replace the erroneous bit with X
The output data is inverted and error-corrected by the OR operation circuit to generate and output. However, the virtual information part is the comparator 1
07 discarded.

[0061] The processing and readout of the CRC remainder calculation result for ROM103 at the error position of the CRC remainder calculation circuit 108 is performed in the same manner as the second embodiment.

In the output data generation method described in this embodiment, although the virtual information portion is discarded by the comparator 107, data in which the dummy bit “0” is put in the FIFO buffer 104 is written, and the virtual You may comprise so that a part may be discarded.

[0063] According to this embodiment, including the table by the same ROM as the decoder of the maximum data length, using a BCH error correction circuit and the CRC error detection circuit, the dummy bit portions missing than the maximum length By supplementing with
There is an effect that encoding and decoding can be flexibly performed even on data having different data lengths.

[0064] Embodiment 4. FIG. 8 is a block diagram showing another embodiment of a decoding circuit for an error correction code and an error detection code according to the present invention.
4 denote the same or corresponding parts. FIG.
FIG. 10 is a data arrangement diagram showing a configuration of input data of the error correction code and the error detection code shown in FIG. 8 to the decoding circuit, and shows a relationship among an information part, a CRC redundant bit, and a BCH redundant bit.

Next, the operation of the decoder shown in FIG. As shown in FIG. 9, an encoder (not shown) performs CRC coding on N information bit sequences Xi (i = iN) to generate redundant bits Di (i = 〜N). However, the lengths of Di are different from each other. The encoder performs BCH encoding on the entire generated information bit sequence Xi + Di (i = 〜N), adds a redundant bit C, and sends out the information bit sequence to a transmission path or writes it on a recording medium.

As shown in FIG . 8, the encoder according to the present invention is the same as the configuration circuit of the encoder of the second embodiment,
CRC remainder operation circuit 1 as many as the number of types of C generator polynomials
08 (108a-c in the figure) and CR at N error positions
It has a ROM 103 for C remainder calculation (103a to 103c in the figure). Hereinafter, the decoding process according to the present embodiment will be described with reference to FIG.

The data input to the BCH and CRC decoder are output from the BCH remainder operation circuit 101 and the FIFO buffer 10.
4 and the CRC remainder operation circuit 108
The data from which the redundant bits have been removed are input to the CRC remainder operation circuits 108a to 108c corresponding to the respective CRC generating polynomials. However, this is distributed according to a predetermined bit position in the input data. On the other hand, BC
The input data itself is input to the H remainder operation circuit 101, the remainder operation is performed by a generator polynomial, and the remainder is output.

The remainder as the output result is stored in the address generation circuit 4
01, the address generation circuit 401 calculates an address corresponding to the remainder, reads the error position written at the address position in the error correction ROMs 103a to 103c using the address, and inputs the error position to the comparator 107. You.
On the other hand, the input data written in the FIFO buffer 104 starts reading at the timing when the error position is input to the comparator 107, and the read counter 106 from the FIFO buffer 104 matches the bit where the error position input to the comparator matches. That is, an error-corrected data is generated by inverting an erroneous bit by an XOR operation circuit and output as corrected data.

[0069] Further, the CRC remainder calculation circuit 108a~c
Performs a remainder operation on the divided input data using a CRC generating polynomial, and outputs a remainder (0 or 1).
The address generation circuit 401 is a BCH remainder operation circuit 1
Based on the remainder output from the N.01, a corresponding ROM is selected from the CRC remainder calculation ROMs 103a to 103c at the N error positions, a corresponding address is generated, and the CRC remainder calculation ROM 103 at each error position is generated. 103a-
c), the result of the CRC remainder operation at the error position written at the address in the corresponding one of the XOR operation circuits 110 (any one of 110a to 110c) is read out.
) And the corresponding CRC remainder operation circuit 108 (1
08a-c) and the result of the CRC remainder operation at the error position are XORed, and output as an error detection result of the corresponding input data.

[0070] According to this embodiment, the CRC remainder calculation circuit, and a CRC error detection judging circuit for performing a modulo operation on the resulting error location from the error correction determination circuit, by having each different CRC error detection code Since the addition of the CRC redundant bits to each of the plurality of divided information bit sequences is performed in parallel, there is an effect that the speed of the entire error correction coding can be increased.

[0071]

Since the present invention is configured as described above, the following effects can be obtained.

[0072] According to the first aspect, C for error location
The error detection result from the RC remainder operation result is stored in a table in ROM.
Error detection and decoding processing
This has the effect that it can be performed in between.

[0073] According to the second invention, since the address which the address generation circuit generates directly using residue from BCH remainder operation circuit, for Habukeru the address generation circuit,
In addition to reducing the circuit scale, there is an effect that the processing delay can be reduced and the speed can be increased.

[0074] According to the third invention, using the circuit of the decoder in the same configuration of the maximum data length, by supplementing a portion missing than the maximum length in the dummy bit for different data length of data Also has an effect that encoding and decoding can be performed flexibly.

[0075] According to a fourth aspect of the present invention, the CRC remainder calculation circuit, and a CRC error detection judging circuit for performing a modulo operation on the resulting error location from the error correction determination circuit, different CR
By providing each C error detection code, CRC redundant bits are added in parallel to each of a plurality of divided information bit sequences, so that the entire error correction coding can be speeded up.

[0076] According to the fifth aspect, C for error location
Error detection result from RC remainder operation result is shown in table
Since direct output is performed, error detection decoding processing can be performed in a short time.
This has the effect of being able to

[0077] According to the sixth invention, since the address which the address generation step generates as it is using residue from BCH remainder operation process, since Habukeru the address generation step,
This has the effect of eliminating the processing delay and increasing the speed.

[0078] According to the seventh aspect, using the decoding method corresponding to the maximum data length, by supplementing a portion missing than the maximum length in the dummy bit, flexibly for different data length of data There is an effect that encoding and decoding can be performed.

[0079] According to the eighth invention, the CRC remainder calculation step, and a CRC error detection determination step of performing a remainder operation on the resulting error location from the error correction determination step, different CR
By providing each C error detection code, CRC redundant bits are added in parallel to each of a plurality of divided information bit sequences, so that the entire error correction coding can be speeded up.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a circuit for decoding an error correction code and an error detection code according to the present invention.

FIG. 2 is a flowchart showing the operation of the error correction code and error detection code decoding circuit shown in FIG.

FIG. 3 is a data array diagram showing a structure of input data to a decoding circuit shown in FIG. 1;

FIG. 4 is a configuration diagram showing another embodiment of the error correction code and error detection code decoding circuit according to the present invention.

FIG. 5 is a flowchart showing the operation of the error correction code and error detection code decoding circuit shown in FIG. 4;

FIG. 6 is an explanatory diagram showing positions of dummy bits and errors in a decoder for an error correction code and an error detection code according to the present invention.

FIG. 7 is a flowchart showing an operation of a BCH and CRC decoding process in this embodiment.

FIG. 8 is a block diagram showing another embodiment of the error correction code and error detection code decoding circuit according to the present invention.

9 is a data array diagram showing a configuration of input data to a decoding circuit of the error correction code and the error detection code shown in FIG.

FIG. 10 is a configuration diagram of a conventional encoder and decoder disclosed in Japanese Patent Application Laid-Open No. H6-188862.

FIG. 11 is a data arrangement diagram showing an arrangement of data used by an encoder and a decoder in a conventional decoding process disclosed in Japanese Patent Application Laid-Open No. 63-257966.

12 is a configuration diagram of a digital modulator including the encoder according to the conventional example shown in FIG.

13 is a configuration diagram of a digital demodulator including the decoder according to the conventional example shown in FIG.

[Explanation of symbols]

 101 BCH remainder operation circuit 102 syndrome operation circuit 103 CRC remainder operation circuit at error position 104 FIFO buffer 105 write counter 106 read counter 107 comparator 108 CRC remainder operation circuit 109 XOR operation circuit 110 XOR operation circuit 401 address generation circuit 402 error correction ROM 1001 Encoder 1002 Decoder 1003 Radio transmission unit 1011 CRC encoding unit 1012 Division unit 1013 BCH encoding unit 1014 Interleaving unit 1021 De-interleaving unit / division unit 1022 Random error correction decoding unit 1023 Burst error correction decoding unit 1024 Synthesis Unit 1025 CRC error detection decoding unit 1026 selection unit 1201 buffer memory 1202 error correction circuit 1203 cumulative addition circuit 1204 CRC Enereta 1205 digital modulating circuit 1206 recording medium 1207 host computer 1208 interface 1301 buffer memory 1302 error correction circuit 1303 cumulative addition circuit 1304 CRC checker 1305 digital demodulation circuit 1306 recording medium 1307 host computer 1308 interface

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Keijiro Take 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Shuji Ito 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric (56) References JP-A-2-21723 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00 G11B 20/00

Claims (8)

(57) [Claims] 1. A BCH (Bose Chaudhuri Hocquen) for performing a remainder operation on an information bit sequence.
ghem) remainder operation circuit, and a CRC (Cyclic Red) for performing a remainder operation on the information bit sequence differently from the BCH remainder operation circuit.
(undancy Check) remainder operation circuit;
An error correction determination circuit that outputs an error position based on an output from the CH remainder operation circuit; and a CRC error detection determination that performs a remainder operation on a part of the BCH remainder at the error position obtained from the error correction determination circuit. Circuit, of the remainder output by the CRC remainder operation circuit for the information bit sequence, a part at the error position is corrected based on the result of the remainder operation performed by the CRC error detection determination circuit. CRC error detection means for outputting a result as a CRC error detection result.
In mis Ri correction code and error detection code of the decoder has, before
Of the remainder calculation result obtained from the BCH remainder calculation circuit.
CRC remainder operation result for error location part is stored
ROM accommodating table and BCH remainder operation circuit
Direct access to the table based on the result of the remainder operation from
Address generating circuit for generating an address to
Decoding of error correction code and error detection code
Bowl . 2. The error correction code and error detection code decoder according to claim 1 , wherein the address generated by the address generation circuit uses the remainder from the BCH remainder operation circuit as it is. 3. A transmitting encoded information sequence by adding dummy data (0) to be a predetermined length for the bit sequence is a short original signal than Jo Tokoro length by the radio network An error correction determination circuit that performs error determination on a remainder output that is a result calculated by the BCH remainder arithmetic circuit after performing reception or reading through a channel or a recording medium, wherein the error position is the virtual information bit sequence. 2. An output as an error position even in a certain case.
Or a decoder for the error correction code and the error detection code according to claim 2 . 4. A different CRC error detection coding is performed for each information bit sequence obtained by dividing the information bit sequence, and for each of the different CRC error detection codes , a CRC remainder operation circuit and an error correction determination circuit obtained is immediately Bei a CRC error detection judging circuit for performing a modulo operation on the error position, performs remainder calculation for the output to the error position from the CRC remainder calculation circuit for performing a modulo operation on the information bit sequence CR
The error correction code and the error detection code decoding according to claim 1 or 2 , wherein the addition result of the output of the C remainder operation circuit is output as a CRC error detection result for each of the CRC error detection codes. vessel. 5. A BCH (Bose Chaudhuri Hocquen) for performing a remainder operation on an information bit sequence.
ghem) residue operation step, and a CRC (Cyclic Red) for performing a residue operation on the information bit sequence different from the BCH residue operation step.
(undancy check) remainder operation step;
An error correction determination step of outputting an error position based on an output from the CH remainder calculation step, and a CRC error detection determination of performing a remainder calculation on a part of the BCH remainder at the error position obtained from the error correction determination step And, of the remainder output by the remainder calculation of the CRC remainder operation circuit on the information bit sequence, a part at the error position is corrected based on the result of the remainder operation performed by the CRC error detection determination step. CRC
Decoding method smell false Ri correction code and the error detecting code; and a CRC error detection step of outputting the error detection result
The remainder operation result obtained from the BCH remainder operation step
The result of the CRC remainder operation for the part at the error position in
And the remainder from the BCH remainder operation step
An address that directly accesses the table based on the operation result
Address generating step of generating addresses.
A decoding method of an error correction code and an error detection code. 6. The decoding method for an error correction code and an error detection code according to claim 5 , wherein the address generated by the address generation step uses the remainder from the BCH remainder operation step as it is. 7. A decoding method of an error correction code and an error detection code for decoding a source signal having a predetermined length, wherein a bit sequence which is a source signal shorter than the predetermined length has a predetermined length. After receiving or reading out the information sequence encoded by adding the dummy data (0) through a transmission line by a wireless line or a recording medium,
The error correction judging step of judging an error with respect to a remainder output obtained as a result of the operation performed in the BCH remainder operation step outputs the error position as the error position even when the error position is the virtual information bit sequence. The decoding method of an error correction code and an error detection code according to claim 5 or 6 . 8. A different CRC error detection coding is performed for each information bit sequence obtained by dividing the information bit sequence, and for each of the different CRC error detection codes , a CRC remainder calculation step and an error correction determination step are performed. CR obtained is immediately Bei a CRC error detection determination step of performing a remainder operation on the error position, performs remainder calculation for the output to the error position from the CRC remainder calculation step of performing a modulo operation on the information bit sequence
7. The decoding of an error correction code and an error detection code according to claim 5 , wherein an addition result of an output of the C remainder operation step is output as a CRC error detection result for each of the CRC error detection codes. Method.