JPS61273019A - Syndrome calculating device - Google Patents

Abstract

PURPOSE:To simplify and quicken the calculation by using two sets of calculation circuits including a code polynomial register, a cyclic register, a coincidence detection circuit and an adder circuit. CONSTITUTION:Two sets of the calculation circuits having the code polynomial registers (X)7-9, 16-18, the cyclic registers (Y)25-27, 34-36, the coincidence detection circuit 57 and the adder circuits 37-39, 43-45 are provided in parallel and the cyclic direction of the cyclic registers is set reversely to each other. The data of the registers Y is circulated until the data is equal to the input data of the high-order term of the registers x and when it is detected by the detection circuit 57 in any calculation circuit that both the high-order terms are equal, the content of each register of the high-order and low-order terms is added, the content of the low-order term, the next term of the code polynomi al is inputted to the registers of the low-order term, the data of the generation polynomial is inputted to the registers Y from the high-order term and circulatd, the said processing is repeated until the lowest-order term is inputted to the registers X, the division by using the generation polynomial is performed and the calculation is finished when the division of the one calculation circuit is finished.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a syndrome calculation device, and more specifically, the present invention relates to a syndrome calculation device.
haudhuri-11ocquenqhem Cod
Reed-Solomon mark Fij (Re
The present invention relates to a syndrome calculation device that calculates a syndrome from a received word when correcting random errors or the like in received data using the ED-Solomon Code.

<Prior Art and Problems to be Solved by the Invention> In highly reliable digital data transmission, data is encoded and transmitted in order to detect and correct error patterns from received data. In this case, it is most preferable to use a Reed-Solomon code, which is a type of BCH code that has the highest correcting ability for random errors, as the error correction code.

In particular, optical disk devices developed in recent years have a higher error rate than conventional magnetic disk devices, due to the roughness of the surface of the optical disk itself, disturbance of the υ-bow, etc. It is essential for an optical disc playback device to incorporate a decoding device for detecting and correcting errors in data read from an optical disc.

Here, to briefly explain the decoding, ■ Find the syndrome from the received word, ■ Find the error location polynomial σ(X) from the syndrome! ! The procedure is as follows: (1) find the backlight of the root of σ(X) (the number of error positions), (2) find the error position from the number of error positions, and correct it.

By the way, the Reed-Solomon code is a Galois field GF ((
), but assuming a digital circuit, it is sufficient to shift q=2. This Galois field GF (2”
), then α2m-1=1, and if m bits are one symbol, the generator polynomial for t-symbol error correction is Q (X)= (x+α)(x+a2)-( x+a”)
The syndrome S obtained from this generator polynomial g(X) is the remainder when the code polynomial f(x) is divided by (×i÷1+α).

For example, in a two-symbol error-correcting Reed-Solomon code on the Galois field GF(23), the generator polynomial Q(X)
is a (x)−(x+α)(x+a)<x+a3)(
X+α4), so if we shift the sign polynomial to f(x), each syndrome will be as follows: So is the remainder of f(x)/(x+α), Sl is the remainder of f(x)/(x+α), and S2 is the remainder of f(x)/(x+α). f<X)
/CX+α), S3 is f(x)/(x+a
'> (1) remainder, which can be obtained as follows.

Therefore, each syndrome s obtained by the above formula
, s , s2. By obtaining the error location polynomial based on s3 and finding the backlight of the root of the error location polynomial, the error location can be found and corrected.

Among the above series of calculations, each syndrome S. .

Sl, S2. The calculation of S3 is surprisingly troublesome, and in order to perform this calculation at high speed, conventionally, for example, a ROM table has been used.

This invention does not use a ROM table, etc.
It is an object of the present invention to provide a syndrome calculation device that can easily and quickly perform 11 calculations of syndromes using hardware such as registers.

Means for Solving Problems> In order to achieve the above object, the syndrome calculation device of the present invention inputs code polynomials in order from the high-order terms and shifts them from the low-order terms, thereby converting the two-term A register for the code polynomial that stores the number, a cyclic register that inputs the generator polynomial in order from the high-order term side, and a match between the contents of the high-order term side of the register for the code polynomial and the contents of the high-order term side of the cyclic register is detected. and an addition circuit that adds the contents of both registers on the high-order term side and the contents of both registers on the low-order term side at the time when the coincidence of contents is detected by the coincidence detection circuit. Two sets are provided in parallel, and the circulation direction of one set of cyclic registers is set opposite to the circulation direction of the other cyclic register.

However, among the registers for code polynomials of the two sets of calculation circuits, the contents of the register on the low-order term side of the calculation circuit on which a match has been detected are shifted to the registers on the high-order term side for code polynomials of both calculation circuits. It may be something.

In the syndrome calculation device with the above configuration, in each set of calculation circuits, the high-order term side of the register for the generator polynomial is inputted until the data becomes equal to the data input to the high-order term side of the register for the code polynomial, and Cycling the data on the lower order term side,
When the coincidence detection circuit detects that the data on both high-order term sides in either set of calculation circuits are equal, the contents of each register on the high-order term side and the low-order term side are added, and the register for the code polynomial is added. Shift the contents of the low-order term side to the high-order term side, input the data of the next term of the code polynomial into the register on the low-order side, and input the data of the generator polynomial again into the register for the generator polynomial, starting from the high-order term side. The data on the high-order term side and the low-order term side of the register for the generator polynomial are input, and the above process is repeated until the data on the lowest-order term side of the code polynomial is input into the register for the code polynomial. Syndrome calculation is performed by repeatedly dividing the code polynomial by the generating polynomial, and when the division in one of the calculation circuits is completed, by retrieving the contents of the lower-order term side of the register for the code polynomial in the calculation circuit. will be completed.

That is, conventionally, such syndrome calculations were performed using RO
This was done using a table of M, etc., but there was a register into which the code polynomial data was input in order from the high-order term side, a register into which the generator polynomial data was input in order from the high-order term side, and a register in which the data of the generator polynomial was input in order from the high-order term side. The syndrome can be calculated using only hardware consisting of a match detection circuit that detects when the contents of two registers match, and an adder circuit that adds the contents of both registers when the registers are small.
= 1, the same calculation result can be obtained by multiplying by I-1 α-1 (however, i = 2m-1-j) instead of multiplying by αj, and each term of the generator polynomial is By having two sets of calculation circuits whose circulation directions are reversed perform calculations at the same time, it is possible to use the one that takes a shorter time to complete the calculation.

Also, among the registers for the sign polynomial of the two sets of calculation circuits, the contents of the register on the low-order term side of the calculation circuit on the side where a match was detected are shifted to the register on the high-order term side for the sign polynomial of the double sieve circuit. In this case, the number of cycles of the generator polynomial register for each digit of the code polynomial is (2m-
1)/2 or less, which is preferable because the overall calculation time can be further shortened.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 5 is a block diagram schematically showing processing for performing flI encoding using the syndrome calculation device according to the present invention, and is a block diagram schematically showing processing for performing flI encoding for each syndrome S, S82. In the calculation circuit that calculates S3, respectively.

Each element of the generator polynomial (X+α), (X+α2), (x+α ), (X+α
4) and input the code polynomial data to all the calculation circuits mentioned above, each syndrome S
, SS S3 bones, these syndrome S. , Sl, S2゜S3
By inputting this into the decoding device, it is possible to obtain an error-corrected code sequence.

Note that α is the primitive element of the Galois field GF (23), and if expressed in 3 bits, 1=001, α=010, α”=100°α
=011. α'=110. α5=i i 1゜α6-1
It is 01.

Therefore, multiplying by α is equivalent to multiplying by α-3, multiplying by α is equivalent to multiplying by α-2, and multiplying by α6 is equivalent to multiplying by α-1. .

FIG. 1 is an electrical circuit diagram showing a syndrome calculation device, and shows syndromes S, Sl, 82. This is to calculate one of S3. This syndrome quadrupling device is composed of two sets of calculation circuits A and B, but in both calculation circuits, the direction of data circulation in the register that inputs the generator polynomial in order from the higher order term is set to be opposite. Since the only difference is in points, needle ring circuit A will be explained in detail below, and calculation circuit B will be explained only in terms of differences.

(Il AND gate (11 (21 (
31, data consisting of 3 bits of each term of the code polynomial is applied bit by bit in order from the higher-order term side, and AND Gut (1)
(2) The output signals from (3) are sent to the register (7) through the OR gate G+1) (5) (61), respectively.
(8) Applied to (9).

Then, the output signal from the register (71 (81 (9)) is connected to the AND gate (1) by the shift signal.
)(21(3) To synchronize open Karel AND
l(11)(12), and OR gate(13)(14
H15) is applied to the register (1G) (17018).

Therefore, the shift signal is AND gate (1) (2)
(3) Each time applied to (io) (11) (12),
The contents of the register (sword (8) (9) are the register (161)
(17) and (18), and the data of the next digit of the code polynomial is input to register (7') (81 (9)).

Also, an AND gate that is opened by a load signal.

Data consisting of 3 bits of the low-order term of the generator polynomial is applied bit by bit to (19), (20), and (21), and the output signals from the AND gates (19), (20, and 21) are connected to the OR gate ( It is applied to registers (25H26) (27) via 22N23) (24).

Then, the AND gate (19
)(20)(21) AND gate (
28) Apply data consisting of 3 bits of the higher-order term of the generator polynomial to (29) and (30) bit by bit, AND! The output signals from the
It is applied to the register (34) (35036) via (33).

Apply the contents of registers (7) (8) (9) and the contents of registers (25) (26) (27) to the XOR gates (37) (38) (39), 'x OR
The gate (37) (38) (39) Carano output signal is passed through the AND gate (40) (41) (
42), and the above OR gate (4] (5) (6)
By applying the voltage to the register (7) (81 (9)) through It constitutes an adder circuit that can input to registers (7), (8), and (9).

Apply the contents of the above registers (16), (17), and (18) and the contents of registers (34) (35036) to the XOR gates (43), (44), and (45), and
' - (43) (44) (45) color (1) output signal is input to the AND gate (4G) by the above addition signal.
(41) AND gate (4) opened in synchronization with (42)
6) (47) (4B), and the above OR gate (13)
(14) and (15) through the registers (1G) (17).
018), the above register (16)
The contents of (17) and (18) and registers (34) and (3)
5) Add the contents of (36) and register (16) (17)
) (18).

The contents of the register (26) are input to the AND gate (51) heard by the cyclic signal and the OR gate (24).
) to the register (27), and the register (
27) to the register (25) via the AND gate (49), which is opened in synchronization with the AND gate (51) by the circular signal, and the OR gate (22).
and set the contents of the registers (25) and (27) to XO
The output signal from the XOR gate (52) is applied to the R gate (52), and the output signal from the XOR gate (52) is applied to the AND gate (
49) AND gate (50) opened in synchronization with (51)
), and the register (
26), a cyclic register is constructed that sequentially transfers the contents of the registers (25), (26), and (27) to the adjacent registers each time the cyclic signal is applied.

Regarding registers (34), (35), and (36), b1 AND gate (53054
) (55) and Oyohi xOR gate (56), the register (3
4) It constitutes a cyclic register that sequentially moves the contents of (35) and (36) to the adjacent register.

In addition, the contents of the registers (16), (17), and (18) above,
and the contents of registers (34), (35), and (3B) are applied to a coincidence detection circuit (57), and an output signal from the coincidence detection circuit (57) is applied to a control circuit (58).

Further, the contents of the register (71 (81) (9)) are outputted as syndrome calculation data and applied to the decoding device shown in FIG.

Note that the clock signal shown in FIG. 4E is sent to registers (7) (8).
H9) (16) (17N1B) is applied to the clock input terminal of the register (25) (26H27) (34) (35) (
36) is applied to the clock input terminal.

(Ml The difference between calculation circuit B and calculation circuit A above is that the XOR gate (52)
56), the contents of registers (26) and (27) are applied to the XOR gate (52), and the
The output signal from the R gate (52) is connected to the AND gate (49).
)1. : Mark 71 L/, l/ :,' s9 (34
)(35>(Apply the D content to the XOR gate (56), and apply the output signal from the XOR gate (56) to the AN
Apply to D gate (53) and register (25026)
The contents of (27) and register (34H35) (3G
) is circulated in the opposite direction to the above calculation circuit.

However, addition signals, shift signals, load signals, cyclic signals,
and clock signals are set to ti13H in accordance with the state of calculation circuit B. Therefore,
In calculation circuit A, multiplication by α can be performed by circulating the contents of the register once, whereas in calculation circuit B, multiplication by α-1 can be performed by circulating the contents of register once. can be made to do so.

The operation of the calculation circuit constituting the syndrome calculation device described above is as shown in FIG. 2. In step (3), the shift signal is set to high level, and the clock signal for the upper register is input twice. register (7) (8) (9) and register (16)
) (17018), input the code polynomial every two terms bits in order from the higher order term, and in step (2), set the load signal to high level and input the clock signal for the lower register once. (25)(
26) (27), and registers (34) (35) (3
6), input the generating polynomial bit by bit in order from the higher-order term, and in step 2, register (1B) (1
7N18H34) Determine whether the contents of (35) and (36) match, and if they do not match. In step (2), by setting the cyclic signal to high level and inputting the clock signal for the lower register once,
Register (25) (26) (27) (34) (35) (
Each term in 3B) is cycled once and the determination in step (2) is performed again.

If it is determined that the contents of both registers match, in step (2), the addition signal is set to high level, and the clock signal for the lower register is input once, so that the lower register (25 )(26) (
27H34) (35) (3G) respectively in the upper register (sword (81 (91 (16) (17) (18
), and it is determined in step ■ whether all terms of the code polynomial have been calculated. If it is determined that there are terms that have not been calculated, the shift signal is set to a high level in step ■. At the same time, by inputting the clock signal for the upper register once, the contents of the upper register (71(8) (9)) can be changed to register (1).
6) (17) (18), and the next term of the code polynomial is transferred bit by bit to the register (7) +8) (9
1, and in step 2, the load signal is set to high level, and the load signal for the lower register is inputted once, so that the lower register (2502
B) (27), and register (34H35) (36)
The generator polynomial is input bit by bit in order from the higher-order terms, and then the determination and processing from step (2) onwards is performed.

If it is determined in step (■) that all terms have been calculated, in step (2), the calculation of the syndrome by the other calculation circuit is stopped, and the clock signal for the upper register 9 is input once. By doing so, the contents of registers (7), (8), and (9) are output as the syndrome calculation results.

That is, the above-mentioned determination and processing are performed simultaneously in both calculation circuits A and B, but if it is determined in step (2) that the contents of both registers in either calculation circuit match, the lower value of the sign polynomial is Shift the next term to the higher-order term side, input the next term to the lower-order term side, and cycle through the registers for the generator polynomial until the contents of both registers on the high-order term side match again. Since it is repeated, the number of register cycles can be reduced for each digit, and the calculation operation can be performed at high speed as a whole.

FIG. 3 is a circuit diagram showing another embodiment of the syndrome calculation circuit, and the difference from the above embodiment is: ■ The contents of the low-order term side registers (katana (8), (9)) to the calculation circuit, ! 1
AND opened by IJIII signal (see Figure 4G)
Gate (59) (6G) (61) and OR gate (62) (63) (64), r Total II Circuit B 17) The point where the voltage is applied to OR gate (13H14) (15), ■ Register (7) on the low-order term side of calculation circuit B
) (8) (The contents of 91 are converted into AND gates (65) (6B) (6
7), and OR gates (13) (14) (15) of calculation circuit A via OR gates (68) (69) (7G)
The point where it is applied to, ■ XOR gate (4
3) The output signals from (44) and (45) are connected to an AND gate (
71) and the XOR gate (43) of calculation circuit B (
44) AND gate (12) output signal from (45)
The calculation circuit A , B's upper low-order term side register (11
(2) The only difference is that the content of (3) is selectively output as a syndrome by the output control unit (15).

FIG. 4 is a timing chart for calculating the remainder of f(x)/(x+α3) as syndrome S2 for the sign polynomial % expression % (which indicates that α 0α 00α5α3 is received as the sign), respectively. , and shows the data flow.

In the figure, A and A'' are AND gates (40), (41), (42), and (46) on the upper stage of calculation circuits A and B, respectively.
)(47) (48) are addition signals that control the opening/closing state, and B and B" are the A N D '7"-1)(2](31001(11 )
(12) (7) flf[[t, 1Jtll shift signal, and C1C' are AND gates (19) (20) (21) (28) on the lower side of calculation circuits A and B, respectively.
(29) is a load signal that controls the opening/closing state of (30), and D and D= are respectively i! AND gates (49) (50) (51) (53) on the lower stage of 1 arithmetic circuits A and B
(54) This is a cyclic signal that controls the opening/closing state of (55), and is E.

E' is the upper register of calculation circuits A and B, respectively (
7) (8) (9) (16) (17) (18)
F and F' are clock signals applied to the lower registers (25) and (26) of calculation circuits A and B, respectively.
(27) (34H35) This is the clock signal applied to (36).

Therefore, when the clock signal is input, if the addition signal is high level, an addition operation is performed, if the shift signal is high level, a shift operation is performed, and if the load signal is high level, the generator polynomial input operation is performed. If the cyclic signal is at a high level, the registers in the lower stage are cyclically operated, and if the control signal is at a high level, the low-order term side in the upper stage of the calculation circuit corresponding to the control signal at the high level is It is possible to perform an operation of inputting the contents of the register to the higher-order term side of the other calculation circuit.

As is clear from this drawing, the registers of each term in the lower row are cycled until the contents of the registers on the higher-order term side in either calculation circuit are equal, and the contents of both registers on the higher-order term side in any calculation circuit are When they match, the contents of the lower register are added to the contents of the upper register in both calculation circuits, and then the contents of the registers and stars on the lower order term side of the upper stage are shifted to the higher order term side, and the code i term is The next term of 8 is input to the register on the low-order side, and the above-mentioned cyclic and addition operations are repeated again, and finally, the register on the low-order side of the upper stage of the calculation circuit where a match was detected earlier is input. By outputting the contents of , the calculation result of syndrome S2 can be obtained. Incidentally, the calculation operation of the syndrome in the other calculation circuit is stopped at this point.

Furthermore, if the content of the register on the higher-order term side for the code polynomial is 0, a shift operation is performed until non-zero content is input.

The remaining syndromes can be obtained similarly and quickly.

Therefore, when the decoder (73) detects that the contents of the registers on the higher-order term side of either calculation circuit match, the corresponding AND gate is opened by one control signal and the shift signal, and the matched side is opened. The contents of the register on the low-order side of the calculation circuit are shifted to the register on the high-order side of the other calculation circuit and the register on the high-order side of the matching calculation circuit, and the contents of the register on the low-order side of both calculation circuits are shifted. When the next digit of the code polynomial is input to , the contents of the register for the generator polynomial can be cycled until the contents of the register on the higher-order term side match.

That is, for any digit, the number of times the register for the generator polynomial is cycled is never more than four times, and the syndrome can be calculated at a higher speed as a whole.

<Effects of the Invention> As described above, the present invention has the unique feature that syndrome calculation can be performed easily and at high speed by reducing the number of shifts using a circuit composed of hardware such as registers and adder circuits. be effective.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram showing one embodiment of the syndrome calculation device, Fig. 2 is a flowchart, Fig. 3 is an electric circuit diagram showing another embodiment of the syndrome calculation device, Fig. 4 is a time chart, and Fig. 5 The figure is a block diagram showing a decoding device. (7) (8) (8) (16) (17) (18
)...Register for code polynomial, 001 (11)(
12)...AND gate forming the shift Do path,
(25) (26) (27) (34) (35) (36)
...Register for generator polynomial, (37) (38H39) (43) (44) (45)...
・XOR gate that constitutes the adder circuit,

Claims (1)

[Claims] 1. By inputting the code polynomial in order from the high-order term side and shifting it from the low-order term side, a register for the code polynomial that stores two terms and a generator polynomial are input in order from the high-order term side. A match detection circuit detects a match between the input cyclic register, the contents of the high-order term side of the code polynomial register, and the contents of the high-order term side of the cyclic register, and when the match detection circuit detects a match between the contents, Two sets of calculation circuits each having an adder circuit that adds the contents of both registers on the high-order term side and the contents of both registers on the low-order term side are arranged in parallel, and the circulation direction of one set of cyclic registers is controlled by the other. A syndrome calculation device characterized in that the cyclic direction of the cyclic register is set opposite to the cyclic direction of the cyclic register. 2. Of the registers for the code polynomials of the two sets of calculation circuits, shift the contents of the registers on the low-order term side of the calculation circuit on which a match has been detected to the registers on the high-order term side for the sign polynomials of both calculation circuits. A syndrome calculation device according to claim 1.