JPS5929016B2 - random error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a random error correction device for correcting random errors occurring in a digital transmission path or the like.

Error correction devices that automatically correct errors that occur in digital information are rapidly being put into practical use as a technology indispensable for improving reliability in the fields of electronic computers and communication equipment as LSI technology advances in recent years. It is being done. The present invention relates to the above-mentioned error correction device, and particularly relates to a device for correcting random errors that are discrete errors, and provides a device that can efficiently suppress error propagation with a small circuit scale. It is something to do.

The error-correcting code is composed of information digits and redundancy digits (parity check digits) that are related to the information digits according to a certain rule.

A code in which parity check digits are related only to information digits within one block is called a block code. On the other hand, a code in which a check digit is not limited to information in one block but is associated with information digits in many blocks is called a convolutional code. The present invention is a random error correction device using the above convolutional code, and the present invention will be explained in detail below.

In explaining the present invention, the basic concept of convolutional codes will be explained.

First, the convolutional code satisfies a set of parity check equations.

It is defined as a set of binary sequences of and 1. Here, it is assumed that the parity check matrix has the following form. However, in the above matrix, all elements other than the shaded areas are 0.

It is assumed that BO is a matrix with b columns and semi-infinite rows, and has only a finite number of rows with non-zero elements, and the first m rows are linearly independent.

Furthermore, Bi is a matrix with the same dimensions as BO. Assume that the row of is shifted down by i row. That is, the first i row is O, and the (1+j)th row of Bi is B. (j=1, 2,...). In this way, the parity check matrix H for i=m is H=[BOBmB2m・
...] (m is an integer).

Now, if the code word is X (semi-infinite column vector), then X is
HX=0 (2) is satisfied.

Assuming that the code word Since the equation (parity check equation) is constant and the first m rows of H are linearly independent, b - m digits can be arbitrarily selected from the first b digits of X, and the remaining m digits can be determined by this parity check. Obtained by solving the equation. Thus once Xl,...,Xb is the first m
If it is taken to satisfy the following equations, m of the following H
The rows further contain m equations for unknown Xb+1,...
, Continue this procedure for each block with b elements.
At this time, the b−m elements of each block are arbitrarily selected,
The remaining m elements are determined by the parity check equation. In this way, there are m check elements for all b elements of the code X, and the redundancy is m/b. For example, B.

If we set , and m = 1, then H becomes ＼ ● ● ′.

When the information sequence to be encoded is 110100..., the first parity check equation becomes X1+X2=o,
Here, if X1)X3×59l9X2k+1 is used as the information bit,
1 is obtained, and the second equation becomes 1+X3+X4=0. By continuing this process, the coded result is 1
11001110100... The received code is then decoded by a syndrome check computed in a conventional manner for parity check codes.

If E is a vector of an error pattern (a semi-infinite column vector with a non-zero element at the location of an error) and Y=X+E is a received code, the syndrome S is as follows.

In this way, S is the sum of the columns of H (M
Od2) is a semi-infinite column vector.

It is also assumed that b digits of the received code are decoded simultaneously. By the way, when decoding the b digit of a given block, it is not necessary to look at all the syndromes, but only the syndromes affected by that block. Let N' be the syndrome affected by one program, and let N be the minimum number that is equal to or greater than m and is divisible by m. Then, consider the errors that occur in one program. In this case, only a matrix created from the first N rows (N/m) b columns of H is involved, and this is called a reduced parity check matrix HN. Note that the above Ma has a non-zero element.

is equal to the value of the row number of the last row of , and N≧ma.
Furthermore, B and T are defined as follows. B:B
Row B. NXb row which is the first N row of 1i) T:N
Shift the original column vector to m rows or less and change the first m rows to O
An NXN matrix showing a linear transformation with rows of . Using this definition, HN is expressed by B and T as follows.

The basic concept of convolutional codes has been described above.

Next, the present invention constructed using the above-mentioned error correcting convolutional code will be explained.

In the present invention, ~′ is used as the basic parity check matrix. A matrix G expressed by is used.

FIG. 1 shows a transmitting side encoder when using the basic parity check matrix expressed by the above equation (6) as the basic parity check matrix.

In this figure, 1 is a serial-to-parallel converter, 2 is a parallel-to-serial converter, 3 is a shift register, and 4 is a modulo-binary adder. The information signal to be transmitted is input to the serial-to-parallel converter, encoded by the shift register 3 and modulo binary adder 4, and further transmitted by the serial-to-parallel converter 2 as a serial signal. The encoding procedure for the encoder in this figure is as follows.

First, a 3-bit information signal input in series is converted into parallel signals in a serial-to-parallel converter. Then, modulo binary addition is performed between the signal obtained by shifting the first bit by one bit by the shift register 3 and the signal of the second bit.
Modulo binary addition is performed between the signal obtained by further shifting the result of the base addition by one bit and the third bit. Furthermore, the signal obtained by shifting this modulo binary addition output by 1 bit and the parity check bit currently being transmitted are modulo binary added, and the result is further shifted by 1 bit and the 1st, 2nd, and 3rd bits. The result of modulo binary addition is output as parity check bits. Therefore, as the encoded serial output, one block in which parity check bits are added to the first to third bits is output as a 4-bit signal. Although the above-mentioned encoding circuit corresponds to the basic parity check matrix shown by G4 in equation (7), it can be configured similarly for general Gb.

FIG. 2 shows a conventional example of a random code decoder for decoding the above-mentioned encoded signal.

In this figure, 21 is a series-to-parallel converter, 22 is a parallel-to-serial converter, and the part A surrounded by the dotted line is a syndrome planning circuit.
B is a syndrome register, and C is an adder for error correction.

In the syndrome calculation circuit A, 23-1 to 23-4
is a shift register which registers one bit of signal in each unit indicated by one section.

24 indicates a modulo binary adder.

Further, in the syndrome register B, 24 is a modulo binary adder, 26-1 to 26-4 are shift registers, 27 is an AND circuit, and 24-1 to 24 in the error correction circuit C are
4-3 is a modulo binary adder.

Here, in order to explain the error correction function of the transmitted signal, (0011), (0100)
, (0111), (1000), (1010), (11
An example will be explained in which signals of 01), (1111), and (0011) are input.

Although the above signals are actually input in series, they are shown converted into parallel signals of 4 bits each by the serial/parallel converter 21. Now, suppose that an error occurs in the third bit of the first four bits (0011) of the above signal in the transmission path, resulting in the signal becoming (00♂1).

*mark indicates an error signal.

The input signal is registered in the shift register in syndrome calculation circuit A, subjected to modulo binary calculation in the modulo binary addition circuit, inputted to syndrome register B, and further subjected to modulo binary addition calculation and AND calculation.

Here, the result of calculating the output of the serial/parallel converter 21, that is, the signal at B in FIG.
~23-4, the process of registering in the shift registers 26-1 to 26-4 is shown below. (Series-parallel converter) j Now, in the next step of 5) above, the error signal of the shift register 23-3 is input to the modulo binary adder 24-3.

Furthermore, since both the signal of the shift register 26-4 and the signal of the shift register 26-2 are 1, the AND circuit 27
Is the output of -2 equal to 1? Rokusei ≦ 2sai / = ↓, which becomes 1 and is output.

Therefore, the polarity of the signal which erroneously became O is reversed and returns to its original state, meaning that the error has been corrected. Now that the error has been corrected, the effect of that error on the syndrome, i.e., shift registers 26-2 and 26-4.
Since the output of the AND circuit 27-2 is fed back to the modulo-binary adder in order to eliminate the signal 1 in . However, the conventional decoder described above has the disadvantage that if errors occur continuously in the transmission path, the error correction capability is exceeded, and the errors propagate as they are.

An example of such a case will be described below. Now, the series-to-parallel converter 21 is (0011), (0100), (011
1), (1000), (1010), (1101), (
1111), (0011), (0101), (0110
), (1000), and (1100) are input.

Then, the third bit of the four bits in the first block is incorrect (00 customer 1), the second bit of the four bits in the third block is incorrect (0♂11), and the eighth bit is incorrect (0♂11). Assuming that the third bit of the 4 bits in the program is incorrectly set to (00 customer 1), shift registers 23-1 to 23-4, shift registers 26-1 to 26-1, etc.
The signals registered in 26-4 are shown below.

At the stage of knob J0), shift register 2 indicated by the arrow
The signal 1 registered in the two registers 6-4 and 26-2 is combined and the signal 1 of the shift register 23-3 is
This error propagation is suppressed in the present invention, in which the last O of 0 is considered to be erroneous, and it is erroneously corrected to become 1.

After this erroneous correction, the contents of the register 26-226-4 are set to O by the feedback of the output of the AND circuit 27-2 (the chamber indicated by 10 is input to the syndrome register at the next point in time, and this is changed again). This may lead to other erroneous corrections (error propagation).In other words, in the configuration of the present application, the final stage output of syndrome register B shown in Figure 2 is subjected to appropriate conversion and then returned to the first stage input of the syndrome register. This is to suppress this error propagation.An embodiment of the present invention is shown in FIG.

In this figure, 24, 25 are modulo binary adders, 31, 32
3 is an AND circuit, 33 is a syndrome register, 34 is a flip-flop circuit, and 35 is a delay line, and the portion B surrounded by the dotted line has the same structure as the portion B surrounded by the dotted line in FIG. In the flip-flop circuit 34, S is a set input terminal, R is a set input terminal, and Q and Q are output terminals, respectively. @, 0, 7 in this figure correspond to @, @, 7 in FIG. By adding the configuration shown in this figure to the syndrome register, the contents registered in the shift registers (26-1 to 26-4) after the step 6) described above change as described below. do.

First, in step 5).

In the next step, the output 1 of the shift register 26-4 sets the flip-flop 34, and the syndrome 1 from step 6) is now prevented from being input to the syndrome register 26.

Therefore, the states of the shift registers 26-1 to 26-4 at this time are as follows. Therefore, the influence on the uncorrectable error syndrome is removed, and the propagation of errors can be suppressed.

The state of each shift register in the next stage is shown below. "l" becomes one, and the pattern in the syndrome register (0101
), it can be seen that the error signal 0 is corrected to 1 in the modulo binary adder 24-3.

Therefore, it can be seen that the error correction function after the error propagation suppression performed in 6) is also functioning normally.

In FIG. 3, the reset signal input to the flip-flop 34 must have a certain delay time with respect to the set signal.

For this purpose, a delay line 35 and an AND circuit 32 are used, and a signal that satisfies the AND condition of the syndrome calculation circuit and a signal obtained by delaying the output of the flip-flop circuit by a certain period of time is used as a reset signal. As described above, according to the present invention, error propagation due to consecutive random errors can be suppressed with a simple configuration.

[Brief explanation of drawings]

FIG. 1 shows a transmitting encoder of a random error correction apparatus, FIG. 2 shows a receiving decoder, and FIG. 3 shows an embodiment of an additional circuit according to the present invention. In Fig. 2, 21 is a serial-to-parallel converter, 22 is a parallel-to-serial converter, A is a syndrome calculation circuit, B is a syndrome register, and C is an adder for error correction. , 31 and 32 are AND circuits, 33 is a syndrome register, 34 is a flip-flop circuit, and 35 is a delay line.

Claims (1)

[Claims] 1. A syndrome calculation circuit that receives a transmitted error-correcting convolutional code and calculates a syndrome from the error-correction convolutional code sequence, which is connected to the syndrome calculation circuit and generates a required syndrome sequence. In a random error correction device that has a decoder including a syndrome register and corrects random errors occurring in a transmitted signal according to a predetermined basic parity check matrix, "1" of a syndrome sequence exceeding a predetermined length is used. is detected,
A random error correction device characterized in that the "1" signal is fed back to the first stage of the syndrome register as a final stage output of the syndrome register. 2. The output of the syndrome register is input to the set input terminal of the flip-flop circuit, and the output signal of the syndrome register is input through an AND circuit that inputs the output signal when the set signal of the flip-flop circuit is input and the output signal of the syndrome calculation circuit. 2. The random error correction device according to claim 1, wherein the random error correction device is fed back to the initial stage input. 3. Claims characterized in that a signal that satisfies the AND condition of the output signal of the syndrome calculation circuit and the signal obtained by delaying the output of the flip-flop circuit by a certain period of time is used as the reset input signal of the flip-flop circuit. Random error correction device of Section 2.