JPS61277230A - Error detecting and correcting code generating system - Google Patents

Abstract

PURPOSE:To detect and correct errors with a small scale circuit by providing a fundamental generating pattern operating circuit, which generates a prescribed code word from data divided by a data dividing circuit, and an accumulating circuit which accumulates operated code words. CONSTITUTION:128-bit data is divided to 4 blocks by 32 bits and 8-bit generated ECC is divided to 4 blocks by 2 bits in the circuit, and 2-bit ECC is added to 32-bit data when viewed from the external, and for example, a required area of a memory for ECC is reduced with respect to handling of ECC in an external connecting device. The constitution of the circuit is made small-scale and simple because the number of bits of fundamental data is 32. In the ECC generating method, 128-bit input block units are operated regularly in 8-bit units to simplify very much the constitution of a fundamental part as an ECC generating means. Thus, errors are detected and corrected with the small-scale circuit constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an error detection and correction code generation method that adds a several-bit code to a data string and makes it possible to detect and correct errors occurring in the data string. It is related to the method.

[Summary of Disclosure] This specification and drawings describe an error detection and correction code generation method that detects and corrects errors occurring in a data string by adding a linear code of several bits, such as a Hamming code, to a data string. The code generation matrix is divided into a plurality of matrix blocks, the input data is divided into a plurality of blocks having the same length as the column direction of the matrix block, and when the linear code is generated, the matrix block is divided for each block. This invention discloses a technique for reducing the redundancy of codes for error correction and reducing the circuit size by generating code words and reconstructing the linear code from a combination of the code words.

[Prior Art] Linear codes are well-known as codes for correcting data errors that occur randomly, and error check codes (hereinafter referred to as , ECC)
As an example, it is known that the number of bits is the minimum (n + 1) bits for data with a length of 2n bits in order to correct a 1-bit error that occurs within the data length. When handling 32-bit data, it is necessary to add 6-bit ECC to correct a 1-bit error that occurs in the data. In the conventional error detection and correction code generation system having such a function, for four consecutively input 32-bit data, that is, 128-bit data, 6 bits each are generated four times for a total of 24 bits. ECC is added, and the information rate representing the transmission rate is 128/(128+24)=0.84. On the other hand, if ECC is directly generated from 128 (=27) bits of data, the code length is 8 bits and the information rate is 128/(128+8)=0.94, so ECC is generated every 32 bits. You can see that the efficiency has deteriorated considerably when it is generated. However, it is possible to generate 8-bit ECC directly from 128-bit data and use it to generate 1
A circuit that corrects bit errors is much more complicated than a circuit that corrects errors using 6-bit ECC for 32-bit data.

Furthermore, when the Reed-Solomon method is used as the means for generating ECC, the calculation for generation is complex and becomes more complicated as the number of bits of data to be handled increases.

[Problems to be solved by the invention] In this way, with conventional technology, if you try to reduce the circuit scale, redundancy increases and efficiency decreases, and if you try to reduce redundancy, the circuit scale increases. , redundancy and circuit scale were inversely proportional to each other.The present invention was made in view of the above-mentioned drawbacks of the prior art, and its purpose is to reduce redundancy and create an error detection and correction code with a small circuit scale. The challenge is to provide a generation method.

[Means for Solving the Problems] In order to achieve the above-mentioned problems, the error detection and correction code generation system of the embodiment shown in, for example, No. 113 uses, for example, a Hamming code as a linear code, and input data is Based on the data division circuit lOO that divides the Hamming code into lengths, and the basic generation pattern obtained by dividing the Hamming code generation matrix into multiple matrix blocks, the data division circuit 1
A basic generation pattern calculation circuit 101 that generates a predetermined code word 102 from data divided by 00, and a code word 10 calculated by the basic generation pattern calculation circuit 101.
It has an accumulation circuit 103 that accumulates 2.

[Operation] In the above configuration, the accumulation circuit 103 accumulates the code words 102 as many times as the divided number, and generates the error detection and correction code 104 for the entire input data.

[Embodiment J] Hereinafter, a circuit in which the error detection and correction code generation system according to the embodiment of the present invention is applied to error detection and correction of 128-bit data will be explained based on the accompanying drawings.

The outline of the example circuit is as follows. In order to finally add 8-bit ECC to 128-bit input data, the circuit is configured to operate in units of 32 bits to make the circuit common and smaller. That is, within the circuit, 128-bit data is divided into four blocks each of 32 bits, and the generated 8-bit ECC is divided into four blocks of 2 bits each. When viewed from the outside, 32-bit data is divided into only 2-bit blocks. Since ECC is added, handling of the ECC of the externally connected device, for example, the required memory area can be reduced. Furthermore, since the basic number of bits of data is 32, the circuit configuration can be realized with a small scale and simple configuration. Roughly speaking, ECC is generated in block units of 128-bit input and 8
Enables execution of regular operations on a bit-by-bit basis, and EC
The basic part of the C generation means can be done with a very simple configuration.

Figures 2 (a) to (d) show 8-bit ECCC Hamming code for 128-bit input data.]
This is a matrix pattern for generating . °X” in the matrix is exclusive OR (hereinafter referred to as Ex-OR)
Ex-O of the data bit corresponding to "x" in the row direction in the input 128-bit data.
For example, in Figure 2 (
In the example of IL), the input data bits are Do ”'D31
Then, ECCo-Dz■D3■D5■D7ΦD9■D
11■013■015Φ017■DI9■D21■D2
3■D25■027■D29ΦD31 (Φ represents exclusive OR). Alternatively, the ECC bits may be generated so that the number "l" of data components at the position corresponding to the X mark and the ECC bit corresponding to that row are odd numbers.

As a whole, 32 8x128 matrix patterns are used.
Figures 2(a) to (d) show the individual large blocks when divided into four 8x32 large blocks each containing 32 bits. Furthermore, each large block of 32 bits is divided into four equal parts (indicated by dotted lines). display)
When we divide it into 8x8 small blocks, we find the following.

First, the ゛X'' pattern corresponding to Co NC4 (lower 5 pits of ECC) is common between large blocks and the same small blocks, and secondly, the upper 3 pits of ECC)
C5 to C7 are composed of a pattern unique to that small block. It is assumed that the numbers are ranked in ascending order starting from 0.

In other words, corresponding to the lower 3 bits of the small block...
The pattern 3×8 is the same in all small blocks. Therefore, the minimum required basic conversion pattern for x'' to obtain ECC is the Mad9x pattern as shown in Figure 3.
By combining the conversion patterns shown in the X8 matrix, 5 bits of ECC basic utility can be obtained.

The above division of the generation matrix can be said to be correct from the following points. A combination (law) holds true for the Ex-OR operation. Therefore, the ECC 8 bits generated from 128 bits/data and the second ECC for 32 bits/data.
It is equal to the 8-bit ECC generated by generating 8 bits of ECC for each large block using the generation matrix shown in Figures (a) to (d), and performing Ex-OR of the 8 bits of ECC generated for each large block. . This also applies to small blocks of 8 bits/data. Therefore, even if Ex-OR@win is performed for 8 bits/data, ECC, which is the Ex-OR output for 128 bits/data, is finally obtained.

Further, for 128-bit data, the characteristics of the embodiment are well recognized, and in view of the circuit scale, an appropriate unit data length is 32 bits. Therefore, in the following embodiment, 32 bits are used as the basic unit of processing.

Based on the above, the detailed configuration of the ECC generation circuit (hereinafter referred to as ECCG) is shown in Figure 4 (a).The input to ECCGIO in Figure 4 (IL) is 32-bit data, large block A 2-bit signal indicating numbers 1 to 4 and a strobe signal which is an output strobe are input, and the output is an ECC 8-bit signal.

32-bit data (DoxD3x) is R every 8 bits.
OM1 to OM4 (for example, in the example of Fig. 2(a), the data of small block 1 is stored in ROMI, the data of small block 2 is stored in ROM2, the data of small block 3 is stored in ROM3, and the data of small block 4 is stored in ROMI). (input into the ROM 4) and output as a 5-bit code for a total of 20 bits.

All four ROMs 1 to 4 for this 8-bit data input are configured with a pattern that performs Ex-OR as shown in Figure 3 above, and are general-purpose ROMs with an 8-bit address input. It is shown in FIG. 4(b).

First, the outputs 0uto "0ut2 (Fig. 4) of ROM1-4 will be explained. ROM1-4 input 8-bit data to address inputs AO-A7, and the output, for example, Outo, is the basic conversion pattern block shown in Fig. 3. Ex-OR is performed in advance on the basis of turn "0" and the stored value is output. For example, Do-D7=” in ROMI
When “01100101” is input, the output Out is D1■D3■D5■D7=” according to pattern O in Figure 3.
l” (■ represents exclusive OR).Similarly, Out
l is Outz = D 2 according to pattern 1 in Figure 3.
■D3■D6■p7=“O”, 0ut2=D4ΦD
5■D8■D7="O", 4 of such ROM
Do each one do ND? , Da ~ Dz 5, D
Input z 6~D23, D24~031, 0uto
, 0utz, 0ut2 are applied four times. Ex-OR
Circuit 5 inputs these 12 bits and outputs each ROM's Out.
Ex-OR is performed for each time, and a 3-bit exclusive OR is output. The exclusive OR output of this Ex-OR circuit 5 is the lower 3 bits of the 8 bits of ECC of 32 bits/data.

The Ex-OR circuit 5 is connected to the ROM1 as shown in FIG. 4(b)(7).
0ut for 8 bits/data from to ROM4
o Take Te Ex-OR, take Ex-OR of 0utz for 8 bits/data from ROM1 to 4OM4, take Ex-OR of Out3 for 17) 8 bits/data from ROM1-ROM4t, and calculate these 3 The two Ex-OR outputs are respectively output as data. That is, E
The 3 bits of the x-OR circuit 5 are large blocks 3
ECC bits 0 to 2 for 2 bits/data.

Note that the Ex-OR circuit 5 may be constructed from logic gates, but the circuit construction will be simpler if it is constructed from a ROM.

The remaining upper 5 bits 3 to 7 of the 8 ECC bits of 32 bits/' data are R as shown in 4th fgJ(a).
Out of each output of OM1-4, the necessary 5 bits and a 2-bit signal representing the block number are obtained by encoder 6. This will be explained in detail below.

As mentioned above, when we compare and examine each 8×32 large block from 1 to 4, we find that the lower order of small block l (θ~4)
The 5-bit 5x8 matrix pattern is all the same between large blocks. The generation pattern for determining the upper three bits (5 to 7) of the 32-bit/data ECC is a combination of patterns 3 and 4 in FIG. Therefore, in order to obtain the upper 3 bits of the 8 bits of ECC of 32 bits/data, encoder ROM 6 is configured with 2 bits of information to be output from each ROM 1 to 4 and 2 bits of information representing the block number, a total of 10 bits. , internally E
In principle, if you perform an x-OR operation, E of 32 bits/data
The upper 5 bits of CC8 bits are obtained. Figure 4(a)
In this circuit, the input from ROMs 1 to 4 to encoder ROM 6 is 5 bits for the following reason. ECC8
16 for each bit to get the top 5 bits
Since there are 5x16=80 corresponding small blocks,
Since 27=12'8>80, a total of 7 bits of input, that is, 5 bits excluding 2 bits of the block number, are input to R.
It is sufficient to input from OM1 to OM4.

The 8-bit ECC for each 32 bits/data thus generated is Ex-ORed for each corresponding bit in the Ex-OR circuit 7 together with the 8-bit ECC generated for the previous 32 bits/data. , are latched in latch 8 for each large block. If the above operation is repeated from large block 1 to large block 4, E for 128 bits/data
CC8 bits are obtained. As mentioned above, the gate circuit 9 is a feedback circuit for Ex-ORing the 8 ECC bits every 32 bits and accumulating them in the latch 8. each time) has one movement that clears latch 8. In other words, the ECC for 32 bits/data of block number 4 is
Ex-ORM calculation is performed in Ex-OR circuit 7, and latch 8
An 8-bit ECC for 128-bit data is obtained only after the data is latched. In this way, 1
Even for long data of 28 bits, ECC can be obtained with minimum redundancy without increasing the circuit scale.

The EC:CG 10 shown above is common to the following ECC addition circuit (FIG. 5) and error detection and correction circuit (FIG. 6).

Next, the ECC addition circuit will be explained using FIG. 5.

External input data and an input enable signal indicating that this data is valid are input to the ECC addition circuit via an external data bus.

A latch 11 has the function of converting input data into data in units of 32 bits and holding the previous 32 bits of data until the next data of 32 bits in total is input from the external data bus. Reference numeral 12 is a device that sends out an enable signal for the input data to 32-bit block data and a 2-bit signal representing block numbers 1 to 4 using this enable signal, and is composed of F/F etc. The timing circuit used is amazing. 10 is the aforementioned ECC generation circuit (ECC
CG). Since it is necessary to sequentially send 32-bit data from latch 11 until the ECC for 128-bit data is sent from 10, it is necessary to delay each 32-bit/block data by 4 blocks in latch 13. be. 14 is a latch that holds the 8-bit ECC obtained by ECCG 10 for one cycle (time to process 4 blocks of data). 15 divides the 8-bit ECC into four parts of 2 bits each and distributes 2 bits to each 32 bits/block, and can be configured with a data selector or the like using the 2-bit signal represented by the block number. 16 is the output latch, 32
The bit data and the 2-bit ECC obtained in step 15 are sent to the outside together, for example, to a storage device such as a memory. In other words, 128 bits + 8 bits ECC, total 13
Send 6 bits (32 bits + 2 bits) x 4 times.

Of course, the 8 ECC bits may not be divided into 2 bits at a time, but a total of 136 bits may be used all at once.

Next, the error detection and correction circuit will be explained using the $6 diagram.The error detection and correction code generation method of this embodiment calculates the so-called error syndrome from the input data, and uses the obtained error syndrome and ECCGIO to generate the error detection and correction code. E
The position of the error bit is detected and corrected from the CC8 bits.

For example, the error detection and correction circuit is connected to a
It is assumed that 2-bit data, 2-bit ECC1, and an enable signal for these input data are input. 20 is an input latch. 21 is a timing generation circuit that generates a 2-bit signal representing a block number from an enable signal, and is composed of an F/F and the like. 10 is the aforementioned ECCG. Reference numeral 22 denotes a latch that restores and reproduces the 2-bit ECC input for each block into 8-bit ECC for four blocks at a time. 24 is a syndrome generation circuit that generates a syndrome from the ECC generated from the input data in the ECCGIO and the ECC generated by the ECC adding circuit shown in FIG. Consists of an OR circuit.

5 is the address (0 to 127) of the bit where the error occurred from the syndrome obtained by the syndrome generation circuit 24.
This is a syndrome data generation circuit that obtains the following information: Of the 8 bits of data obtained by the syndrome data generation circuit 25, the lower 7 bits represent an error bit address in binary representation (0 to 127), and the most significant bit represents the presence or absence of an error. This address data is latched in latch 26 for l cycles. If the second and third bits from the top of this address data represent the block number, the decoder 27 compares it with the block number signal generated by the timing generation circuit 21 and determines the address where the error occurred. If it matches the block number to which it belongs and it is determined that there is an error by looking at the error presence/absence signal from the latch 26, the correction instruction circuit 28 uses this error information and error address information to select a predetermined value in the Ex-OR circuit 29. 1 bit of the 32-bit data at the predetermined address of the block number is inverted. This correction instruction circuit 28 outputs "0" for each bit when there is no error or when the block number of the data to be output and the address of the bit where the error occurs are different from the block number to which it belongs even if it is recognized that there is an error. will be sent and no corrections will be made.

The 32-bit data corrected by the Ex-OR circuit 29 is converted by the converter 30 into the number of bits of the external data bus. 31 is an output latch. In this way, since the error syndrome is generated in the small-scale ECCG IO, the error detection and correction circuit in FIG. 6 is also small-scale.
Even with such a small-scale circuit, a 1-bit error in 128 bits/data can be detected and corrected.

In the above embodiment, 8 bits of E are input to 128 bits of input data.
Error correction was performed by adding CC, but another example of how this data division method can be applied successfully is when performing 1-bit error correction and 2-bit error detection within a data length of 64 bits. Since the number of additional bits is 8 bits, 4 blocks of data and ECC require 1 external bit.
It can be handled as 6-bit data + 2-bit ECC.

Furthermore, although the data length handled in the above embodiment is as large as 128 bits, it is expressed as a 32-bit data length inside the circuit and in external connection media such as memory and transmission lines, making it very easy to handle in terms of processing. . E for further error correction
CC is 2 bits compared to the apparently 32 bit data, and the ratio [information rate] of ECC data is 1/17.
Therefore, the cost for ECC is small.

In addition, since the ECC generation method can be executed by calculating regular patterns in block units and 8-bit units, there is no need for complex gate circuits, and as in this example, two types of ROM patterns (Fig. 3) are used. Patterns 1 and 3) will suffice.

[Effects of the Invention] As explained above, according to the present invention, error detection and correction can be performed with a small-scale circuit configuration without increasing redundancy.

[Brief explanation of the drawing]

Figure 1 is a basic configuration diagram of an embodiment according to the present invention, Figure 2 (&
) to (d) are 8-bit EC from 128-bit data.
A matrix pattern diagram for bit-wise arithmetic operation to obtain C. Figure 3 is a diagram explaining a bit-wise arithmetic operation pattern to obtain a 5-bit basic code from 8-bit data. C) is a circuit diagram of the ECC generation circuit and internal components of the embodiment, FIG. 5 is a diagram of the ECC addition circuit of the embodiment, and FIG. 6 is an error detection and correction circuit diagram of the embodiment. In the figure, 1, 2, 3.4・ROM, 5, 7.29...E
x-OR circuit, 6... encoder ROM, 8.11.
13, 14, 20, 22, 23, 26.31...Latch, 9...Gate circuit, lO...ECCG, 12
．． 21... Timing generation circuit, 15... Data selector, 16... Output latch, 24... Syndrome generation circuit, 25... Syndrome data generation circuit,
27... Decoder, 28... Correction instruction circuit, 30...
...It is a converter. Figure 4 (b) Figure 4 (C)

Claims (3)

[Claims] (1) In an error detection and correction method that performs error detection and correction of input data by adding a linear code to input data of a predetermined bit length, the generation matrix of the linear code is divided into a plurality of matrix blocks, and the input data is When the matrix block is divided into a plurality of blocks having the same length in the column direction and the linear code is generated, a code word is generated from the matrix block for each block, and the linear code is generated from the combination of the code words. An error detection and correction code generation method characterized by reconstructing. (2) When dividing a generation matrix into matrix blocks, arrange the matrix blocks of the divided words so that they have at least a common basic generation pattern before dividing, and when generating code words, The error detection and correction code generation method according to claim 1, characterized in that a code word is generated based on a generation pattern. (3) The error detection and correction code generation system according to claim 1 or 2, wherein the linear code is a Hamming code.