JPS5825295B2 - Error system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an error correction control system, particularly a data transfer system that automatically corrects random sound bit errors and detects (t+1) bit errors by adding an error correction code. , one-on-one for the syndrome
A memory for storing error bit position information indicated by the syndrome is provided at an address location corresponding to the syndrome.
The present invention relates to an error correction control system which performs the above error correction and detection by reading out the contents of the memory.

Conventionally, in data transfer systems such as the main memory of a data processing system, in order to improve the reliability of operation, especially as the storage capacity of the main memory increases,
A so-called SEC/DED Hamming code, which performs bit error automatic correction/two-bit error detection, is used.

However, as the degree of integration of IC memory devices increases,
Automatic correction of t or more bit errors/(t+1)
It has become necessary to employ error correction codes that provide bit error detection.

The so-called BCH code is well known as this type of multi-bit error correction code, and the details of this code are as follows.
Including conventional decoding methods, for example, ``Code Logic'' by Miyayo et al.
(Shokodo) etc.

However, in the case of this known method, the use of a shift register is considered in determining the error bit position from the obtained syndrome, so the process of actually determining the error bit position is difficult. It becomes huge.

The present invention aims to solve the above points,
The error bit position detection is performed by accessing a memory such as a read-only memory, thereby simplifying the configuration for correction processing based on the output read from the memory, and further reducing the storage capacity of the memory. The purpose of the present invention is to provide an error correction control system that does the following.

Therefore, the error correction control system of the present invention corrects t random bit errors (t is an integer of 2 or more) and adds an error correction code to detect (t+1) bit errors to data, and utilizes the data. In a data transfer system that automatically corrects t bit errors and detects (t-1-1) bit errors based on the data and the error correction code added above,
Error bit position information representing the error bit position corresponding to the output of the syndrome generating means in binary representation is stored in the syndrome generating means and the address position corresponding to the output of the syndrome generating means in a one-to-l ratio.
A memory is provided to store 1M bit errors separately, and errors in the data are corrected and detected based on the contents of the memory, and correctable errors and uncorrectable errors are detected. The fact that instructions to this effect were issued in response to the outbreak was considered a sign of success.

This will be explained below with reference to the drawings.

Figures 1 to 3 show t-bit error automatic correction/(1
+1) An explanatory diagram for obtaining a check matrix for bit error detection. Fig. 4 is an explanatory diagram for explaining one embodiment of processing for obtaining a syndrome according to the present invention. Fig. 5 is an explanatory diagram for explaining an example of processing for obtaining a syndrome according to the present invention. FIG. 6, an explanatory diagram for explaining the correspondence with the stored contents, shows the configuration of an embodiment of the present invention.

As an example, consider a BCH code with a code word length of 15 bits, a number of information points = 7, and a 2-bit random error correction capability.

The generating polynomial of this code has the elements α and α3 of the Galois field GF (24) as roots.

G(x)-(x'+x-1-1) (x'+x"+
x2+x+1), and its check matrix is given by the one shown in FIG.

As shown in the above-mentioned literature, a code word having an error in the first and third digits is applied to the test matrix village, and the syndrome S1, which is calculated from the upper half of the old test matrix in FIG. If the syndrome calculated from the half is 82, it is given by the syndrome.

Since the above equation (5) is transformed, the above 2-bit error position is given by Kokichi, who obtains the solution to the polynomial.

Furthermore, if there is only one error, 52-(Sl)'' holds true, so the error bit position can be given by solving f(X)-X+8l-0-(D).

However, when determining the error bit position using the above-mentioned known method, a conventional method has been used in which a shift register is used to solve the problem, which results in a complicated processing configuration.

It is known that adding one line of parity check for all bits to the check matrix 7 shown in FIG. 1 provides the ability to detect 3-bit errors.

The test matrix river created in this way is shown in FIG.

When using the inspection module IJ shown in FIG. 2, error conditions are detected as follows.

That is, by applying the test matrix shown in FIG. 2 to the code word, the syndrome calculated from the first row of the matrix is S, the syndrome calculated from the second row is S, the syndrome calculated from the third row is S, and the syndrome calculated from the third row is S. 8 syndromes
2, the difference between them is (a) 5o-81-82-0 in the case of no error (b) 5o-81-82-0 in the case of 1-bit error (So=', 5l-82-〇1i ) 5o=1, (Sl)3-82 (c) In case of 2-bit error condition (1) So-0, (Sl)3\52 (ii) 5o=O1(Sl)3=82 (d) In the case of a 3-bit error state, there are the following relationships: 5o-1 and (Sl)3-82. These relationships are used to automatically correct errors up to 2 bits and detect 3-bit errors.

FIG. 3 shows a test in which the old check matrix αl shown in FIG. Matrix old is shown.

If the old matrix shown in FIG. 3 is used, syndrome S is obtained.

, Sl, and S2, Sl and 82 are the same as those in (a) to d) described above with reference to FIG. 2, except for syndrome S.

What does it mean that becomes logic “0” and logic “1”?
The meaning of becoming is somewhat different.

In other words, the condition that the logic is "0" means that "there is an even number of places that are the logic "1" among the nine digits that make up syndrome S," and the condition that the logic is "1" means that "syndrome S is There is an odd number of logical "1" locations among the nine constituent digits.

In the error correction control system of the present invention, the inspection matrix (2) shown in FIG. 3 can be used as is.

However, in general, code word error correction/detection involves extracting the digits at the position of the value "1" for each row in matrix H from among the digits constituting the code word, taking their parity, and calculating the syndrome bit for each row. It is carried out by Kokichi who generates.

For this reason, in the case of an old matrix in which each row has many positions with the value "l", such as the inspection matrix shown in FIG. 3, the processing speed for syndrome generation and the circuit configuration for this purpose become complicated.

Therefore, in the present invention, it is advantageous to use a test matrix as shown in FIG. 4 for water.

The old matrix shown in Figure 4 can be divided into the left half of the unit matrix and the right half of the check matrix by adding modulo 2 between each row and exchanging the rows of the matrix shown in Figure 3. This is what I did.

However, when using the Mado IJ Kusu old shown in FIG. 4,
Syndrome S according to the first line.

, the syndrome according to lines 2 to 5 is 81, line 6
Even if we assume that the syndrome from rows to rows 9 is 82 and set syndrome 8 as , the relationship given by equation (5) above is 81 and 8.
2, the conventional error bit position determination process cannot be used, and it is necessary to consider other methods.

In the case of the present invention, the test matrix shown in FIG. 3 can be used, but regardless of whether the old test matrix shown in FIG. 3 or shown in FIG. This can be done with a simple configuration using .

That is, in order to obtain the syndrome S by applying the test matrix old to the code word, the processing as shown in FIG. 4 is executed.

In Figure 4, old is the inspection matrix and W is the code.
code word W is parity P, BCH
Codes C6 to C7 and data D.

Those composed of D6 to D6 are shown in an older manner.

In the case of the present invention, a memory is prepared and error bit position information representing the error bit position indicated by the syndrome S is stored in an address position given by a certain syndrome $.

When a certain syndrome $ is given by the process shown in FIG. 4, the memory is accessed and the error bit position is determined based on the stored contents.

FIG. 5 explains the configuration of a memory that stores error bit position information used in the present invention.

That is, for example, when a code word W and a matrix H are used, what pattern the syndrome $ takes depends on which one bit in the code word W has an error, and which two bits there is an error in. It is possible to calculate in advance what pattern the syndrome $ will take depending on whether there is an error, and what pattern it will take when there is an error of 3 or more bits.

For this reason, information on which bit position an error exists in corresponding to a certain syndrome S is stored in the memory.

In the case shown in FIG. 4, when the syndrome 5BfA L/Sl is given as [0OOOOOOJ, this indicates that "0OOOOOOJ" indicating that there is no error bit is stored at the memory address r00000000J.

Also, syndrome s8 or SL is 1-oooooooot
When given by J, the memory address [ooooooo
This indicates that "1O000000" indicating that an error exists in bit C6 is stored in iJ.

Similarly, syndrome s8 to sl is 10000001
1”, the memory address roo000
"10000100" indicating that an error exists in bits C8 and C1 is stored in 011j.

Also, syndrome s8 to sl is rllllllllO
Corresponding to patterns such as J and rllllllllJ that cannot occur with an error of less than 2 bits, roooooooooJ is stored at the address in the memory to indicate that the error bit position cannot be determined.

In the case of the memory shown in FIG. 4, the syndrome S is used to reduce the storage capacity of the memory, as will be described in detail with reference to FIG.

The corresponding processing is handled separately.

Furthermore, the stored contents are divided into an A part and a B part, and when an error exists in only one bit, the bit position is expressed by four bits in the A part.

Furthermore, if there is an error in two bits, one bit position is represented by 4 bits in part A, and the other bit position is represented by B.

It is expressed using 4 bits in the bar.

The contents of both parts A and B are set to all zeros in case there is no error or in case there is an error in three or more bits.

For this reason, if we now perform the calculation as shown in Figure 4, 58 to sl in syndrome S will be as shown above < [000
If 00011j is obtained, “0OO
The address location given by OOOIIJ is accessed and the stored content "10000100" is read.

Then extract the position of the first error bit C6 according to the contents of part A in the memory contents "100OJ", and
The position of the second error bit C1 is extracted based on the part content "0100".

FIG. 6 shows the configuration of an embodiment in which, as explained in connection with FIG. 5, the free memory is accessed for the determined syndrome $, the error bit position is determined, and automatic correction/detection is performed. ing.

In the figure, 1 is a syndrome generation means, 2 is a read-only memory in which error bit position information is stored, and 3 is an address decoder, which is used for s8 to s8 in the syndrome S obtained by the syndrome generation means 1. 4 is a parity generator that decodes the contents of sl, and syndrome S
8 to Sl and S.

5 is an OR circuit that generates a logic ``0'' when any of 58 to SL in the syndrome is a logic ``0''. 6 is a NOR circuit that emits logic "1" when the contents of part A read from memory 2 are all logic "0"; 7 is a NOR circuit that outputs logic "1" when the contents of part B read from memory 2 are 8-0 and 8-1 are decoders which emit a logic "1" when all logics are "0" and decode the contents of the A part and the B part, respectively.

Further, 9 to 18 represent AND circuits, 19 to 24 OR circuits, 25 a NOR circuit, 26 a NOT circuit, and 27 to 31 exclusive OR circuits.

(1) Now, for example, input code word P.

, Co... Consider the case where only the C1 bit in D6 has an error.

In this case, the syndrome generator 1 performs the processing shown in FIG.
000000100) is obtained.

Then, s8 to sl are given as address information to the memory 2, and [0100°ooooJ is read out from the corresponding address position in the memory 2 as shown in FIG.

The content 1-otooJ of this A part is input to the decoder 8-0, and the content "0000" of the B part is input to the decoder 8-0.
1 is input.

As a result, in the decoder 8-0, the terminal "2" is set to logic "1".
”, and in the decoder 8-1, the terminal becomes “1” and “15
” all produce a logic “0”.

Since this old NOR circuit 25 emits a logic "1" as described later, one input logic rlJ of the exclusive OR circuit 29 is applied via the OR circuit 22 and the AND circuit 16.

As a result, the contents of the C1 bit in the input code word are inverted, and the outputs are P' and Co'.

...D6' as "P, Co, C1...D6
J is output.

That is, the 1-bit error is corrected and output.

(II) Next, consider the case where an error occurs only in the parity bit P in the input code word.

In this case, syndrome S.

only becomes logic "1".

As a result, the parity generator 4 becomes logic "1", the OR circuit 5 becomes logic "0", and both NOR circuits 6 and 7 become logic "1".
1”.

As a result, the AND circuit 13 outputs a logic "1", and only the parity bit P in the input code word is inverted via the OR circuit 20, the AND circuit 14, and the exclusive OR circuit 27, and the output r P t Cos Ct・・・・・・
D6J is output.

(Top) Next, the parity bit P in the input code word
Let us consider the case where the C1 bit causes an error.

In this case, the syndrome $ is S = (sa, S7
-...-...Sl, SO)-(000000101)
is obtained.

In this case, it is clear that the correction process for the C1 bit is performed in the same way as shown in (I) above.

Also, in this case, the parity generator 4 becomes logic "0",
OR circuit 5 outputs logic "1", and NOR circuit 6 outputs logic "1".
The NOR circuit 7 outputs a logic "1".

As a result, AND circuit 12, OR circuit 20, AND circuit 1
4. The input parity bit P is inverted and outputted via the exclusive OR circuit 27.

In other words, the output is "P, Co, C,...D6
" is output.

On the other hand, a 2-bit error is notified via the OR circuit 19.

(IV) Next, C in the input code word.

Consider the case where bit 701 causes an error.

In this case, the syndrome $ is S = ("8, s7-- Sl, 5O)-(0
00000110) is obtained.

As a result, from memory 2, as is clear from FIG. 5, the contents r1000J of part A and the contents r1000J of part B
0100JKichi is read out.

Therefore, in decoder 8-0, terminal "1" is logic "1".
", and in the decoder 8-1, the terminal "2" becomes logic "1".
emits.

On the other hand, at this time, the parity generator 4 outputs 2 bits.

Since it is an error, the logic becomes "0", the OR circuit 5 outputs the logic "1", and the NOR circuits 6 and 7 both output the logic "0".
is outputting.

As a result, AND circuit 11 is turned on and notifies a 2-bit error.

At this time, the NOR circuit 25 is emitting a logic "1", so the exclusive OR circuits 28, 29 . C in the input code word via.

The bit and 01 bit are inverted, and the output “P, Co,
C1...D6" is output.

(■ In addition, the parity bit P in the manual code word
and C.

Let us consider a case where an error occurs in three bits: bit and 01 bit.

In this case, the syndrome S is S = (S3.s, m・Sl, 5o) = (0000
00111) is obtained.

Regarding the part related to the Co bit and the C1 bit, the correction process is started in the same way as in the case of IVI, and the decoder 8-
0, the terminal "1" outputs a logic "1", and the decoder 8-1 outputs the terminal "2" a logic "1".

However, at this time, the parity generator 4 generates a logic "1", the OR circuit 5 generates a logic "1", and both the NOR circuits 6 and 7 generate a logic "0".

Therefore, the AND circuit 10 is turned on, the NOR circuit 25 outputs a logic "0", and the NOT circuit 26 outputs a logic "1".
``Uncorrectable error''.

On the other hand, since the NOR circuit 25 is outputting a logic "0" at this time, the AND circuits 14 to 18 are all turned off, and the exclusive OR circuits 27 to 31 pass the input code word as is, and the non-AND circuits 14 to 18 are all turned off. No desired correction is made.

(Vl) Finally, C6, C1 in the input code word
, C2 has an error.

In this case, the syndrome S is S − (SB, S7...sl, 5o) =
(000001110) is obtained.

In this case, in the memory 2, since the syndromes s8 to sl are not obtained when an error of 2 bits or less occurs, the contents of the A part and the B part are both "0OOOJ".

From this, decoders 8-0 and 8-1 both have terminal "1".
” through “15” will not produce a logic “1”.

On the other hand, the parity generator 4 outputs a logic "1", and the OR circuit 5
also outputs a logic “1”, and the NOR circuits 6 and 7 both output a logic “1”.
1" is emitted.

As a result, the AND circuit 10 is turned on, and an "uncorrectable error" is notified via the NOT circuit 26.

In FIG. 6, the parity generator 4, OR circuit 5, NOR circuits 6, 7, AND circuits 9 to 13, etc. are prepared for S in the generated syndrome.

By giving special treatment to , it can be considered that the storage capacity required for the memory 2 is halved.

That is, the syndrome S8 or s occurred.

If addresses for the memory 2 are prepared considering all combinations of , 29 addresses are required.

However, S associated with the parity bit.

By treating the memory 2 separately as shown in Figure 6,
Only 28 addresses are required for the storage capacity, which means that half of the storage capacity is sufficient.

As an alternative configuration, it is sufficient to simply provide the above-mentioned parity generator 4, and the hardware configuration becomes significantly simpler.

Of course S. For example, S. You are also free to give special treatment to and sl.

As explained above, according to the present invention, the error bit position determination process is greatly simplified by using the memory 2, and when the inspection matrix shown in FIG. In addition to simplifying the process, error bit position information can be stored in memory 2 even if conventional methods are no longer available for determining error bit positions.
It is now possible to read and use the file.

Furthermore, syndrome s8 or s.

By treating a part of the data as special, it has the advantage that the storage capacity of the memory 2 can be significantly reduced.

In addition, in the above explanation, 2-bit error automatic correction/
It goes without saying that the example of 3-bit error detection can generally be extended to random t-bit error automatic correction/(t+1)-bit error detection.

Furthermore, if reliability is a problem when reading from the memory 2 itself, it is possible to provide the memory 2 with an error correction code.

[Brief explanation of the drawing]

Figures 1 to 3 show t bit error automatic correction/(t
+1) An explanatory diagram for obtaining a check matrix for bit error detection. Fig. 4 is an explanatory diagram for explaining one embodiment of processing for obtaining a syndrome according to the present invention. Fig. 5 is an explanatory diagram for explaining an example of processing for obtaining a syndrome according to the present invention. FIG. 6, an explanatory diagram for explaining the correspondence with the stored contents, shows the configuration of an embodiment of the present invention. In the figure, 1 is a syndrome generating means, 2 is a memory, and 8-(
1 and 8-1 are decoders, 27 to 31 are exclusive OR circuits for bit inversion, $ is a syndrome, old is a check matrix, and W is a code word.

Claims (1)

[Claims] 1 An error correction code that corrects random sound bit errors (t is an integer of 2 or more) and detects (t-1-1) bit errors is added to data, and when using the data, and the error correction code added above, automatically corrects the t bit error and (t+
1) In an f-event transfer system that detects bit errors, a syndrome generating means and an error bit position corresponding to the output of the syndrome generating means are placed at an address position corresponding one-to-one to the output of the syndrome generating means. A memory is provided to store error bit position information expressed in binary representation for each individual bit error, and error correction and detection of the data is performed based on the stored contents of the memory. Further, an error correction control system is characterized in that an instruction to that effect is given in response to the occurrence of a correctable error and the occurrence of an uncorrectable error.