KR870001606B1 - Decoder for correcting code word error - Google Patents

Abstract

This invention is concerned with the decoder circuit for recorrecting the error of the corded-word. When the state signals applied to the encoder using the R-S cord, the errors are recorrected and transmitted to the circuit. Several parities are generated, so as to protect the data in regenerating the digital signals thus the encording is done. While decording the data syndrome from the state signals encorded is found to recorrect the errors. All the operation of this circuit is executed in the defined field. This offers decoder circuit that can recorrect the error of the 8-bits.

Description

Decoder Circuit for Error Correction of Codewords

Circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1,2,3,4,5,6: EXOR gate 30: Buffer

10,20,17,27: 8-bit register 15,25: 8-bit multiplex

40: 14-decimal counter 19, 21, 26: Multiplier

A ₁ , A ₂ , A ₁₀ : Endgate

The present invention relates to a decoder circuit for error correction of codewords, and to provide a circuit capable of correcting and transmitting an error in a status signal applied by an encoder using an R-S code.

In order to protect the data when the digital signal is reproduced, several parities are generated and encoded.

In decoding, it is proposed to obtain the syndrome S ₀ , S ₁ from the encoded status signal and correct the error value by this syndrome.

All these arithmetic operations are performed in a finite feed. An object of the present invention is to provide a decoder circuit that can correct an error of one symbol (8 bits) when decoding and processing 8 bits of data.

Another object is to make it possible to configure a circuit which is convenient to find an error position in error correction as a multiplier, an EXOR gate, or a noah gate.

In order to accurately identify the error value and the location of the error by syndrome (S ₀ ) (S ₁ ) and to correct the symbol, the error value of the syndrome can be fed back through an 8-bit multiplexer and register.

The status signal of the syndrome is applied through the multiplier and the gate to generate a signal indicating the error position through the noah gate.

In general, the Reed-Solomon code is the most powerful BCH code for error correction in multi-channel transmission.

d_k-2x^k-2

………………

d₁x

d₀ d (x) = d _k-1 x ^k-1

d _k-2 x ^k-2

… … … … … …

d ₁ x

d ₀

And the codeword

c_n-2x^n-2…………………

c₁x

c₀ c (x) = c _n-1 x ^n-1

c _n-2 x ^n-2 ... … … … … … …

c ₁ x

c ₀

d_k-2x^n-2

……………………

d₀x^n-k

p_r-1x^n-k-1 = d _k-1 x ^n-1

d _k-2 x ^n-2

… … … … … … … …

d ₀ x ^nk

p _r-1 x ^nk-1

p_r-2x^n-k-2………………………p₀

p _r-2 x ^nk-2 ... … … … … … … … … p ₀

With r = n-k

If

K symbols of the codeword c _n-1 , c _n-2 ,... c _{n-k + 1} , c _nk are the data words d _k-1 , d _k-2 ,. same as d ₁ , d ₀ ,

의 나머지와 같으며The remainder of the codeword c _nk-1 , c _nk-2 ,... , c ₁ , c ₀ are the ferritics, obtained by the nk order-generated polynomial g (x)

Is like the rest of

In the finite field of GF ( ^2m ), the RS code shows that the following parameters are established.

Code length: n = 2 ^{m-1 Information} amount: k = 2 ^m -2t-1

Number of Perity: n-k = 2t Initial Distance: dmin = 2t + 1

Error correction ability: t

Therefore, the decoders 14 and 12 of the present invention are calculated using a shortened RS code when defined in the GF 2 ⁸ .

n = 2 ⁸ -1 = 255

k = 2 ⁸ -2 × 1-1 = 253

If n is n-241 and k is k-241, n = 14 and k = 12.

The decoder circuit of the present invention has two number of validities and twelve data words.

When described in detail by the accompanying drawings as follows.

According to the present invention, an encoded status signal (Rx), that is, a codeword including a parity is configured to be applied to the 8-bit registers 10 and 20 through the EXOR gates 1 and 2, thereby forming the 8-bit register 10. The state signal fed back through the AND gate A ₁ is applied to the EXOR gate 1 to perform a repetitive operation added with the next symbol to obtain a syndrome S ₀ from the 8-bit register 10. do.

In the 8-bit register 20, the state signal returned through the multiplier 21 and the AND gate A ₂ is applied to the EXOR gate 2, and a repetitive operation of adding a symbol multiplied by the next symbol and α power is performed. And the syndrome S ₁ can be obtained from the 8-bit register 20.

Also, the syndrome S ₀ obtained by the codeword may be sequentially fed back from the 8-bit register 17 through the 8-bit multiplexer 15 to match an output signal of the 8-bit register 27 to represent an error value. Organize

The syndrome S ₁ performs an iterative operation such that the α power is calculated and fed back through the multiplier 26 in the 8-bit register 27 through the 8-bit multiplexer 25 to return the equation of α in the finite field. After configuring to represent the value of ₁ )

The syndrome S ₀ is applied to one side of the EXOR gate 5 through the multiplier 19 and the syndrome S ₁ is applied to the other side of the EXOR gate 5 to output the position of the error to the NOR gate NOR. It can be configured as a signal.

At this time, when the error value of the syndrome S ₀ and the position signal of the error are applied from the AND gate A ₁₀ , an error value is supplied to the EXOR gate 96 so that an error is applied to each code word applied through the buffer 30. It is configured to be removed.

Here, the counter signal CL of the 14-degree counter 40 is configured so that each codeword of the state signal Rx can be sequentially applied to each circuit. The AND gate A ₁ and A ₂ are controlled simultaneously. The control signals are applied to the bit multiplexers 15 and 25 so that 14 different symbols can be prevented from being calculated with the other 14 symbols.

In the present invention configured as described above, when the state signal Rx is inputted, 14 symbols are applied in parallel with 8-bit values.

14 symbols are c ₁₃ , c ₁₂ ,... When input in the order of c ₁ and c ₀ , it is applied to the 8-bit registers 10 and 20 through the gates 1 and 2 (abbreviated EXOR gate).

The 8-bit register 10 is c ₁₃ , c ₁₂ ,... c When inputted in codeword order of ₀ , the output is applied to one side of the AND gate A ₁ .

c₁₂

c₁₁

…

c₁

c₀이 구해진다.The output of the fourteen-counter counter 40 is applied to the other side of the AND gate A ₁ to perform a repetitive operation which is added to the previous codeword, and finally, in the 8-bit register 10, Syndrime S ₀ = c ₁₃

c ₁₂

c ₁₁

…

c ₁

c ₀ is found.

α¹²c₁₂

…

αc₁

c₀의 연산 결과가 저장하게 되며And when subjected to a code word of the 8-bit leisure requester 20 the output of which after the α W from the multiplier 21 aengeu gate (A _2), the other is applied to one side end of the gate (A ₂₎ of the The counter signal of the 14-degree counter 40 is applied to the side and is output to the gate 2 and added to the next codeword. In the 8-bit register 20, the syndrome S ₁ is S ₁ = α ¹³ c ₁₃

α ¹² c ₁₂

…

αc ₁

c ₀ result of operation is saved

As soon as the first symbol (c ₁₃ ) of the next codeword is received, the counter (zero state) output signal of the hex counter (40) is applied to the 8-bit multiplexer (15) (25) to produce the syndrome (S ₀ ) (S ₁ ). status signal is an 8-bit register 17 27 is applied to at the same time, the aND gate 14, binary counter and a counter signal in (a ₁₎ was applied to the other cheukye the aND gate of the _{(a 2) (a 1)} (a 2) "Off" to prevent the addition of the already calculated syndrome (S ₀ ) (S ₁ ) and the symbol (c ₁₃ ) of the next codeword

The symbol c ₁₃ of the next codeword is applied to the 8-bit registers 10 and 20, and iteratively performs a new syndrome S ₀ (S ₁ ) as described above according to the count signal of the hexadecimal counter 40. ).

c₁₂

…

c₀의 코드워드의 합으로 나타나는 것으로 입력된 상태신호(Rx)에 에러가 있을 때는 신드롬(S₀)에는 에러값을 갖게 된다.At this time, the syndrome S ₀ applied to the 8-bit register 17 is S ₀ = c ₁₃

c ₁₂

…

It is represented by the sum of the code words of c _{0. When} an input state signal Rx has an error, the syndrome S ₀ has an error value.

That is, the formula of Rx = c + ei is established, c is a codeword and ei is an error value.

S ₀ = R (α ⁰ ) = ei

S ₁ = R (α) = eiα ⁱ

In this relationship, the error value is ei = S ₀

으로 나타낼 수 있음을 알 수 있다. 따라서 신드롬(S₁)의 출력 신호는 멀티플라이어(26)를 통하여 반복 궤환시켜 α승을 곱한 출력 신호가 나타나도록 하여 유한 필드내에 R-S 코드로서 생성다항식

으로 표기되게 하여 g(x)=(x+α⁰)(x+α)=x²+α²⁵x+α=x²+(α+1)x+α이 되므로 유한한 값을 갖도록 한다.Error location

It can be seen that. Therefore, the output signal of the syndrome S ₁ is repeatedly generated through the multiplier 26 so that the output signal multiplied by the α power appears to be generated as an RS code in a finite field.

Since g (x) = (x + α ⁰ ) (x + α) = x ² + α ²⁵ x + α = x ² + (α + 1) x + α, it has a finite value.

When there is an error in the state signal Rx inputted in the present invention, the state path applied through the buffer 30 is output through the gate 6 for each codeword so that the codeword at the AND gate A ₁₀ may be used. By adding the error value at the error location

에서와 같이 신드롬을 나눌수 있는 회로를 제공하고자 할때에 그 회로 구성이 어렸고 복잡하여 지므로 충분히 오동작을 행할 우려가 있는 덤을 감안하여 에러의 위치를 구하는 상기식을 유한 필드내에 이항 정리를 하여

식에서 αⁱS₀

+S₁=0을 구할 수가 있으며In order to find the position of the error to correct the error by canceling the error value by the characteristic of the EXOR gate whose output becomes low potential when the two input signals of the gate 6 are high potential signals

In order to provide a circuit capable of dividing the syndrome as shown in Fig. 2, since the circuit configuration becomes small and complicated, the above equation for finding the position of the error is binarized in a finite field in consideration of the possibility of malfunction.

Α ⁱ S _{0 in the} formula

You can get + S ₁ = 0,

Syndrome S ₀ is applied to one side of gate 5 by multiplying α power α ¹³ in multiplier 19 to satisfy this on the other side of gate 5.

The syndrome S ₁ is applied to the other side of the gate 5 to be applied to the NOR gate NOR through the gate 5. Since the NOR gate is 8-bit transmission (8 channels), it can be configured as one inverter for each configured bit.

+S₁=0이 되어서 노아게이트(NOR)출력이 HIGH가 되도록 하여 에러 위치에서 앤드 게이트(A₁₀)에 인가되도록 한 것이다.Noah gate (NOR) is the formula α ⁱ S ₀ to represent a high potential signal when an error occurs

+ S ₁ = 0 so that the NOR output becomes HIGH so that it is applied to the AND gate A ₁₀ at the error position.

Therefore, when an error occurs, an error position signal and an error value of the other side are applied to one side of the AND gate A ₁₀ and supplied to the gate 6 so that the corresponding error value of each codeword can be eliminated.

That is, according to the present invention, when the data status signal Rx is applied in the order of the codewords (c ₁₃ , c ₁₂ , ... c ₀ ), (c ₁₃ ', c ₁₂ ', ... c ₀ '), the codewords (c ₁₃ , c ₁₂ ,... c ₀ ) obtains the syndrome S ₀ (S ₁ ) from the 8-bit registers 10 and 20 and occupies the entire buffer 30 at this time.

Then, the error value is obtained from the 8-bit register 17 (in this case, the codeword in the buffer 30 goes out into the buffer and the codewords c ₁₃ ', c ₁₂ ',… c ₀ 'are inputted into the buffer, and the 8-bit registers 10 and 20 are newly replaced. The syndrome is obtained so that all these operations are driven as the counter pulse CL of the 14-degree counter 40). The multiplier 19 and the gate 5 are the α operation value of the syndrome S ₁ of the 8-bit register 27. When the error value is applied to the AND gate A ₁₀ and the error value is applied to the AND gate A ₁₀ , a symbol having an error in the codeword is applied to the gate 6 to perform data correction of an 8-bit symbol. In particular, the present invention provides an output of an 8-bit register 27 and an 8-bit register 17 which are repeatedly α-operated in a finite field by returning a constant error value ei generated in error by one codeword. To match the output time of There is an advantage that it is not necessary to construct a separate circuit for matching the output timing of both registers 17 and 27, and it is possible to multiply the circuit without forming a division circuit at the time of determining the error position α. ) And the gate (EXOR gate 5) to output the error position signal through the NOR gate (NOR) has the effect of preventing malfunction, improving the operation speed and accurate error correction.

As described above, the present invention cannot perform the error correction function when there are two or more errors in the codeword (because the error correction capability is t = 1).

In the multi-processing of 8-bit data, an error of one symbol (8 bits) can be corrected accurately, and an error correction decoder circuit for codewords for finding the error position can be provided.

Claims (1)

The 8-bit registers 10 and 20 are connected to the EXOR gates 1 and 2 to be fed back to the EXOR gates 1 and 2 through the multiplier 21 and the end gate A ₁ and A ₂ . In the error correction circuit configured to obtain a syndrome S ₀ (S ₁ ), an 8-bit register 17 is connected to an 8-bit multiplexer 15, and the EXOR gate 5 is connected to one side through the multiplier 19. The multiplier 26 and the EXOR gate 5 may be configured by connecting the 8-bit register 27 to the 8-bit multiplexer 25 after configuring the connection and the error value ei applied to the AND gate A ₁₀ . Decoder circuit configured to be connected to the AND gate A ₁₆ through the NOA gate NOR and connected to the EXOR gate 6 to which the output of the buffer 30 is applied. .

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