KR870001608B1 - Decoder for digital audio equipments - Google Patents

Abstract

The invention provides a decoder suitable for digital audio units by employing a decoder for correction and an erasure flag generation circuit, for use in the circuit for processing errors generated while transmitting digital data words in the format of error correction. Several parities are generated to protect data while regenerating digital signals, and for decoding, syndromes S0, S1 are obtained from encoded state signals, by which detects error values and positions to recorrect the error value of the coded words applied to the buffer.

Description

Decoder of digital audio equipment

1 is an overall circuit diagram of the present invention.

2 is an error correction decoder circuit of the present invention.

3 is an error display circuit of the present invention.

4 is a state signal diagram of a flip-flop FF ₂ of the present invention.

5 is an output state diagram of the 14-degree counter of the present invention.

* Explanation of symbols for main parts of the drawings

1,2,5,6,7,8: EXOR gate 9,19,21,26: Multiplier

30,30 ': buffer 40: counter

15,25: 8-bit multiplexer 10,20,17,27,37,47: 8-bit register

50: OA gate portion FF ₁ , FF ₂ : Flip-flop

A ₁ , A ₂ , A ₁₁ , A ₁₂ : AND gate

The present invention seeks to provide a decoder suitable for digital audio equipment as an error correction decoder circuit and an error display circuit in an error processing circuit generated when a digital data word is transmitted in an error correction format.

In order to protect the data during digital signal reproduction, several parities are generated and encoded. When decoding, a syndrome S ₀ S ₁ is obtained from the encoded state signal.

By this syndrome, the codeword applied to the buffer by finding the error value and error location is proposed to correct the error value.

All of these calculations are to be performed within a finite field. However, when an error exceeding the error correction capability t occurs, an error flag circuit (Erasure Flag Gerneration) indicating that the encoded status signal is an error is required.

Therefore, the conventional error display circuit requires a bit of a digital signal ("1", "0") indicating an error in the most significant bit (MSB), so that all signals must be processed as 9 bits in 8-bit data transmission. It could not prevent the increase in size.

However, in the decoder circuit that can correct the error of one symbol (8 bits) when the 8-bit data is multi-processed and encoded, the syndrome (S ₀ ) (S ₁ ) is a convenient circuit to find the error position during error correction. By using the error correction decoder circuit and the error correction decoder circuit, where the error value and the error position can be accurately identified and the error correction decoder circuit easily corrects all symbols, all 8-bit signals are stored in the codeword symbols. An error display circuit that can be corrected to ("1" or "0") is connected so that error processing is easy and hardware size can be reduced by preventing the number of bits from being increased during data signal processing.

In consideration of the high probability of single error in digital audio equipment, single error correction can be performed, which simplifies the circuit and speeds up processing, and becomes an error indication when an error that exceeds the error correction capability occurs. It is an object of the present invention to provide a decoder of a digital audio device having a reproduction ability that is almost indistinguishable by hearing and has a reproduction ability that is nearly original.

In general, the R-S code (Reed-Solomon Dode) is the most powerful BCH code for error correction in multi-channel transmission, so that the associative processing is performed on the Salois field so that the data word of k symbols is obtained.

And the codeword

는 데이타 워드

와 같으며 코드 워드의 나머지

는 패리티로서 n-k 차 생성다항식g(x)예 의하여 구해지며 그 값은

의 나머지와 같으며 GF(2^m) : 유한 필드내에서 R-S부호는 다음과 같은 매개 변수가 성립됨을 알 수 있다.Suppose that k symbols of a code word

Is the data word

Is the same as the rest of the codeword

Is the parity obtained by the nk-generated polynomial g (x).

GF (2 ^m ): RS code within finite field shows the following parameters.

Code length: n = 2 ⁿ -1 Information amount: k = 2 ^m -2t-1

Parity number: n-k = 2t Minimum distance: dmin = 2t, 1

Error correction ability: t

Therefore, the decoder (14, 12) circuit of the present invention is calculated using a shortened RS code when defined in the GH (2 ⁸ )

n = 2 ^8-1 = 255

k = 2 ⁸ -2 × 1-1 = 253

When n-241 and k-241 are selected so that parity number = nk = 2t = 2 ∴ t = 1, n = 14 and k = 12. The decoder circuit of the present invention has two parity numbers and a data word There are 12 decoder circuits with calibration capability t = 1.

Therefore, in such a decoder circuit, when an error signal is included in one symbol (8 bits) of the codeword, an error signal is included, but an error signal included in two or more symbols cannot be corrected. An error display circuit is needed to indicate that the decoded status signal is an error.

Thus, the present invention provides a circuit which is convenient for finding an error position at the time of error correction in an error correction decoder circuit, corrects an error in the range of error correction capability (t = 1), and generates a codeword when an error exceeding the error correction capability occurs. It is intended to construct a circuit capable of converting all 8-bit signals to a selected digital signal ("1" or "0") in the symbol.

FIG. 1 is an overall circuit diagram of the present invention, wherein a status signal of each symbol (8-bit signal) of a codeword CX including a data status signal and a parity status signal is applied to the error detection circuit ER 10 and buffy 30. After obtaining the syndrome S ₀ (S ₁ ) from the error detection circuit ER 10, when S ₀ ≠ 0 and S ₁ ≠ 1 when an error occurs, the error value is calculated after calculation is performed in the syndrome calculation circuit ER 20. The error value is detected by the detection circuit ER 32.

The error position detecting circuit ER 31 detects the error position and configures the error eliminating unit ER30 to output the gate ER 33 through the error eliminating unit, and an error signal at the position of each symbol output through the buffer 30. And the codewords outputted to the buffer 30 'by the error values applied to the error removal unit ER 30 by canceling each other. ) Outputs a data status signal from which parity is removed.

Only when an error exceeding the error correction capability (t = 1) occurs, the code word CX applied to the buffer 30 in the state in which the error removal unit ER 30 is not driven has an error in the error detection circuit ER 50. The error signal and the parity cancellation circuit ER 40 are driven by the output signal generated at the time to generate a flag signal of the digital status signal of "1" in all 8-bit symbols output to the buffer 30 '. It is configured so that the output data status signal is an error condition.

In detail, the circuit of FIG. 2 and FIG. 3 shows the error correction decoder circuit. FIG. 2 shows the codeword CX including the parity status signal generated to protect the data signal. It is configured to be applied to the 8-bit registers 10 and 20 through (2), and the state signal fed back through the AND gate A ₁ from the 8-bit register 10 is applied to the EXOR gate 1. It is configured to obtain a syndrome S ₀ from the 8-bit register 10 by performing a repetitive operation added with the symbol.

In the 8-bit register 20, the multiplier 21 and the end gate A ₁ are configured so that the quenched status signal is applied to the EXOR gate 2 so that a symbol multiplied by the next symbol and α power is added. The syndrome S ₁ can be obtained from the 8-bit register 20.

In addition, the syndrome S ₀ obtained by the codeword is configured to be sequentially fed back from the 8-bit register 17 through the 8-bit far-extractor 15 to coincide with the output signal of the 8-bit register 27 to obtain an error value. To represent the

The syndrome S ₁ performs a repetitive operation such that the α power is computed and fed back through the multiplier 26 in the 8-bit register 17 through the 8-bit multiplexer 25 so that the equation is changed to α in the finite field. After configuring to represent the value of S ₁ )

The syndrome S ₀ is applied to one side of the EXOR gate 5 through the multiplier 19 and the syndrome S ₀ is applied to the other side of the EXOR gate 5 to output the position of the error to the NOR gate NOR. It can be configured as a signal.

At this time, when the position signal of the error of the error value of the syndrome S ₀ is applied at the AND gate A ₁₀ , an error value is supplied to the EXOR gate 6 to supply an error value to each codeword applied through the buffer 30. It is configured to be removed.

Here, the counter signal CL of the 14-degree counter 40 is configured so that each codeword of the status signal R _X can be sequentially applied to each circuit, while controlling the AND gate A ₁ (A ₂ ). The control signal is applied to the 8-bit multiplexer 15 and 25 to prevent 14 different symbols from being calculated with the other 14 symbols.

3 is an error display circuit of the present invention.

When the correction capability is exceeded and each symbol of the codeword CX including the error state signal is applied in units of 8 bits, the symbols are applied to the 8 bit registers 37 and 47 through the EXOR gates 7 and 8. The state signal fed back from the 8-bit register 37 through the AND gate A ₁₁ is applied to the EXOR gate 7 to perform a repeating operation which is added to the next symbol, thereby causing a syndrome (S ₀ ) in the 8-bit register 37. ) To be available.

In the 8-bit register 12, a state signal fed back through the multiplier 9 and the end gate A ₁₂ is applied to the EXOR gate 8 to perform a repetitive operation of adding a symbol multiplied by the next symbol and α power. The error detection circuit 10 is configured so that the syndrome S ₁ can be obtained from the 8-bit resist 47 so that an error occurs in each symbol of the codeword CX. The output signal is configured to be applied to the input terminal D of the flip-flop FF ₁ through the orifice N ₁₁ , and the oragate unit 50 is speeched so that the error occurs in the oracle unit 50 when an error of each symbol occurs. By applying the above status signal, all 8 bits of the error symbol are configured to maintain the status signal of "1".

The counter signal CL of the 14-degree counter 40 is configured so that each symbol of the codeword CX can be sequentially applied to each circuit. The AND gate A ₁₁ (A) of the error detection circuit ER 50 is used. ₁₂ and the flip-flop FF ₂ through the AND gate A ₈ (A ₉ ) to output only the data state signal by removing the carry included in the codeword CX by the counter state signal. After the configuration to control the And gate portion 60 is configured to connect.

Here, the buffer 30 'is an output signal P ₁ of each 8-bit symbol through the buffer 30' in spite of the presence or absence of an error in the symbol of the codeword CX. It is configured to be applied to).

4 is a state signal diagram of the flip-flop (FF) of the present invention, which shows an output signal for removing parity inserted into a codeword to protect data.

5 shows an output state diagram of the 14-degree counter of the present invention.

In the present invention configured as described above, when the encoded state signal (cx) is input, the state signal is applied to eight channels simultaneously as 14 code words.

The 14 codewords are applied to the 8-bit registers 10 and 20 through gates 1 and 2 (abbreviated as EXOR gates) when input in the order of cc ... cc.

When the 8-bit register 10 is input in codeword order of cc ... c order, its output is applied to one side of the AND gate A, and the output of the hexadecimal counter 40 is connected to the AND gate A ₁ . It is applied to the other side and performs repetitive operation that is added to the immediately preceding codeword. Syndrome S ₀ = c ₁₃ + c ₁₂ + c ₁₁ ... c ₁ + c ₀ is obtained in the 8-bit register 10. .

When the above codeword is applied to the 8-bit register 20, the output is applied to the one side of the AND gate A ₂ after the α power is applied by the multiplier 21, and the output is applied to the other side of the AND gate A ₂ . The counter signal of the true counter 40 is applied and output to the gate 2 and added to the next codeword. In the 8-bit register 20, the syndrome S ₁ is S ₁ = α ¹³ c ₁₃ + α ¹ -c The operation result of ₁₂ +, ... αc ₁ + c ₀ will be saved

As soon as the first symbol (c ₁₃ ) of the next codeword is received, the counter (zero state) output signal of the hex counter (40) is applied to the 8-bit multiplexer (15) (25) and the state of the syndrome (S ₀ ) (S1). signal to be applied to the other side of the 8-bit register 17 (27), the counter signals 14 binary counter at the same time that it is end to the gate (a ₁₎ (a ₂₎ and-Kate _{(a 1) (a 2)} - a "off" sikieo already calculated a syndrome (S ₀₎ (S ₁₎ and the next symbol of a code word (c ₁₃₎ symbols of a next code word in the preventing added to an 8-bit register (10) (20) (c 13) The new syndrome S ₀ (S ₁ ) is obtained by applying an iterative operation as described above according to the count signal of the 14-degree counter 40.

At this time, the syndrome S ₀ applied to the 8-bit register 17 is represented by the sum of the code words of S ₀ = c ₁₃ + c ₁₂ , ... c ₁ + c ₀ . If is, the syndrome (S ₀ ) has the same error value.

That is, the expression cx = c, ei is established and c is the codeword ei is the error value.

S ₀ = R (α ⁰ ) = ei

으로 나타낼 수 있음을 알 수 있다.The relationship of S ₁ = R (α) = eiai gives the error value ei = S ₀ and the error position is α ⁱ =

It can be seen that.

으로 포기되게 하여 g(x)=(x+a)(x+a)=x²+a²⁵x+a=x²+(a+1)x+a이 되므로 유한한 값을 갖도록 한다.Therefore, the output signal of the syndrome S ₁ is repeatedly fed back through the multiplier 26 so that the output signal of the α power is displayed so that it is generated as an RS code in a finite field.

Since g (x) = (x + a) (x + a) = x ² + a ²⁵ x + a = x ² + (a + 1) x + a so that it has a finite value.

에서와 같이 신드롬을 나눌수 있는 회로를 제공하고자 할때에 그 회로 구성이 어렵고 복잡하여지므로 충분히 오동작을 행할 우려가 있는 점을 감안하여 에러의 위치를 구하는 상기식을 유한필드내에 이항 정리를 하여 αⁱ=

식에서

을 구할 수가 있으며 게이트(5)에서 이를 만족시킬 수 있게 신드롬(S₀)은 멀티플라이어(19)에서 α승(α¹³)만을 곱해서 게이트(5)의 일측에 인가되고 게이트(5)의 타측에는 신드롬(S₁)이 인가되어 게이트(5)를 통하여 노아게이트(NOR)에 인가되게 된다.When there is an error in the state signal CX applied in the present invention, the state signal applied through the buffy 30 is outputted through the gate 6 for each codeword so that the error of the codeword in the AND gate A ₁₀ . By adding an error value at the position, when the two input signals of the gate 6 are high potential signals, the output value is canceled by the characteristic of the EXOR gate whose output becomes low potential, so as to find the position of the error so that the error can be corrected. Equation α ⁱ =

By the binomial theorem to the formula since the difficult and the circuit configuration in the complex when trying to provide a circuit which divided the syndrome in view of the points which might well be a malfunction to obtain the location of the error within a finite field such as in α ⁱ =

At the ceremony

In order to satisfy this in the gate 5, the syndrome S ₀ is applied to one side of the gate 5 by multiplying only the α power (α ¹³ ) in the multiplier 19 and the other side of the gate 5. The syndrome S ₁ is applied to the NOR gate NOR through the gate 5.

이

이 되도록하여 에러 위치에서 앤드 게이트(A₁₀)에 인가되도록 한 것이다.Since the NOR gate is an 8-bit transmission (8 channels), it can be configured as one inverter for each configured bit. The NOR gate can express a high potential state signal when an error occurs.

this

This is to be applied to the end gate (A ₁₀ ) at the error position.

Therefore, when an error occurs, an error position signal and an error value of the other side are applied to one side of the AND gate A ₁₀ and supplied to the gate 6 so that the corresponding error value of the symbol of each codeword can be eliminated.

That is, according to the present invention, when the data status signal cx is applied in the order of codewords (c ₁₃ , c ₁₂ ... c ₀ ), (c ₁₃ ', c ₁₂ ' ... c ₁ ', c ₀ '). The syndromes are obtained from the 8-bit registers 10 and 20 by the codewords c ₁₃ , c ₁₂ ... c _0. At this time, 14 symbols are filled in the buffer 30.

Then, an error value is obtained from the 8-bit register 17. At this time, new co-words C ₁₃ ', C ₁₂ ', ... C ₀ 'are input to the buffer 30, and the 8-bit registers 10 and 20 are newly synthesized. This operation drives all of these operations as the counter pulse CL of the 14-counter counter 40.

Therefore, the position of the error in the multiplier 19, the gate 5, and the noar gate NOR is determined by the α operation value of the syndrome S ₁ of the 8-bit register 27, and the error value in the AND gate A ₁₀ is determined. In this case, the symbol having an error in the codeword is applied to the gate 6 when it is applied to perform data correction of 8-bit symbols. In particular, the present invention provides a constant error value (ei) generated at the time of error by one codeword. By returning), the output time of the 8-bit register 27 and the output time of the 8-bit register 17 which are repeatedly α-operated in the finite field can be matched, so that the output time points of the registers 17 and 27 are matched. There is an advantage that there is no need to configure a separate circuit for the circuit, and the error position signal as a multiplier circuit (multiple tire 19) and a gate (EXOR gate 5) is constructed by not forming a division circuit when determining the error position α ⁱ . (NOR By outputting through), it is possible to prevent the malfunction, increase the operation speed and correct the error. Also 14 binary counter signal is to be output as fifth degree Table counter signal (CT) when (1,0,1,1), the flip-flop (FF ₂₎ is re-configured to be set, and a status signal (1,0,1 When 1, the flip-flop FF ₂ is set so that the AND gates A ₈ and A ₉ are configured so that the input / output state of the flip-flop FF ₂ is always output as shown in FIG. 4 despite an error in the thimble. do.

That is, the codeword (CX) is represented by the sum of each symbol c ₁₃ , c ₁₂ , c ₁₁ ... c ₁ , c ₀ , where c ₁₃ to c _{12 is} the data status signal and c ₁ , c ₀ is the data. Parity to protect. Therefore, only the original data signal is needed for decoding, and the parity signal needs to be removed. As shown in FIG. 4, a set signal is applied to the cent terminal S of the flip-flop FF ₂ through the AND gate A ₈ . When the symbols c ₁₃ to c ₂ applied to the output QL are applied to the high gate state signal of the AND gate part 60, the symbols c ₁₃ , c ₁₂ ... c applied through the oragate part 50. ₂ ) When the data state signal, which is a signal, is output and the symbols of the parity state signals c ₁ and c ₀ are applied, a reset signal is applied to the reset terminal R to the flip-flop FF ₂ so that the AND gate unit 60 is applied. the block codewords (CX) a parity symbol of because (c _1, c ₀₎ is insulated from the AND gate (a ₈₎ that can be coded only the original data signal to when they not an error occurs in the code word ( Flip-flop as a control signal of the fourteen counter 40 through A ₉ ). The FF ₂ can be controlled, so that the end-category unit 60 can be controlled without configuring a separate counter circuit.

In addition, each symbol of the 14 codewords contains an error signal in each symbol of the codeword CX that has exceeded the correction ability (t = 1), and the errors are in the order of c ₁₃ , c ₁₂ ... c ₁ , c ₀ . When applied to the sensing circuit ER 50 is applied to the 8-bit register (37) 47 through the EXOR gate (7) (8).

When the symbols of c ₁₃ , c ₁₂ ... c ₁ , c ₀ are input, the 8-bit register 37 is applied to one side of the AND gate A ₁₁ , and the output of the hex counter 40 is It is applied to the other side of the AND gate A ₁₁ to perform a repetitive operation added with the immediately preceding symbol to obtain a syndrome S ₀ .

S ₀ = c ₁₃ , c ₁₂ , c ₁₁ ... c ₁ , c ₀

In addition, when each symbol of the higher codeword is applied to the 8-bit register 47, the output is applied to one side of the AND gate A ₁₂ after the? Power in the multiplier 9, and is applied to the AND gate A ₂ . as is applied to the counter signal of the other side 14, binary counter 40 is output to the gate 8 is also be included with the next code symbol wodeuyi syndrome (S ₁₎ is

If the value of syndrome (S ₀ ) (S ₁ ) is all 0, there is no error in codeword. If the value of syndrome (S ₀ ) (S ₁ ) is not 0, error value Is applied to the input terminal (D) of the flip-flop (FF ₁ ) through the orifice (N ₁₁ ), and the high-potential output signal from the output terminal (Q) of the flip-flop (FF) to the oragate unit (50). Is outputted through the AND gate unit 60 as described above, with a flag of “1” attached to all 8 bits regardless of the presence or absence of an 8-bit thimble state signal applied to the oragate unit 50. Therefore, when an error occurs in the codeword symbol while the parity symbol is removed from the AND gate unit 60, all bits are converted to "1" to output a data state signal capable of recognizing an error state. .

In particular, the present invention enables an error display by attaching an error flag of " 1 " to an 8-bit signal that is a symbol of a codeword, thereby preventing the number of bits from being increased during data signal processing, thereby reducing the hardware size. In order to enable this flag signal to appear as a "0" bit, an output post-inverter of the flip-flop (FF ₁ ) may be configured, but the error flag of "1" when the present invention is applied to a digital audio device. The number of bits to be expressed is more preferable than the bits of " 0 " since all 8-bit signals rarely maintain the number of bits of " 1 " in processing digital audio signals.

으로 나타낼수 있을때 신드롬(S₀)(S₁)을 나눌수 있는 회로의 구성이 어렵고 복잡하여지므로 충분히 오동작을 행할 우려가 있는 점을 감안하여 유한 필드내에서 이항 정리한 후

식을 만족할 수 있는 멀티 플라이어(19) 및 EXOR 게이트(5)를 구성시킬 수가 있어 8비트용 데이타를 다중 처리하여 테코딩할때에 한 심볼(8비트)의 에러를 정정할 수 있는 데코더 회로에서 에러 정정시에 에러 위치를 찾아내기 편리한 효과가 있으며 에러 정정용 데코더에서 에로 정정 능력을 초가하는 에러 발생시에는 에러 감지회로(ER 50)의 후단에 오아게이트(N₁₁)를 통하여 플립플롭(FF₁)을 제어하여 버퍼(30')로 인가되는 각 심볼(8비트)에 8비트 신호를 모두 디지탈 신호의 "1"프래그 신호로 변환시킬수 있도록 함으로써 에러 상태의 출력 신호를 표시할 수 있게 함과 동시에 14진 카운터 회로의 카운터 신호르 앤드 게이트로서 변환시켜 코드워드(CX)에 포함된 패리티를 제거시켜 원래의 데이타 상태 신호를 출력시킬 수가 있는 것으로 아날로그의 음을 디지탈 신호 처리하는 디지탈 오디오 기기에서 단일 에러는 정정시켜 원음으로 재생시키는 동시에 에러 정정 능력을 초가하는 에러 발생시에는 「1」의 프래그 신호로서 신호가 없도록 함으로써(묵음) 필요없이 많은 에러 정정 능력을 가질때 보다 처리 속도를 높히는 동시에 청각에 의하여는 거의 원음과 같은 재생 능력을 발휘할 수 있는 복호기를 제공할 수가 있는 것이다.As described above, in the present invention, the error position in configuring the first degree error canceling unit ER 30 is α ⁱ =

Since it is difficult and complicated to construct a circuit that can divide syndrome (S ₀ ) (S ₁ ) when it can be expressed as

In the decoder circuit capable of constructing a multiplier 19 and an EXOR gate 5 capable of satisfying the equation, and correcting an error of one symbol (8 bits) when the 8-bit data is multi-processed and recorded. When the error is corrected, it is convenient to find the error position.In case of an error that exceeds the error correction capability in the error correcting decoder, flip-flop FF _{1 is} formed through an ore gate N ₁₁ at the rear end of the error detection circuit ER 50. By controlling all the 8-bit signals in each symbol (8 bits) applied to the buffer 30 'to the "1" flag signal of the digital signal, it is possible to display the output signal in error state. It converts the counter signal of the true counter circuit as the gate and gate, removes the parity contained in the codeword (CX), and outputs the original data state signal. In a digital audio device that performs de-signaling, when a single error is corrected and reproduced in the original sound, and an error that exceeds the error correction capability occurs, there is no signal as a flag signal of "1" (mute) and it has a lot of error correction capabilities without need. It is possible to provide a decoder capable of speeding up the processing more and at the same time hearing can reproduce almost the original sound.

Claims (1)

The 8-bit registers 10 and 20 are connected to the EXOR gates 1 and 2 and fed back to the EXOR gates 1 and 2 through the multiplier 21 and the end gate A ₁ and A ₂ . In the error correction circuit configured to obtain the syndrome S ₀ (S ₁ ), the output side of the 8-bit registers 17 and 27 is provided.

By configuring a multiplier 19 and an EXOR gate 5 satisfying the error condition, the error position α ⁱ signal through the NOA gate NOR and the error value ei of the 8-bit multiplexer 15 are obtained from the AND gate A _10. ) Is flipped through the oragate (N ₁₁ ) at the rear of the error correction decorator circuit configured to be supplied to the EXOR gate (6), such as the output of the buffer 30, and the normal sensing circuit (ER 50). After configured to control the flop (FF ₁ ) and configured to be connected to the AND gate portion 60 through the oragate portion 50 and flip-flop through the end gate (A ₈ ) (A ₉ ) in the 14-degree counter 40 (FF ₂ ) is configured to convert the 8 bits of each symbol applied through the buffer 30 'to the bit signal of "1" when the error of the symbol is detected. and the correction decoder circuit gate ₍₁₀ a) and the buffer 30 and the associated EXOR gate 6 side The gate of the error display circuit 7, 8 and the decoder of the digital audio device that configured to be connected to a buffer 30 '.

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