KR100212830B1 - Syndrome calculation apparatus of reed solomon decoder - Google Patents

Abstract

The present invention relates to a syndrome calculation device of a Reed Solomon decoder, and a galloace adder (43) outputting a syndrome calculation cell by adding a received symbol (r _i ) and an intermediate value inputted through a register (11): The register 45 for latching and outputting the value output from the Aceh adder 43 according to the symbol clock sym_clk: the ROM 47 and the root (a ⁱ ) of the code generation polynomial g (x) are stored. The intermediate value is inputted to the galloche adder 43 by multiplying the root a ⁱ of the code generation polynomial g (x) stored in the ROM 47 by the value output from the register 45. Comprising a galloa adder 49 outputting as a syndrome (S _i ), by implementing a syndrome cell without using a multiplexer, the structure is not only simple, but the area is reduced to a very large integrated circuit (VLSI) It is easy to implement.

Description

Syndrome Calculator of Reed Solomon Decoder

1 is a schematic configuration diagram of a typical Reed Solomon decoder.

2 is a circuit diagram of a conventional syndrome calculation device.

3 is a circuit diagram of a conventional syndrome calculation cell.

4 is a circuit diagram of a syndrome calculation cell of a Reed Solomon decoder according to the present invention.

* Explanation of symbols for main parts of the drawings

1: first-in-first-out buffer 3: syndrome calculation unit

5: error position polynomial calculation unit 7: error correction unit

9 control unit 43 Galoache Adder

45: register 47: ROM

49: galloche adder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Reed Solomon decoder for error correcting and decoding digital data subjected to error correcting coding (error control coding: ECC) by a Reed solomon encoder (RS encoder). The present invention relates to a syndrome calculation device of a Reed Solomon decoder which receives a Solomon-coded digital data and calculates a syndrome.

In general, error correction coding (ECC) encodes digital data for detecting and correcting an error occurring when transmitting digital data through a communication channel or storing in a storage medium, and adds data used for detecting or correcting an error. This increases the reliability of the data.

The history of this error correction code (ECC) began in 1948 with Shannon. In 1948, Shannon Shannon established a communication system that transmits data at a transmission rate R (bps), which has a unique transmission capacity of C (bps) and does not exceed that capacity. Using the sign proves which channel is possible. In other words, it is more economical to use an error correction code while using an existing channel that is somewhat poorer than implementing a very good channel.

However, Shannon only proved that an error correction code exists and did not mention how to find the error correction code.

Accordingly, efforts to find an error correction code have been steadily progressed up to now, and the error correction code is largely divided into a block code and a nonblock code. The block code divides the information sequence into blocks of k bits and then error corrects the code in block units. The non-block code encodes the entire information into the information sequence. Representative examples of such block codes include BCH codes (Bose and Ray-Chaudhuri and Hocquenghem code) and Reed Solomon codes (RS code), and representative examples of non-block codes include convolutional codes. have. The BCH code is operated on Galoache GF (2 ^m ) as a cyclic code.

A cyclic code refers to a linear code in which a cyclic shifted linear vector is a linear vector of the linear code, regardless of cyclic shift of any linear vector of the linear code.

Therefore, the BCH code can be coded using the feedback shift register when the code generation polynomial g (x) is determined as in the following Equation 1 below.

In this case, the BCH code has the ability to correct up to t errors if the generated polynomial g (x) has two consecutive roots.

On the other hand, the Reed Solomon code is an optimal code of the BCH code and can correct t errors if the code generation polynomial is determined as in the first equation.

Accordingly, Reed Solomon codes are currently used not only widely in communication and computer storage systems, but also in secret communication systems as a way to combat jamming.

This Reed Solomon code is operated on Galoache GF (2 ^m ) similarly to the BCH code. That is, the Galoache GF (2 ^m ) is a number system having 2 ^m elements. When the hardware system is implemented in hardware, each element may be represented by m binary digits. Not only is it effective for the digital structure, but no overflow occurs.

Reed Solomon code having a code on Galoache GF (2 ^m ) as described above is a systematic code that does not mix information and parity, and a nonsystematic code that mixes information and parity. Are classified.

The systematic code is obtained by first moving the information to a higher byte so as not to mix information and parity, and then obtaining an error correction code, and is obtained from the following equation.

In the second equation, c (x) is a codeword polynomial, i (x) is an information polynomial, and t (x) is a polynomial of error correction parity.

That is, the information i (x) is moved to the higher byte by χ ^{NK difference} so as not to mix information and parity, Find the parity t (x) that satisfies.

And, The parity t (x) that satisfies can be obtained from the following equation.

In the above Denotes the remainder of the codeword polynomial c (x) divided by the code generation polynomial g (x).

That is, to obtain the parity t (x) Is divided by the code generation polynomial g (x), which can be implemented by concatenating the shift registers according to the code generation polynomial g (x).

In the non-system code, information and parity are mixed by simply multiplying the information by the code generation polynomial g (x) as shown in Equation 4 below.

In equation 4, c (x) is an n-1 order codeword polynomial, i (x) is an k-1 order information polynomial, and g (x) is an n-k order code generating polynomial.

The code generating polynomial g (x) is multiplied by the information polynomial i (x) to produce a codeword polynomial c (x). The code generating polynomial g (x) is multiplied by two consecutive roots as in Equation 5 below. If we set to have t errors, we can correct t errors.

Reed-Solomon decoding of Reed-Solomon-coded digital data as described above is largely divided into frequency-domain decoding and time-domain decoding, and the process of Reed-Solomon decoding in the time domain is performed in four steps as follows.

1) Calculation of syndrome

The received data r (x) may be expressed as a sum of a codeword polynomial c (x) and an error polynomial e (x) generated during transmission, as shown in Equation 6 below.

Therefore, it is possible to know whether an error has occurred during transmission by assigning the roots a ⁰ to a ^2t-1 of the code generation polynomial g (x) in order to the received data r (x) as shown in Equation 7 below.

That is, when the received data r (x) becomes 0 by substituting the root a ⁱ of the code generation polynomial g (x) into the received data r (x), it means that no error occurred during transmission. If the received data r (x) does not become 0 by substituting root a ⁱ of the code generation polynomial in (x), it means that an error has occurred in the i th position or the i th order.

2) Finding error location polynomial

Compute the coefficients of the error location polynomials from the Berlekamp-Massey algorithm or the Euclid algorithm.

If the error position polynomial obtained by the above algorithm is sigma (X), a polynomial of not more than t is obtained in the Reed Solomon code having an error correction capability of t as shown in Equation 8 below.

3) Error value calculation

Substituting a ^-t into the error position polynomial σ (X) finds the position of the error.

That is, when a ^-t is substituted into the error position polynomial σ (X) and the error position polynomial σ (X) becomes 0, an error occurs at the i th position or the i th order.

The error evaluation polynomial? (X) can be obtained from the following ninth expression.

In Formula 6, S (X) is a syndrome polynomial.

Thus, the error evaluation polynomial Ω (X) is obtained and the error value e _i is calculated from the following equation.

In Equation 10, σ 'is a value obtained by differentiating the error position polynomial σ.

4) Error correction

After the error value is obtained as described above, the original codeword polynomial c (x) is obtained by using Equation 11 below.

At this time, if the same value is added to the characteristics of galloise becomes 0, e (x) + e (x) = 0.

On the other hand, a typical Reed Solomon decoder that implements the Reed Solomon decoding method as described above in hardware, as shown in FIG. 1, first-in, first-out of temporarily storing and outputting the Reed Solomon-coded received signal r (x). A buffer 1 and a syndrome calculator for calculating and outputting a syndrome S _i from the Reed-Solomon-coded received signal r (x): A syndrome position polynomial σ (X) is calculated by receiving the syndrome S _i . The error position polynomial calculating unit 5 outputs the error estimation polynomial Ω (X) by receiving the syndrome S _i and the error position polynomial σ (X), and calculates an error value e _i from the error evaluation polynomial Ω (X). An error correction unit 7 for correcting an error generated in the received signal r (x) by adding the error value e _i to the received signal r (x) output from the first-in first-out buffer 1; Part (3) and error Is configured to include a value polynomial calculation unit 5 and a controller 9 that control each of the error correction unit (7).

The syndrome calculation unit 3 receives the received signal r (x) and calculates syndrome S _i . At this time, the syndrome calculation unit 3 completes the syndrome calculation only when one code word c (x) is input. .

The error position polynomial calculation unit 5 calculates a polynomial that can find the error position through the Berlekamp algorithm, the Euclid algorithm, or the like, and outputs the error position polynomial σ (X) to the error correction unit 7. The error correction unit 7 obtains an error evaluation polynomial Ω (X) from the error position polynomial σ (X) and the syndrome S _i output from the syndrome calculation unit 3, and then obtains an error from the error evaluation polynomial Ω (X). Obtaining the value e _i and adding the received signal r (x) output from the first-in first-out buffer 1 to correct an error generated in the received signal r (x) to output an error corrected decoded code word c (x). will be.

As shown in FIG. 2, the syndrome calculator 3 latches the read solo decoded received signal r (x) according to the symbol clock sym_clk to sequentially input the received symbol r _i . The register 11 and the receiving symbol r _i are sequentially input through the register 11 and the syndrome S ₀ to each root a ⁰ to a ^{2t-1 of} the code generation polynomial g (x) is received. A plurality of (2t) syndrome calculation cells 13-1 to 13-2t for calculating S _2t-1 ) are included.

For example, in the syndrome calculation unit 3 used in the Reed Solomon decoder for decoding Reed Solomon codes (N, K), NK = 2t syndrome calculation cells 13-1 to 13-2t are required. . That is, it receives N symbols (one code word) and calculates _2t syndromes S ₀ to S _{2t-1 at} the same time.

In this case, each of the syndrome calculation cells 13-1 to 13-2t is a hardware implementation of a syndrome calculation formula such as the following equation 12.

In the above, r _j means a received symbol in which the received signal r (x) is input in synchronization with the symbol clock.

As shown in FIG. 3, each syndrome calculation cell 13-1 to 13-2t, which implements the 12th equation in hardware, includes a galloise adder for adding the received symbol r _i and the median value. 31) and: first ROM 33, in which the root a ⁱ of the code generation polynomial g (x) is stored; second ROM 35, in which 1 is stored; Multiplexer 37 for selectively outputting the values stored in the ROM (33, 35): The intermediate value by multiplying the value output from the galloche adder 31 and the value input through the multiplexer 37 Galoache multiplier 39 to output: The intermediate value outputted from the galoache multiplier 39 is latched in accordance with the symbol clock sym_clk and input to the galloa adder 31 and as a syndrome S _i . It is comprised including the register 41 to output.

The multiplexer 37 is configured to receive a codeword end signal cw_end as a selection signal, and when the codeword end signal cw_end is input, 1 is stored in the second ROM 35. It is input to the Aceh multiplier 39.

In the conventional syndrome calculation cell configured as described above, the galloa adder 31 is input to the galloa multiplier 39 by adding the depth symbol r _i and the intermediate value input through the register 41.

On the other hand, the multiplexer 37 selectively outputs 1 stored in the root a ⁱ of the code generation polynomial g (x) stored in the first ROM 33 or in the second ROM 35.

That is, the multiplexer 37 receives the codeword end signal cw_end as a selection signal and, when the codeword end signal cw_end is input, selects and stores 1 stored in the second ROM 35. In other cases, the root a ⁱ of the code generation polynomial g (x) stored in the first ROM 33 is selected and output.

In addition, the galloa multiplier 39 multiplies the root (a ⁱ ) or 1 of the code generation polynomial g (x) input through the multiplexer 37 with the value input from the galloa adder 33 to register ( Enter 41).

In addition, the register 41 latches the intermediate value input from the galloise multiplier 39 according to a symbol clock and inputs it back into the galloise adder 33.

By repeating the process as described above, it is finally a syndrome (S _i) output from the register 41.

However, the conventional syndrome calculation cell as described above has a complex structure and an area increase due to the use of the second ROM 35 and the multiplexer 37 where 1 is stored, thereby increasing the area of a large scale integrated circuit (VLSI). There was a problem that is not suitable for implementation.

Accordingly, the present invention has been made to solve the above-mentioned problems, and by implementing a syndrome calculation cell without using a multiplexer, it provides a syndrome calculation device of a Reed Solomon decoder having a simple structure and a reduced area. Its purpose is to.

A syndrome calculation apparatus for a Reed Solomon decoder according to the present invention for achieving the above object comprises a register for latching a Reed Solomon decoded received signal according to a symbol clock to sequentially input a received symbol, and then sequentially receiving the received symbol through the register. A syndrome calculation device including a plurality of syndrome calculation cells for receiving syndromes and calculating syndromes for each root of a code generating polynomial, the syndrome calculation cell comprising: a galloche adder for outputting the received symbol plus the intermediate value; A register for latching and outputting the value output from the galloche adder according to a symbol clock; and a ROM storing a root of a code generating polynomial and a root of a code generating polynomial stored in the ROM and a value output from the register. Galoache multiplier that multiplies and inputs the median into the Galoache adder And it characterized in that configured included.

Therefore, as a syndrome cell is implemented without using a multiplexer, the structure is not only simple, but the area is reduced, and thus it is easy to implement a large scale integrated circuit (VLSI).

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

4 is a circuit diagram of a syndrome calculation cell according to the present invention, wherein the syndrome calculation cell according to the present invention includes a galloa adder 43 for outputting by adding a reception symbol r ₁ and an intermediate value: the galloa adder 43 Register 45 latches and outputs the value outputted by the symbol clock (sym_c1k) according to the symbol clock (sym_c1k): a ROM 47 in which the root a ⁱ of the code generation polynomial g (x) is stored, and the ROM 47 is stored. Multiply the root (a ⁱ ) of the code generation polynomial g (x) and the value output from the register 45 by inputting the intermediate value into the galloese adder 43 and as a syndrome S _i . It is comprised including the galoache multiplier 49 which outputs.

The register 45 receives a codeword end signal cw_end through a reset terminal rst and is reset.

Referring to the operation and effects of the syndrome calculation device of the Reed Solomon decoder according to the present invention configured as described above in detail as follows.

The galloise adder 43 adds the depth symbol r ₁ to the intermediate value input from the galloise multiplier 49 and inputs it to the register 45. At this time, the register 45 is reset by receiving the codeword end signal cw_end through the reset terminal rst.

The register 45 latches the value output from the galloche adder 43 according to the symbol clock sym_c1k and inputs the galache multiplier 49. The galloise multiplier 49 multiplies the root a ⁱ of the code generation polynomial g (x) stored in the ROM 47 by the value output from the register 45 and multiplies the intermediate value by the galloise adder 43. Enter

By repeating the process as described above, it will be finally output the syndrome (S _i) in the register (45).

As described above, the present invention has the effect that the structure is simplified by implementing the syndrome calculation cell to change the operation order to remove the multiplexer that is conventionally used to select the root or one of the code polynomial There is.

Claims (1)

A register 11 which sequentially receives the received symbols r _i of the Reed-Solomon-coded received signal r (x) according to a symbol clock, a received symbol ri inputted through the register 11, and a code generation polynomial A lead including a plurality of syndrome calculating cells 13-1 to 13-2t for calculating the roots a ⁰ to a ^2t-1 of g (x) and outputting syndromes S ⁰ to S ^2t-1 . In the syndrome calculation device of the Solomon decoder, a galoche adder 43 for adding the received symbols r _i and the intermediate value of the syndrome calculation cells 13-1 to 13-2t to the register 11 is added. And: Register 45 which latches and outputs the value output from the Galois adder 43 according to the symbol clock sym_c1k: a ROM in which the root a ⁱ of the code generation polynomial g (x) is stored. 47 and: the product to an output value from the root (a ⁱ⁾ and the register 45 of the code generating polynomial g (x) stored in the ROM 47 Loa body multiplier 49 by the syndrome calculation unit in the Reed-Solomon decoder, characterized in that configured including