SU1550531A1 - Device for performing operations on polynominals for ultimate purposes - Google Patents

Abstract

The invention relates to digital computing and can be used in the construction of coding and decoding devices for calculations in finite Galois fields. The purpose of the invention is to expand the functionality of the device by increasing the set of operations performed, as well as providing the possibility of changing the dimension of the field. The goal is achieved by the fact that the device contains registers 1, 2, 4 shift, a generator of 3 pulses, two elements AND-NOT 5, 6, TWO ELEMENTS AND 7, 8 AND ELEMENT OR 9, input 10 input dimension, input 11 input sequence, input 12 of input of a polynomial, input 13 of the installation, input 14 of the recording resolution, input 15 of the launch and output 16 of the operation result. 1 il.

Description

cl

03

The invention relates to specialized computing devices and can be used in the construction of coding and decoding devices for performing calculations in finite Galois fields GF (2 m).

The purpose of the invention is to expand the functionality of the device by increasing the set of operations to be performed by increasing the set of operations to be performed, as well as providing the possibility of changing dimensions.

1} OLYA.

The drawing shows the functional scheme of the device.

The device contains: the first 1 and) second 2 shift registers, the generator of 3 mpuls, the third 4 shift register, Two elements AND-NOT 5, 6, two elements AND 7, 8 and element OR 9.

The device has input 10 of the input variable, input 11 of the input sequence, input 12 of the input of the polynomial, input 3 of the installation, input 14 of the write resolution, input 15 of the start and output 16 of the operation result. Input 10 of the device (to get the Galois field dimension) GF (2P), input 11 for receiving (K-1) is a binary binary sequence, which determines the irreducible | Yulin in the Galois field of a given size {input, input 12 for input of polynomials, go 14 for obtaining the resolution signal write polynomial, input 13 - for the installation of the device in its original state, input 15 - to start the pulse generator.

The device operates as follows.

When performing any operation in the Galois Field, the GF (2h) first sets the dimension of this field. For this, the input 10 of the device receives a signal at the inputs of the first bits of the first 1, second 2, and third 4 shift registers. The signal specifying the dimension of the field is a sequence of length (n-1) of binary symbols, containing a single character in the K th bit, and zeros, K 1, n-1 in all other bits.

Then, the input 11 of the device receives a signal in the form (K.-1), a bit binary sequence, defining an irreducible polynomial in the Galois field of a given dimension, which is fed to the inputs of the second bits of the first shift registers 1, 2 and 4.

five

0

,

0

five

When performing any operation specified in the field, i.e. operations of addition, multiplication and division, the first polynomial in the form of a 1-bit binary sequence 1 1, n is fed through the input 12 of the device to the input of the third bit of the first shift register 1. At the same time, the input 14 of the recording resolution of the device to the input of the recording permission The first shift register 1 receives a signal enabling the writing of the first operand.

To perform the addition operation, the second polynomial is written in the same way, and the result of the addition of two polynomials will be obtained in the first register shift 1.

When the multiplication operation is performed, the second polynomial is written into the bits of the second 2 shift register, for which the input resolution 14 of the device records the input of the recording resolution of the second shift register 2 to enable the recording, and the second polynomial to the third discharge input of the second shift register 2 . A start signal is then provided to the generator start input 15. pulses 3. From the pulse generator output, pulses arrive at the shift inputs of the first 1 and second 2 shift registers until a single polynomial is formed in the second shift register 2. Then, from the output of the first element AND 7, through element 9 OR, a stop signal of the generator of 3 pulses is output, which is fed to its stop input. The result of the multiplication will be recorded in the first shift register 1.

The division operation is performed in the same way as the multiplication operation, except that the second polynomial is written to the third shift register 4, and the pulse generator 3 stop signal is output from the second element 8 AND via element 9 OR to the pulse generator stop input. The result of the division will also be recorded in the first 1 shift register.

To perform the next operation, the device is reset, for which the input of the device to the output of the first 1, second 2, third 4 shift registers is given to set the registers to the zero state.

Claims (1)

Invention Formula A device for performing operations on polynomials in finite fields, containing two shift registers and a pulse generator, characterized in that, in order to expand the functionality of the device by increasing the set, perform time operations, as well as to ensure the possibility of changing the dimensionality of the field, it entered the third shift register, two NAND elements, two AND elements and an OR element, with inputs for entering the dimension, entering the sequence and entering the device polynomial respectively to the inputs of the first, second and The second bits of all shift registers, the setup and write enable inputs of the device correspond respectively to the set inputs O and write enable of all the shift registers whose shift inputs are connected to the output of the pulse generator, the start input of which is the start input of the device, the generator stop input pulse is connected to the code of the OR element, the first input of which is connected to the output of the first element AND, the first input of which is connected to the output of the first bit of the second shift register, and the second input of the element AND is connected to the output of the first NAND element, whose inputs are connected respectively to the outputs of the bits from the second to the nth second shift register (where n is the size of the shift registers is equal to the degree of the polynomial), the second input of the OR element is connected to the output of the second element AND, the first input which is connected to the output of the first bit of the third shift register, and the second input of the AND element is connected to the output of the second NAND element, whose inputs are connected respectively to the outputs of the bits from the second to the nth third shift register, the output of the first shift register Is the output of the device operation result.