SU1658388A1 - Device for residue forming according to number modulus - Google Patents

Abstract

The invention relates to computing. Its use in digital information processing systems (for example, to form elements of finite fields) allows for improved performance. The device contains shapers of 2, 3 pulses, elements OR 5, 4, element 9 of comparison, subtractor 10 and registers 11, 12. Thanks to the introduction of counter 1, elements OR 6-8. registers 13, 14, elements 15-17 and multiplexer 18 in the device a faster computation algorithm is implemented. 1 or t9

Description

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The invention relates to computing and can be used in digital information processing systems, in particular, to form elements of finite fields.

The purpose of the invention is to increase speed.

The drawing shows the functional diagram of the device.

The device contains a counter 1, the first and second drivers 2 and 3 pulses, the first - the fifth elements OR 4-8, the element 9 comparison, the subtractor 10, the first - the fourth registers 11-14, the first - the third elements 15 And 17 and the multiplexer 18 In the drawing, informational inputs 19, inputs 20 of the module assignment, input 21 Start of calculation, output 22 End of calculation, outputs 23 of the result are indicated.

The principle of operation of the device for forming the remainder in an arbitrary modulus of a number is the implementation of the following modulo-numerical algorithm.

From the higher bits of a certain number arriving at the inputs of the device, the code of the selected module is subtracted, if the value of the number formed by these bits is greater than the value of the selected module; if it turns out to be less, then a shift is made to one bit towards the higher bits and the cycle repeats. After subtraction, the difference is written to the place of the decrement in the high-order register, the received code is shifted by one bit towards the high-order bits, and the whole operation is repeated until the lower digits of the number code are shifted to the high-order register, the contents of which after writing the difference of the last subtraction into it will correspond to the code of the result of the calculations, i.e. the magnitude of the remainder of the number of the selected module.

A device for forming a residue of an arbitrary modulus of the number works as follows.

In the initial state, all registers 11-14 are reset. The module by which the formation of residual numbers is carried out is specified by a parallel binary code supplied to the inputs 20 of the device. The inputs 19 of the device receive a number in the parallel binary code, with the older N bits going to the first inputs of the multiplexer 18, and the lower M to N bits to the information inputs of the register 13, (M is the number of bits needed to represent in the parallel binary code of the number from which it is necessary to form the remainder, and N is the number of bits required to represent in the parallel binary

code module). After the codes are supplied, the numbers and the module to the inputs 19 and 20 of the device, to the input 21, the beginning of the calculation is given a pulse, which zeroed the counter 1, wrote the module code into register 12, the lower digit of the code number into register 13, and higher digit code numbers. Since the control input of the multiplexer 18 is affected by a zero potential, its outputs connected to the information

5 inputs of the register 14, are connected with its first inputs. The same impulse. The beginning of the calculation, the passage through the element OR 6, is fed to the input of the imager of 3 pulses. By the cut of the input pulse (i.e. after

0 how the codes of numbers and the module are written into registers 12-14) the pulse shaper 3 will generate a pulse that will allow comparison of the elements of the 9 higher N bits of the number code recorded in the register

5 14, and the module code recorded in register 12. As a result of the comparison, three situations can arise.

a) The code of the number written in register 14 will be less than the code of the module. In this case, the comparison element 9 will generate at its output Less impulse, which, passing through the element OR 7, goes to the first input of the element AND 15, and since the second (inverse) input of the element 15 also affects the zero-potential from the output of the counter 1, this pulse will pass through the element 15 and will go to the shift inputs of registers 13 and 14. In this case, the code of the number in these registers will shift by one bit towards the older ones.

0 bits (register 14 has an N + 1 bit), and the youngest bit of register 14 will overwrite the information from the most significant bit of register 13. The same pulse will go to the counting input of the counter

5 1, which counts it, and to the second input of the element OR 6. From the output of the element OR 6, a pulse arrives at the input of the pulse shaper 3, which, at the cut of the input pulse, will form the next pulse for

0 permitting the operation of reference element 9 and the operation of the device will be repeated.

b) The code of the number written in register 14 will be equal to the code of the module. In this case, the comparison element 9 will issue at its output

5 Equally, the impulse that zeroed the register 14 and the passage through the elements OR 7 and AND 15 will overwrite the information from the most significant register register 13 to the lowest register register 14. This impulse is also counted by counter 1 and through the element OR b

It enters the input of the pulse generator 3, which will form a pulse to enable the operation of the comparison element 9.

c) The code of the number recorded in register 14 will be greater than the code of the module. In this case, the comparison element 9 gives more output to its output. , the module code and outputs a difference code to its information outputs. At the same time, the output of the subtractor of the subtractor 10 appears at the output. A pulse appears that sets the multiplexer 18 to the state of switching its outputs with its second inputs. The same pulse acts through the OR 4 element on the register write 14 input. As a result, the difference code from the outputs of the subtractor 10 is written to register 14. Pulse The end of the subtract also affects the input of the driver 2 pulses. From the input pulse slice (i.e. after writing to register 14) the pulse shaper 2 will generate a pulse which, passing through the elements OR 7 and AND 15, shifts the information in registers 14 and 13 towards the higher bits and rewrites the information from the most significant bit of register 13 to the least significant bit of register 14, and is also counted by counter 1 and fed through the element OR 6 to the input of the driver 3 pulses. By cutting the input pulse, the pulse former 3 will generate a pulse that permits operation of the reference element 9. As soon as counter 1 is filled (its volume is equal to M-N). element 15 will close and pulses from the output of reference element 9 will flow through another circuit. If during the last comparison operation, element 9 gives a pulse to its output Less, then this pulse, the passage through the element OR 8 and the open element AND 17, goes to the input of register 11 recording and to the first input of the element OR 5. At the same time, in register 11 the result of the calculation is written (i.e., the remainder of the selected module from the specified number), and the output of the element OR 5 appears pulse. The end of the calculation indicates that the formation of the residue is complete, its code is written in the output register 11 and the device is ready for follow his calculation cycle. If the comparison element 9 generates a pulse at its output Equals, then this pulse zeroes the register 14, through the open element AND 16 enters the second input of the element OR

5 and zeroes the output register 11. At output 22, a pulse appears. End of calculation. In this case, the remainder of a given number of the selected module will be identical

equals zero. And if the comparison element 9 gives an impulse to its output More, then this impulse allows subtraction of the module code from the code of the number recorded in register 14, the difference will be recorded in register 14, and

further, under the influence of a pulse formed by the shaper of 2 pulses and transmitted through the element OR 8, and the open element AND 17, this difference will be written into the output register 11. At the output 22

a pulse appears. End of calculation, indicating that the outputs of the 23 formed the remainder of the specified number for the selected module, and the device is ready for the next cycle of calculations, in which any other module can be selected and any other number specified.

The technical and economic efficiency of the device in question is to increase the speed of formation of the remainder in an arbitrary modulus of the number. So, for example, when the size of the number M and the width of the module N is known, the device will spend (2M / 2N) .t time units, where t is the sum of the time required

to trigger the compare item, the subtractor, and to write the data to the register. The considered device performs the formation of the remainder of the number on the selected module for (M - N). t units of time.

Considering the value of t is approximately the same in both cases, we estimate the gain B in the speed of the proposed device as compared with the known.

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Claims (1)

Apparatus of the Invention A device for forming a residual modulo an arbitrary modulus of a number containing a comparison element, the output of which is connected to the subtractor’s enable input, the first and second pulse drivers, the first OR element, the first input of which is the input of the device’s calculation and the second inputs of which are combined with the inputs of, respectively, the zeroing and recording resolution of the first register, the outputs of which are the outputs of the device, the second register, the output of the second el The ORP is the output of the device calculating end, characterized in that. that, in order to improve speed, the third and fourth registers, the counter, the third - the fifth OR elements, the first - the third AND elements and the multiplexer, the first information inputs of which and the information inputs of the third register are entered, are entered into the device device inputs, resolution enable entries of the second and third registers are combined with the zeroing input of the counter and the first input of the third OR element and are connected to the input of the device Calculation Start, informational inputs The second register are the inputs of the device module, the outputs of the second register are connected to the first Yokhod of the comparison element and the inputs of the subtracable subtractor, the outputs of which are connected to the second information inputs of the multiplexer, the outputs of which are connected to the installation inputs of the fourth register, whose outputs are connected to the information inputs of the first register, the inputs of the decremented subtractor and the second information inputs of the comparison element, the output of which is less connected to the first inputs of the fourth and of OR elements, outputs of which are respectively connected to the enabling input of the first AND gate and the first input of the third AND gate, outputs its comparison element is connected to the input of the fourth register, the second input of the fourth element OR, and the first input of the second element AND, the output of the work of the subtractor is connected to the control input of the multiplexer, the second input of the first element OR and the input of the first pulse generator, the output of which is connected to the third input of the fourth and second input of the fifth OR element, the outputs of the first OR element and the third register are connected respectively to the recording resolution input and the information input of the fourth register, the output of the first AND element is connected to the shift inputs of the third and fourth registers, the second input of the third element IL And And the counting input of the counter, the output of which is connected to the prohibitory input of the first element And the second inputs of the second and third elements And the outputs of which are connected respectively to the first and second inputs of the second the OR element, the output of the third element OR is connected to the input of the second pulse generator, the output of which is connected to the enabling input of the comparison element.