SU1647871A1 - Threshold gate - Google Patents

Abstract

The invention relates to the field of automotive and computer technology and can be used in the construction of various devices for processing discrete information. The purpose of the invention — an increase in speed — is achieved by the introduction of half-adders 4.1 to 4. p. The device also contains 1 clock pulse generator, multichannel scanning multiplexer 2, trigger 3, element OR 5, counting block b, drives 7.1 - 7.p-1, elements AND 8.1 - 8.p-1, element And 9. element IL AND 10, input information buses 11, information output 12, output 13 of the end of operation of the threshold element. 1 hp ff, 3 ill.

Description

The invention relates to the field of automation and computer technology and can be used in the construction of various devices for processing discrete information.

The aim of the invention is to increase speed.

FIG. 1 shows the threshold element flowchart; in fig. 2 is a block diagram of a threshold element according to claim 2; in fig. 3 - storage scheme.

The threshold element contains 1 clock pulse generator, multichannel scanning multiplexer 2, trigger 3, half adder 4.1 - 4, p, element OR 5, counting unit 6, drives 7.1 - 7.p-1, elements AND 8.1 - 8.p-1, element AND 9, element OR 10, input information bus 11, information output 12, output 13 of the end of operation of the threshold element.

Multichannel scanning multiplexer 2 is connected to the clock input with the output of the generator 1 clock pulses,

information inputs with input information buses 11, stop output - with trigger input 3, i-m and (p + ij-m outputs (f 1, ..., p) - with half-adder inputs 4.I. Sum and transfer outputs of half-adder 4.J 0 1,2 p-1) are connected to

the first and second counting inputs of the accumulator 7J, the first output of which is connected to the first input of an EI element 8.J connected by inputs to the generator 1 clock pulse 1, the output of the trigger 3 and the second outputs of the drives 7.1 to 7J-1, and the output from the subtracting input of the drive 7.J and j-th input of the element OR 5, connected by the r-th input with the output of the sum of half-adder 4.p, and the output with the first counting input of the counting block b. The second counting input of the latter is connected to the transfer output of the half-adder 4.p, and the output to the information output 12 of the threshold element. The second outputs of the threshold element are connected to the inputs of the element And 9 connected by the input with the output of the trigger 3, and the output with the output 13 of the end of the operation of the threshold element.

Xi

00

Xi

The threshold element according to claim 2 contains the element OR 10, the inputs of which are connected to the output of the counting block b and the third outputs of the accumulators 7.1 to 7.p-1, and the output to the information output 12 of the threshold element.

A multichannel scanning multiplexer 2 can be made as in a prototype device in the form of a p / 2p-bit distributor of pulses, the outputs of which are connected to the first inputs of 2p groups of I elements (2p is the number of multiplexer channels). The second inputs of the AND elements of each group are a group of information inputs of the multiplexer, and the outputs are connected to the inputs of the OR element, the output of which is the corresponding multiplexer output (output of the corresponding channel). The pulse clock distributor input is the clock input of the scanning multiplexer, and the last bit of the pulse distributor output is the stop output of the scanning multiplexer.

A multichannel scanning multiplexer can also be made in the form of 2p shift registers connected by information inputs to the information inputs of the scanning multiplexer, clock inputs with its clock input, and transfer outputs to the information outputs of the scanning multiplexer. The inverse outputs of each shift register are connected to the inputs of their AND element, and the outputs of the latter are connected to the inputs of the AND element, the output of which is the stop output of the scanning multiplexer. The enable inputs of the write shift registers are connected to the write input of the scanning multiplexer.

Drive 7J is generally performed as a reversible binary counter for min (Jloga 1), 11od2 (a + + 1)) t bits, which has summing and subtracting count inputs of the first digit, as well as count input of the second digit, connected in parallel with the output of the transfer of the first bit in the summation mode and being the second summing counting input of the accumulator. In the initial state, the number qi 0 is written to the accumulator. The direct outputs of the counter bits with numbers equal to the numbers of the single bits in the binary representation of the number qi and the inverse outputs of the remaining bits are connected to the inputs of the AND element, the direct output of which is the second the output of the drive, and the inverse - its first output (outputs 14 and 15 in Fig. 3).

When performing a threshold element in accordance with claim 2

either qi-a is selected, while the third output of the accumulator is the forward output of the highest bit of the counter (see output 16 in Fig. 3), or the outputs of the counter are connected to the inputs of the threshold shaping unit (direct outputs of the counter bits) that implements a threshold function with weights of inputs 21 and a threshold a at + qi, where a is the threshold of the function implemented by the threshold element.

5 The threshold shaping unit can be performed as follows.

Let the binary representation be

 .

  one

Let ... 0, a oi 1. Inputs of the block, starting with f-ro and up to j-ro, such that at 034-1 5.. . aj 1, and

5 U +1 O are connected to the inputs of the element I, the output of which, as well as the inputs of the block, starting from (J + 1) -th and up to the 1st, such that a -y u 4-2 ...- (% - 0, and "1 + 1 1, connected to the inputs of the element

0 OR, the output of which, as well as the inputs of the block, starting from (i + 1) -th and to t-ro, such that +1 +1 at 4-2 ... with 1, and cq +1 0, are centered with the inputs element And, the output of which, as well as the inputs of the block, starting with

5 (I + 1) -Go and ending with the input with number t, such that ... 0, and #t + 1 1, are connected to the inputs of the OR element, and so on until all are combined

 inputs of the block forming the threshold (direct output of the counter). If "and 1, the last is the element AND, O, the last is the element OR. In the particular case, when a 2P block of the form 5, the threshold is performed as an OR element connected by inputs to the block inputs from (p + 1) -th to the -th. In the particular case, cpp-1 0, + i ..., the block forming the threshold is executed as an element And connected by inputs with the inputs of the block from the p-th dri-go. When a, the threshold formation unit is executed as a communication line from its i-ro input to the output,

5 Counting block 6 is performed as a sum counter on / 3 IfXfc (a 4-1) bits. It may have any of the known circuit implementations of the counter. The difference between the used counter is the presence of the second counting input connected to the counting input of the second discharge of the counter in parallel with the transfer from the first discharge. Such a counter can be performed, for example, on Tt-flip-flops connected in series, with the transfer output of each trigger connected to the transfer input (counting input) of the next trigger, the transfer output of the first trigger connected to the transfer input (counting input) of the second trigger via the OR element, the second input of which is the second counting input of the counting unit. In the initial state, the code of the number q 0 is recorded in the counter.

When q 2 1 is selected, the forward output of the high bit of the counter is the output of the counting node. Otherwise, the forward outputs of the counter are connected to the inputs of the threshold generation unit, equal to q + a, implemented in the order described above, the output of which is the output of the counting unit.

Trigger 3, as in the prototype device, is performed as an RS trigger when implementing a multichannel scanning multiplexer on shift registers or when implementing it on a pulse distributor, when a pulse at the output of the stop is synchronized with a pause between clock pulses, or as a counting trigger when the multichannel scanning multiplexer is executed on the pulse distributor, and the pulse at the stop output is synchronized with the clock pulse.

The proposed threshold element functions as follows.

In the initial state, the multichannel scanning multiplexer 2, the counting unit 6, the accumulators 7 and the trigger 3 are reset. At the same time, at the output of the trigger there is a zero signal blocking the passage of clock pulses through the elements of 8. When the scanning multiplexer 2 is executed on the shift registers, the input code from the input information buses 11 is written to the shift registers.

Upon receipt of clock pulses from the output of the clock generator 1 to the clock input of the multichannel scanning multiplexer 2, the latter converts the parallel code supplied to the group of input information buses 11.1 (inputs of the 1st channel of the scanning multiplexer 2) into a sequence of pulses at its 1st output ( output (th channel). Moreover, during the time of operation of multiplexer 2, at its 1st output a number of pulses is formed equal to the number of single signals on the group of input information buses 11.1.

The pulses from the 1st and (p + outputs of the scanning multiplexer 2 arrive at the inputs of the half adder 4.1. If a pulse arrives at one of its inputs, this causes an impulse at its output of the sum connected to the first counting input of the accumulator 7.1, at Cr and the first the counting input of the accumulator of the counting unit 6 through the element OR 5 at I p, to the contents of which the unit is added to 10. If a pulse arrives at both inputs of half-accumulator 4.I, this causes a pulse at its transfer output connected to the second summing counting input of the accumulator 7.I with p and sche Foot

5 of block 6 with I p, to the contents of which is added the number two.

If during the operation of the scanning multiplexer 2, the inputs of the half-adder 4.p receive no less than a pulse, then

At the output of the counting unit 6, a single signal is generated, which arrives at the output 12 of the threshold element, which is the result of the operation and at the same time indicates the end of the operation cycle.

5 The result is removed from the output 12 of the counting unit 6. If during the operation of the scanning multiplexer 2 in the counting unit 6 there is no accumulation of the required number of pulses, then the operation continues in the order described above until all input information buses are polled, which will require} n / 2p cycles, where p is the width of the input code. At the same time, upon completion of the multichannel scanning

5 of the multiplexer 2, it blocks itself and then does not generate pulses on its information outputs. In this case, at its stop output, a pulse is formed, which switches on trigger 3 (in the pause between such pulses). In this case, a single signal appears at the output of trigger 3, allowing the passage of clock pulses through AND elements 8.

Then the process of sequential recalculation of the contents of drives 7 into the counting block 6 occurs. Let 7.1 be the smallest number of the drive in which the code is written that is different from the original qi, i.e. during the operation of the multichannel scanning multiplexer 2, pulses arrive at its counting inputs, while at its first output, connected to the input of the And 8 element, there is a single signal, and at the second, connected to the inputs of the And 8.1 + 1 elements, 8.p -1, - zero, prohibiting the passage of clock pulses to their outputs. Thus, at all inputs of the element AND 8.I connected to the second outputs of accumulators 7.1-7.1-1, there are single signals. The resulting clock

the pulses pass through the element AND 8.I to the subtracting counting input of the accumulator 7.1, from the contents of which one is subtracted, and through the element OR 5 to the counting input (first) of the counting unit 6, to the contents of which is added one. Work continues in this manner until the accumulator 7. returns to its original state. In this case, a zero signal appears at its first output, prohibiting the further passage of clock pulses at the output of the AND 8.1 element, and at the second output - a single signal permitting the passage of clock pulses at the outputs of the AND 8.1 + 1 elements - 8.p-1. Further, the contents of the drives 7.I + 1 - 7.p-1 are counted in the same way as counting unit 6.

P

If Ј xi - a 1 then at some point

i 1

time in the counter of the counting block will be recorded the code of the number q + a, where q is the code of the number of the initial state of the counter of the counting block 6. At the output of the counting block b there appears a single signal arriving at the output 12 of the threshold element resulting from and indicating the end of the work cycle.

If Ј xi a, then at the end of the first 1

Counting the contents of all the accumulators 7 into the counting unit 6 at their second outputs are single signals indicating their return to the initial state, which causes a single signal at the output of the AND 9 element, indicating the end of the operation cycle and arriving at the output 13 of the end of the threshold element .

In this case, a zero output signal is removed from the output 12 of the threshold element.

P

Thus, when Ј xi and at the output i 1

a single signal is generated at the threshold, and zero otherwise.

In the case of a device according to claim 2, the operation of the threshold element is performed in the same order as described above.

The difference is that when a number of pulses 4.1 equal to threshold a or a + 1 is received at the inputs of some half adder 4.1, a counter of the corresponding number will be recorded in accumulator 7.I counter, which causes a single signal at its third output to enter the element OR 10 what causes it to exit

12, which is the information output of the threshold element, a single signal resulting from the operation and indicating the end of the operation cycle.

The operation of the threshold element ends when a single signal appears at one of the outputs 12 or 13. The result is removed from the information output 12 of the threshold element.

0 Thus, a single signal is generated at the output of the threshold element if the number of single signals at its inputs is greater than or equal to the threshold, otherwise, a zero signal is generated at the output of the threshold element.

Threshold element provides increased speed.

Claims (2)

1. A threshold element containing 0 multichannel scanning multiplexer connected by a clock input to the output of a clock generator, information inputs with input information buses, a stop output with a trigger input, an OR element connected by an output to the counting input of the counting unit whose output is informational the output of the threshold element, p-1 drives and p elements And, 0 the first output of the 1st accumulator is connected to the input of the 1st element I, the output of which is connected to the i-th input of the OR element and the subtractive input of the 1st accumulator, and the inputs to the output of the clock generator, 5 triggers and second outputs of accumulators from the first to (M) -th, second outputs of accumulators are connected to the inputs of the element I, the output of which is connected to the output The end of the threshold element, and the input 0 with the output of the trigger, in order to improve speed , p-1 half adders have been entered into it, and the inputs of the 1st half adder are connected to the i-th and (p + 1) -th information outputs of the 5 multi-channel scanning multiplexer (1 1.2 p), the output amount the p-th half-adder is connected to the input of the OR element, and the transfer output is connected to the second summing input of the counting unit, the sum and transfer outputs j-ro of the half-adder 0 1-2 ... p-1) are connected to the first and second summing inputs j -ro accumulator. 2. An element according to claim 1, characterized in that, in order to increase speed, the third outputs of the accumulators are connected to the inputs of the second OR element, which is connected by input to the output of the counting unit, and the output to the information output of the threshold element. j / j j one Јj